Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Bo Shen | 7ca6f36 | 2014-02-09 15:52:39 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Configuration settings for the SAMA5D3 Xplained board. |
| 4 | * |
| 5 | * Copyright (C) 2014 Atmel Corporation |
| 6 | * Bo Shen <voice.shen@atmel.com> |
Bo Shen | 7ca6f36 | 2014-02-09 15:52:39 +0800 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #ifndef __CONFIG_H |
| 10 | #define __CONFIG_H |
| 11 | |
Fabien Lehoussel | df1cf77 | 2020-02-24 16:45:31 +0100 | [diff] [blame] | 12 | #include <linux/sizes.h> |
Wu, Josh | b2d387b | 2015-03-30 14:51:19 +0800 | [diff] [blame] | 13 | #include "at91-sama5_common.h" |
Bo Shen | 7ca6f36 | 2014-02-09 15:52:39 +0800 | [diff] [blame] | 14 | |
Bo Shen | 7ca6f36 | 2014-02-09 15:52:39 +0800 | [diff] [blame] | 15 | /* |
| 16 | * This needs to be defined for the OHCI code to work but it is defined as |
| 17 | * ATMEL_ID_UHPHS in the CPU specific header files. |
| 18 | */ |
Wenyou Yang | e61ed48 | 2017-09-14 11:07:42 +0800 | [diff] [blame] | 19 | #define ATMEL_ID_UHP 32 |
Bo Shen | 7ca6f36 | 2014-02-09 15:52:39 +0800 | [diff] [blame] | 20 | |
| 21 | /* |
| 22 | * Specify the clock enable bit in the PMC_SCER register. |
| 23 | */ |
Wenyou Yang | e61ed48 | 2017-09-14 11:07:42 +0800 | [diff] [blame] | 24 | #define ATMEL_PMC_UHP (1 << 6) |
Bo Shen | 7ca6f36 | 2014-02-09 15:52:39 +0800 | [diff] [blame] | 25 | |
Bo Shen | 7ca6f36 | 2014-02-09 15:52:39 +0800 | [diff] [blame] | 26 | /* SDRAM */ |
Wenyou Yang | e61ed48 | 2017-09-14 11:07:42 +0800 | [diff] [blame] | 27 | #define CONFIG_SYS_SDRAM_BASE 0x20000000 |
Bo Shen | 7ca6f36 | 2014-02-09 15:52:39 +0800 | [diff] [blame] | 28 | #define CONFIG_SYS_SDRAM_SIZE 0x10000000 |
| 29 | |
Bo Shen | cd23aac4 | 2014-03-19 14:48:45 +0800 | [diff] [blame] | 30 | #ifdef CONFIG_SPL_BUILD |
Wenyou Yang | 1878804 | 2017-04-14 08:51:45 +0800 | [diff] [blame] | 31 | #define CONFIG_SYS_INIT_SP_ADDR 0x318000 |
Bo Shen | cd23aac4 | 2014-03-19 14:48:45 +0800 | [diff] [blame] | 32 | #else |
Bo Shen | 7ca6f36 | 2014-02-09 15:52:39 +0800 | [diff] [blame] | 33 | #define CONFIG_SYS_INIT_SP_ADDR \ |
Wenyou Yang | 1878804 | 2017-04-14 08:51:45 +0800 | [diff] [blame] | 34 | (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) |
Bo Shen | cd23aac4 | 2014-03-19 14:48:45 +0800 | [diff] [blame] | 35 | #endif |
Bo Shen | 7ca6f36 | 2014-02-09 15:52:39 +0800 | [diff] [blame] | 36 | |
| 37 | /* NAND flash */ |
Bo Shen | 7ca6f36 | 2014-02-09 15:52:39 +0800 | [diff] [blame] | 38 | #ifdef CONFIG_CMD_NAND |
Bo Shen | 7ca6f36 | 2014-02-09 15:52:39 +0800 | [diff] [blame] | 39 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
Wenyou Yang | e61ed48 | 2017-09-14 11:07:42 +0800 | [diff] [blame] | 40 | #define CONFIG_SYS_NAND_BASE 0x60000000 |
Bo Shen | 7ca6f36 | 2014-02-09 15:52:39 +0800 | [diff] [blame] | 41 | /* our ALE is AD21 */ |
| 42 | #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) |
| 43 | /* our CLE is AD22 */ |
| 44 | #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) |
Tom Rini | 8f1a80e | 2017-07-28 21:31:42 -0400 | [diff] [blame] | 45 | #endif |
Bo Shen | 7ca6f36 | 2014-02-09 15:52:39 +0800 | [diff] [blame] | 46 | |
Bo Shen | 7ca6f36 | 2014-02-09 15:52:39 +0800 | [diff] [blame] | 47 | /* USB */ |
Bo Shen | 7ca6f36 | 2014-02-09 15:52:39 +0800 | [diff] [blame] | 48 | #ifdef CONFIG_CMD_USB |
| 49 | #define CONFIG_USB_ATMEL |
| 50 | #define CONFIG_USB_ATMEL_CLK_SEL_UPLL |
| 51 | #define CONFIG_USB_OHCI_NEW |
| 52 | #define CONFIG_SYS_USB_OHCI_CPU_INIT |
Wenyou Yang | e61ed48 | 2017-09-14 11:07:42 +0800 | [diff] [blame] | 53 | #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00600000 |
Bo Shen | 7ca6f36 | 2014-02-09 15:52:39 +0800 | [diff] [blame] | 54 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "SAMA5D3 Xplained" |
| 55 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 |
Bo Shen | 7ca6f36 | 2014-02-09 15:52:39 +0800 | [diff] [blame] | 56 | #endif |
| 57 | |
Bo Shen | cd23aac4 | 2014-03-19 14:48:45 +0800 | [diff] [blame] | 58 | /* SPL */ |
Wenyou Yang | 1878804 | 2017-04-14 08:51:45 +0800 | [diff] [blame] | 59 | #define CONFIG_SPL_MAX_SIZE 0x18000 |
Bo Shen | cd23aac4 | 2014-03-19 14:48:45 +0800 | [diff] [blame] | 60 | #define CONFIG_SPL_BSS_START_ADDR 0x20000000 |
| 61 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 |
| 62 | #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 |
| 63 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 |
| 64 | |
Fabien Lehoussel | df1cf77 | 2020-02-24 16:45:31 +0100 | [diff] [blame] | 65 | /* size of u-boot.bin to load */ |
| 66 | #define CONFIG_SYS_MONITOR_LEN (2 * SZ_512K) |
Bo Shen | cd23aac4 | 2014-03-19 14:48:45 +0800 | [diff] [blame] | 67 | |
Wenyou Yang | 5541543 | 2017-09-14 11:07:44 +0800 | [diff] [blame] | 68 | #ifdef CONFIG_SD_BOOT |
Guillaume GARDET | 205b4f3 | 2014-10-15 17:53:11 +0200 | [diff] [blame] | 69 | #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" |
Wenyou Yang | 5541543 | 2017-09-14 11:07:44 +0800 | [diff] [blame] | 70 | #endif |
Bo Shen | cd23aac4 | 2014-03-19 14:48:45 +0800 | [diff] [blame] | 71 | |
Michael Opdenacker | ea83ea5 | 2021-05-31 23:23:48 +0200 | [diff] [blame] | 72 | /* Falcon boot support on raw MMC */ |
| 73 | #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x100 /* 128 KiB */ |
| 74 | #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) |
| 75 | /* U-Boot proper stored by default at 0x200 (256 KiB) */ |
Michael Opdenacker | ea83ea5 | 2021-05-31 23:23:48 +0200 | [diff] [blame] | 76 | #define CONFIG_SYS_SPL_ARGS_ADDR 0x22000000 |
| 77 | |
| 78 | /* Falcon boot support on FAT on MMC */ |
| 79 | #define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" |
| 80 | #define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" |
| 81 | |
| 82 | /* Falcon boot support on raw NAND */ |
| 83 | #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x1a0000 |
| 84 | |
Bo Shen | cd23aac4 | 2014-03-19 14:48:45 +0800 | [diff] [blame] | 85 | #endif |