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wdenk73a8b272003-06-05 19:27:42 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2003-2005
wdenk73a8b272003-06-05 19:27:42 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31
32/*
33 * High Level Configuration Options
34 * (easy to change)
35 */
36
37#undef CONFIG_MPC860
38#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
39#define CONFIG_RPXLITE 1 /* RMU is the RPXlite clone */
40#define CONFIG_RMU 1
41
Wolfgang Denk2ae18242010-10-06 09:05:45 +020042#define CONFIG_SYS_TEXT_BASE 0xfff00000
43
wdenk73a8b272003-06-05 19:27:42 +000044#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
45#undef CONFIG_8xx_CONS_SMC2
46#undef CONFIG_8xx_CONS_NONE
47#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */
48#if 0
49#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
50#else
51#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
52#endif
53
wdenk73a8b272003-06-05 19:27:42 +000054#undef CONFIG_BOOTARGS
55#define CONFIG_BOOTCOMMAND \
Wolfgang Denk53677ef2008-05-20 16:00:29 +020056 "bootp; " \
57 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
58 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
wdenk73a8b272003-06-05 19:27:42 +000059 "bootm"
60
61#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020062#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenk73a8b272003-06-05 19:27:42 +000063
wdenkca75add2003-08-29 10:05:53 +000064/* enable I2C and select the hardware/software driver */
65#undef CONFIG_HARD_I2C /* I2C with hardware support */
66#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
67
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020068#define CONFIG_SYS_I2C_SPEED 40000 /* 40 kHz is supposed to work */
69#define CONFIG_SYS_I2C_SLAVE 0xFE
wdenkca75add2003-08-29 10:05:53 +000070
71/* Software (bit-bang) I2C driver configuration */
72#define PB_SCL 0x00000020 /* PB 26 */
73#define PB_SDA 0x00000010 /* PB 27 */
74
75#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
76#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
77#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
78#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
79#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
80 else immr->im_cpm.cp_pbdat &= ~PB_SDA
81#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
82 else immr->im_cpm.cp_pbdat &= ~PB_SCL
83#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
84
85/* M41T11 Serial Access Timekeeper(R) SRAM */
86#define CONFIG_RTC_M41T11 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087#define CONFIG_SYS_I2C_RTC_ADDR 0x68
88#define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with the linux driver */
wdenkca75add2003-08-29 10:05:53 +000089
wdenk73a8b272003-06-05 19:27:42 +000090#undef CONFIG_WATCHDOG /* watchdog disabled */
91
Jon Loeliger90cc3eb2007-07-04 22:33:23 -050092
93/*
94 * Command line configuration.
95 */
96#include <config_cmd_default.h>
97
98#define CONFIG_CMD_DATE
99#define CONFIG_CMD_DHCP
100#define CONFIG_CMD_I2C
101#define CONFIG_CMD_NFS
102#define CONFIG_CMD_SNTP
103
wdenkca75add2003-08-29 10:05:53 +0000104
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -0500105/*
106 * BOOTP options
107 */
108#define CONFIG_BOOTP_SUBNETMASK
109#define CONFIG_BOOTP_GATEWAY
110#define CONFIG_BOOTP_HOSTNAME
111#define CONFIG_BOOTP_BOOTPATH
112#define CONFIG_BOOTP_BOOTFILESIZE
113
wdenk73a8b272003-06-05 19:27:42 +0000114
wdenkaf6d1df2003-12-03 23:53:42 +0000115#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */
Stefan Roesef2302d42008-08-06 14:05:38 +0200116#define CONFIG_AUTOBOOT_PROMPT \
117 "\nEnter password - autoboot in %d sec...\n", bootdelay
wdenkaf6d1df2003-12-03 23:53:42 +0000118#define CONFIG_AUTOBOOT_DELAY_STR "system"
119
wdenk73a8b272003-06-05 19:27:42 +0000120/*
121 * Miscellaneous configurable options
122 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_LONGHELP /* undef to save memory */
124#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger90cc3eb2007-07-04 22:33:23 -0500125#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk73a8b272003-06-05 19:27:42 +0000127#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk73a8b272003-06-05 19:27:42 +0000129#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
131#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
132#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk73a8b272003-06-05 19:27:42 +0000133
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_MEMTEST_START 0x0040000 /* memtest works on */
135#define CONFIG_SYS_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */
wdenk73a8b272003-06-05 19:27:42 +0000136
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenk73a8b272003-06-05 19:27:42 +0000138
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk73a8b272003-06-05 19:27:42 +0000140
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenk73a8b272003-06-05 19:27:42 +0000142
143/*
144 * Low Level Configuration Settings
145 * (address mappings, register initial values, etc.)
146 * You should know what you are doing if you make changes here.
147 */
148/*-----------------------------------------------------------------------
149 * Internal Memory Mapped Register
150 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_IMMR 0xFA200000
wdenk73a8b272003-06-05 19:27:42 +0000152
153/*-----------------------------------------------------------------------
154 * Definitions for initial stack pointer and data area (in DPRAM)
155 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200157#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200159#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk73a8b272003-06-05 19:27:42 +0000161
162/*-----------------------------------------------------------------------
163 * Start addresses for the final memory configuration
164 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk73a8b272003-06-05 19:27:42 +0000166 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_SDRAM_BASE 0x00000000
168#define CONFIG_SYS_FLASH_BASE (0-flash_info[0].size) /* Put flash at end */
Jon Loeliger90cc3eb2007-07-04 22:33:23 -0500169#if defined(DEBUG) || defined(CONFIG_CMD_IDE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
wdenk73a8b272003-06-05 19:27:42 +0000171#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
wdenk73a8b272003-06-05 19:27:42 +0000173#endif
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200174#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenk73a8b272003-06-05 19:27:42 +0000176
177/*
178 * For booting Linux, the board info and command line data
179 * have to be in the first 8 MB of memory, since this is
180 * the maximum mapped by the Linux kernel during initialization.
181 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk73a8b272003-06-05 19:27:42 +0000183
184/*-----------------------------------------------------------------------
185 * FLASH organization
186 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
188#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
wdenk73a8b272003-06-05 19:27:42 +0000189
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
191#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenk73a8b272003-06-05 19:27:42 +0000192
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200193#define CONFIG_ENV_IS_IN_FLASH 1
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200194#define CONFIG_ENV_ADDR ((CONFIG_SYS_TEXT_BASE) + 0x40000)
Wolfgang Denk3a76ab52009-06-10 00:15:11 +0200195#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
196#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE /* Used size for environment */
wdenk73a8b272003-06-05 19:27:42 +0000197
198/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200199#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
200#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
wdenk73a8b272003-06-05 19:27:42 +0000201
202/*-----------------------------------------------------------------------
wdenkca75add2003-08-29 10:05:53 +0000203 * Reset address
204 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_RESET_ADDRESS ((ulong)((((immap_t *)CONFIG_SYS_IMMR)->im_clkrst.res)))
wdenkca75add2003-08-29 10:05:53 +0000206
207/*-----------------------------------------------------------------------
wdenk73a8b272003-06-05 19:27:42 +0000208 * Cache Configuration
209 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger90cc3eb2007-07-04 22:33:23 -0500211#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenk73a8b272003-06-05 19:27:42 +0000213#endif
214
215/*-----------------------------------------------------------------------
216 * SYPCR - System Protection Control 11-9
217 * SYPCR can only be written once after reset!
218 *-----------------------------------------------------------------------
219 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
220 */
221#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenk73a8b272003-06-05 19:27:42 +0000223 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
224#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenk73a8b272003-06-05 19:27:42 +0000226#endif
227
228/*-----------------------------------------------------------------------
229 * SIUMCR - SIU Module Configuration 11-6
230 *-----------------------------------------------------------------------
231 * PCMCIA config., multi-function pin tri-state
232 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_SIUMCR (SIUMCR_MLRC10)
wdenk73a8b272003-06-05 19:27:42 +0000234
235/*-----------------------------------------------------------------------
236 * TBSCR - Time Base Status and Control 11-26
237 *-----------------------------------------------------------------------
238 * Clear Reference Interrupt Status, Timebase freezing enabled
239 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
wdenk73a8b272003-06-05 19:27:42 +0000241
242/*-----------------------------------------------------------------------
243 * RTCSC - Real-Time Clock Status and Control Register 11-27
244 *-----------------------------------------------------------------------
245 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246/*%%%#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
247#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_RTE)
wdenk73a8b272003-06-05 19:27:42 +0000248
249/*-----------------------------------------------------------------------
250 * PISCR - Periodic Interrupt Status and Control 11-31
251 *-----------------------------------------------------------------------
252 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
253 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenk73a8b272003-06-05 19:27:42 +0000255
256/*-----------------------------------------------------------------------
257 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
258 *-----------------------------------------------------------------------
259 * Reset PLL lock status sticky bit, timer expired status bit and timer
260 * interrupt status bit
261 *
262 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
263 */
264/* up to 50 MHz we use a 1:1 clock */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
wdenk73a8b272003-06-05 19:27:42 +0000266
267/*-----------------------------------------------------------------------
268 * SCCR - System Clock and reset Control Register 15-27
269 *-----------------------------------------------------------------------
270 * Set clock output, timebase and RTC source and divider,
271 * power management and some other internal clocks
272 */
273#define SCCR_MASK SCCR_EBDF00
274/* up to 50 MHz we use a 1:1 clock */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_TBS)
wdenk73a8b272003-06-05 19:27:42 +0000276
277/*-----------------------------------------------------------------------
278 * PCMCIA stuff
279 *-----------------------------------------------------------------------
280 *
281 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
283#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
284#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
285#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
286#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
287#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
288#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
289#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenk73a8b272003-06-05 19:27:42 +0000290
291/*-----------------------------------------------------------------------
292 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
293 *-----------------------------------------------------------------------
294 */
295
296#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
297
298#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
299#undef CONFIG_IDE_LED /* LED for ide not supported */
300#undef CONFIG_IDE_RESET /* reset for ide not supported */
301
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
303#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenk73a8b272003-06-05 19:27:42 +0000304
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenk73a8b272003-06-05 19:27:42 +0000306
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenk73a8b272003-06-05 19:27:42 +0000308
309/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenk73a8b272003-06-05 19:27:42 +0000311
312/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenk73a8b272003-06-05 19:27:42 +0000314
315/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200316#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenk73a8b272003-06-05 19:27:42 +0000317
318/*-----------------------------------------------------------------------
319 *
320 *-----------------------------------------------------------------------
321 *
322 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323/*#define CONFIG_SYS_DER 0x2002000F*/
324#define CONFIG_SYS_DER 0
wdenk73a8b272003-06-05 19:27:42 +0000325
326/*
327 * Init Memory Controller:
328 *
329 * BR0 and OR0 (FLASH)
330 */
331
wdenk7e780362004-04-08 22:31:29 +0000332#define FLASH_BASE_PRELIM 0xFC000000 /* FLASH base - up to 64 MB of flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200333#define CONFIG_SYS_PRELIM_OR_AM 0xFC000000 /* OR addr mask - map 64 MB */
wdenk73a8b272003-06-05 19:27:42 +0000334
335/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
wdenk73a8b272003-06-05 19:27:42 +0000337
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200338#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
339#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
wdenk73a8b272003-06-05 19:27:42 +0000340
341/*
342 * BR1 and OR1 (SDRAM)
343 *
344 */
345#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */
wdenkd94f92c2003-08-28 09:41:22 +0000346#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB */
wdenk73a8b272003-06-05 19:27:42 +0000347
348/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200349#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000E00
wdenk73a8b272003-06-05 19:27:42 +0000350
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200351#define CONFIG_SYS_OR1_PRELIM (0xF0000000 | CONFIG_SYS_OR_TIMING_SDRAM ) /* map 256 MB */
352#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenk73a8b272003-06-05 19:27:42 +0000353
354/* RPXLITE mem setting */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200355#define CONFIG_SYS_NVRAM_BASE 0xFA000000 /* NVRAM & SRAM base */
wdenk7e780362004-04-08 22:31:29 +0000356/* IMMR: 0xFA200000 IMMR base address - see above */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200357#define CONFIG_SYS_BCSR_BASE 0xFA400000 /* BCSR base address */
wdenk7e780362004-04-08 22:31:29 +0000358
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200359#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_BASE | BR_V) /* BCSR */
360#define CONFIG_SYS_OR3_PRELIM 0xFFFF8910
361#define CONFIG_SYS_BR4_PRELIM (CONFIG_SYS_NVRAM_BASE | BR_PS_8 | BR_V) /* NVRAM & SRAM */
362#define CONFIG_SYS_OR4_PRELIM 0xFFFE0970
wdenk73a8b272003-06-05 19:27:42 +0000363
364/*
365 * Memory Periodic Timer Prescaler
366 */
367
368/* periodic timer for refresh */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369#define CONFIG_SYS_MAMR_PTA 20
wdenk73a8b272003-06-05 19:27:42 +0000370
371/*
372 * Refresh clock Prescalar
373 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200374#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV2
wdenk73a8b272003-06-05 19:27:42 +0000375
376/*
377 * MAMR settings for SDRAM
378 */
379
wdenkd94f92c2003-08-28 09:41:22 +0000380/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200381#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenk73a8b272003-06-05 19:27:42 +0000382 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
383 MAMR_RLFA_16X | MAMR_WLFA_16X | MAMR_TLFA_16X)
384
385/*
wdenk73a8b272003-06-05 19:27:42 +0000386 * BCSRx
387 *
388 * Board Status and Control Registers
389 *
390 */
391
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200392#define BCSR0 (CONFIG_SYS_BCSR_BASE + 0)
393#define BCSR1 (CONFIG_SYS_BCSR_BASE + 1)
394#define BCSR2 (CONFIG_SYS_BCSR_BASE + 2)
395#define BCSR3 (CONFIG_SYS_BCSR_BASE + 3)
wdenk73a8b272003-06-05 19:27:42 +0000396
397#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200398#define BCSR0_ENNVRAM 0x02 /* CS4# Control */
wdenk73a8b272003-06-05 19:27:42 +0000399#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */
400#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */
401#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */
402#define BCSR0_COLTEST 0x20
403#define BCSR0_ETHLPBK 0x40
404#define BCSR0_ETHEN 0x80
405
406#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */
407#define BCSR1_PCVCTL6 0x02
408#define BCSR1_PCVCTL5 0x04
409#define BCSR1_PCVCTL4 0x08
410#define BCSR1_IPB5SEL 0x10
411
412#define BCSR2_ENPA5HDR 0x08 /* USB Control */
413#define BCSR2_ENUSBCLK 0x10
414#define BCSR2_USBPWREN 0x20
415#define BCSR2_USBSPD 0x40
416#define BCSR2_USBSUSP 0x80
417
418#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */
419#define BCSR3_BWNVR 0x02 /* NVRAM Battery */
420#define BCSR3_RDY_BSY 0x04 /* Flash Operation */
421#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */
422#define BCSR3_D27 0x10 /* Dip Switch settings */
423#define BCSR3_D26 0x20
424#define BCSR3_D25 0x40
425#define BCSR3_D24 0x80
426
427#endif /* __CONFIG_H */