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Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +01001/*
2 * (C) Copyright 2000-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2006
6 * Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27/*
28 * board/config.h - configuration options, board specific
29 */
30
31#ifndef __CONFIG_H
32#define __CONFIG_H
33
34/*
35 * High Level Configuration Options
36 * (easy to change)
37 */
38
39#define CONFIG_MPC885 1 /* This is a MPC885 CPU */
40#define CONFIG_TQM885D 1 /* ...on a TQM88D module */
41#define CONFIG_TK885D 1 /* ...in a TK885D base board */
42
Wolfgang Denk2ae18242010-10-06 09:05:45 +020043#define CONFIG_SYS_TEXT_BASE 0x40000000
44
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +010045#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020046#define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */
47#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +010048#define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 66 MHz - CPU default clock */
49 /* (it will be used if there is no */
50 /* 'cpuclk' variable with valid value) */
51
52#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
Wolfgang Denk3cb7a482009-07-28 22:13:52 +020053#define CONFIG_SYS_SMC_RXBUFLEN 128
54#define CONFIG_SYS_MAXIDLE 10
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +010055#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
56
57#define CONFIG_BOOTCOUNT_LIMIT
58
59#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
60
61#define CONFIG_BOARD_TYPES 1 /* support board types */
62
63#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010064 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +010065 "echo"
66
67#undef CONFIG_BOOTARGS
68
69#define CONFIG_EXTRA_ENV_SETTINGS \
Heiko Schocher48690d82010-07-20 17:45:02 +020070 "ethprime=FEC\0" \
71 "ethact=FEC\0" \
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +010072 "netdev=eth0\0" \
73 "nfsargs=setenv bootargs root=/dev/nfs rw " \
74 "nfsroot=${serverip}:${rootpath}\0" \
75 "ramargs=setenv bootargs root=/dev/ram rw\0" \
76 "addip=setenv bootargs ${bootargs} " \
77 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
78 ":${hostname}:${netdev}:off panic=1\0" \
79 "flash_nfs=run nfsargs addip;" \
80 "bootm ${kernel_addr}\0" \
81 "flash_self=run ramargs addip;" \
82 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
83 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
84 "rootpath=/opt/eldk/ppc_8xx\0" \
Wolfgang Denk2b4f7782008-01-15 17:21:28 +010085 "bootfile=/tftpboot/tk885d/uImage\0" \
86 "u-boot=/tftpboot/tk885d/u-boot.bin\0" \
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +010087 "kernel_addr=40080000\0" \
88 "ramdisk_addr=40180000\0" \
89 "load=tftp 200000 ${u-boot}\0" \
90 "update=protect off 40000000 +${filesize};" \
91 "erase 40000000 +${filesize};" \
92 "cp.b 200000 40000000 ${filesize};" \
93 "protect on 40000000 +${filesize}\0" \
94 ""
95#define CONFIG_BOOTCOMMAND "run flash_self"
96
97#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +010099
100#undef CONFIG_WATCHDOG /* watchdog disabled */
101
102#define CONFIG_STATUS_LED 1 /* Status LED enabled */
103
104#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
105
106/* enable I2C and select the hardware/software driver */
107#undef CONFIG_HARD_I2C /* I2C with hardware support */
108#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
109
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */
111#define CONFIG_SYS_I2C_SLAVE 0xFE
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100112
113#ifdef CONFIG_SOFT_I2C
114/*
115 * Software (bit-bang) I2C driver configuration
116 */
117#define PB_SCL 0x00000020 /* PB 26 */
118#define PB_SDA 0x00000010 /* PB 27 */
119
120#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
121#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
122#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
123#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
124#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
125 else immr->im_cpm.cp_pbdat &= ~PB_SDA
126#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
127 else immr->im_cpm.cp_pbdat &= ~PB_SCL
128#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
129#endif /* CONFIG_SOFT_I2C */
130
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C?? */
132#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
133#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
134#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100135
136# define CONFIG_RTC_DS1337 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137# define CONFIG_SYS_I2C_RTC_ADDR 0x68
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100138
139/*
140 * BOOTP options
141 */
142#define CONFIG_BOOTP_SUBNETMASK
143#define CONFIG_BOOTP_GATEWAY
144#define CONFIG_BOOTP_HOSTNAME
145#define CONFIG_BOOTP_BOOTPATH
146#define CONFIG_BOOTP_BOOTFILESIZE
147
148
149#define CONFIG_MAC_PARTITION
150#define CONFIG_DOS_PARTITION
151
152#undef CONFIG_RTC_MPC8xx /* MPC885 does not support RTC */
153
154#define CONFIG_TIMESTAMP /* but print image timestmps */
155
156
157/*
158 * Command line configuration.
159 */
160#include <config_cmd_default.h>
161
162#define CONFIG_CMD_ASKENV
163#define CONFIG_CMD_DATE
164#define CONFIG_CMD_DHCP
165#define CONFIG_CMD_EEPROM
166#define CONFIG_CMD_I2C
167#define CONFIG_CMD_IDE
168#define CONFIG_CMD_MII
169#define CONFIG_CMD_NFS
170#define CONFIG_CMD_PING
171
172
173/*
174 * Miscellaneous configurable options
175 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_LONGHELP /* undef to save memory */
177#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100178
179#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
181#ifdef CONFIG_SYS_HUSH_PARSER
182#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100183#endif
184
185#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100187#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100189#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
191#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
192#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100193
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
195#define CONFIG_SYS_MEMTEST_END 0x0300000 /* 1 ... 3 MB in DRAM */
196#define CONFIG_SYS_ALT_MEMTEST /* alternate, more extensive
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100197 memory test.*/
198
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100202
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100204
205/*
206 * Enable loopw command.
207 */
208#define CONFIG_LOOPW
209
210/*
211 * Low Level Configuration Settings
212 * (address mappings, register initial values, etc.)
213 * You should know what you are doing if you make changes here.
214 */
215/*-----------------------------------------------------------------------
216 * Internal Memory Mapped Register
217 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CONFIG_SYS_IMMR 0xFFF00000
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100219
220/*-----------------------------------------------------------------------
221 * Definitions for initial stack pointer and data area (in DPRAM)
222 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200224#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200226#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100228
229/*-----------------------------------------------------------------------
230 * Start addresses for the final memory configuration
231 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100233 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_SDRAM_BASE 0x00000000
235#define CONFIG_SYS_FLASH_BASE 0x40000000
236#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
237#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
238#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100239
240/*
241 * For booting Linux, the board info and command line data
242 * have to be in the first 8 MB of memory, since this is
243 * the maximum mapped by the Linux kernel during initialization.
244 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100246
247/*-----------------------------------------------------------------------
248 * FLASH organization
249 */
250
251/* use CFI flash driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200253#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
255#define CONFIG_SYS_FLASH_EMPTY_INFO
256#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
257#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
258#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100259
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200260#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200261#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
262#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */
263#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100264
265/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200266#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
267#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100268
269/*-----------------------------------------------------------------------
270 * Hardware Information Block
271 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
273#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
274#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100275
276/*-----------------------------------------------------------------------
277 * Cache Configuration
278 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100280#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100282#endif
283
284/*-----------------------------------------------------------------------
285 * SYPCR - System Protection Control 11-9
286 * SYPCR can only be written once after reset!
287 *-----------------------------------------------------------------------
288 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
289 */
290#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200291#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100292 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
293#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100295#endif
296
297/*-----------------------------------------------------------------------
298 * SIUMCR - SIU Module Configuration 11-6
299 *-----------------------------------------------------------------------
300 * PCMCIA config., multi-function pin tri-state
301 */
302#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100304#else /* we must activate GPL5 in the SIUMCR for CAN */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100306#endif /* CONFIG_CAN_DRIVER */
307
308/*-----------------------------------------------------------------------
309 * TBSCR - Time Base Status and Control 11-26
310 *-----------------------------------------------------------------------
311 * Clear Reference Interrupt Status, Timebase freezing enabled
312 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100314
315/*-----------------------------------------------------------------------
316 * PISCR - Periodic Interrupt Status and Control 11-31
317 *-----------------------------------------------------------------------
318 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
319 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100321
322/*-----------------------------------------------------------------------
323 * SCCR - System Clock and reset Control Register 15-27
324 *-----------------------------------------------------------------------
325 * Set clock output, timebase and RTC source and divider,
326 * power management and some other internal clocks
327 */
328#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100330 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
331 SCCR_DFALCD00)
332
333/*-----------------------------------------------------------------------
334 * PCMCIA stuff
335 *-----------------------------------------------------------------------
336 *
337 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200338#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
339#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
340#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
341#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
342#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
343#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
344#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
345#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100346
347/*-----------------------------------------------------------------------
348 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
349 *-----------------------------------------------------------------------
350 */
351
352#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
353
354#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
355#undef CONFIG_IDE_LED /* LED for ide not supported */
356#undef CONFIG_IDE_RESET /* reset for ide not supported */
357
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200358#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
359#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100360
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200361#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100362
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200363#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100364
365/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200366#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100367
368/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100370
371/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200372#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100373
374/*-----------------------------------------------------------------------
375 *
376 *-----------------------------------------------------------------------
377 *
378 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200379#define CONFIG_SYS_DER 0
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100380
381/*
382 * Init Memory Controller:
383 *
384 * BR0/1 and OR0/1 (FLASH)
385 */
386
387#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
388#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
389
390/* used to re-map FLASH both when starting from SRAM or FLASH:
391 * restrict access enough to keep SRAM working (if any)
392 * but not too much to meddle with FLASH accesses
393 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200394#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
395#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100396
397/*
398 * FLASH timing: Default value of OR0 after reset
399 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200400#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100401 OR_SCY_6_CLK | OR_TRLX)
402
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200403#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
404#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
405#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100406
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200407#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
408#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
409#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100410
411/*
412 * BR2/3 and OR2/3 (SDRAM)
413 *
414 */
415#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
416#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
417#define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */
418
419/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200420#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100421
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200422#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
423#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100424
425#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200426#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
427#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100428#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200429#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
430#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
431#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
432#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100433 BR_PS_8 | BR_MS_UPMB | BR_V )
434#endif /* CONFIG_CAN_DRIVER */
435
436/*
437 * 4096 Rows from SDRAM example configuration
438 * 1000 factor s -> ms
439 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
440 * 4 Number of refresh cycles per period
441 * 64 Refresh cycle in ms per number of rows
442 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200443#define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100444
445/*
446 * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad)
447 *
448 * CPUclock(MHz) * 31.2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200449 * CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100450 * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16
451 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200452 * CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us
453 * CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us
454 * CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us
455 * CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100456 *
457 * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will
458 * be met also in the default configuration, i.e. if environment variable
459 * 'cpuclk' is not set.
460 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200461#define CONFIG_SYS_MAMR_PTA 128
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100462
463/*
464 * Memory Periodic Timer Prescaler Register (MPTPR) values.
465 */
466/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200467#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100468/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200469#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100470
471/*
472 * MAMR settings for SDRAM
473 */
474
475/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200476#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100477 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
478 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
479/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200480#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100481 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
482 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
483/* 10 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200484#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100485 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \
486 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
487
488/*
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100489 * Network configuration
490 */
491#define CONFIG_FEC_ENET /* enable ethernet on FEC */
492#define CONFIG_ETHER_ON_FEC1 /* ... for FEC1 */
493#define CONFIG_ETHER_ON_FEC2 /* ... for FEC2 */
494
495#define CONFIG_LAST_STAGE_INIT 1 /* Have to configure PHYs for Linux */
496
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200497/* CONFIG_SYS_DISCOVER_PHY only works with FEC if only one interface is enabled */
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100498#if (!defined(CONFIG_ETHER_ON_FEC1) || !defined(CONFIG_ETHER_ON_FEC2))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200499#define CONFIG_SYS_DISCOVER_PHY
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100500#endif
501
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200502#ifndef CONFIG_SYS_DISCOVER_PHY
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100503/* PHY addresses - hard wired in hardware */
504#define CONFIG_FEC1_PHY 1
505#define CONFIG_FEC2_PHY 2
506#endif
507
TsiChung Liew0f3ba7e2008-03-30 01:22:13 -0500508#define CONFIG_MII_INIT 1
509
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100510#define CONFIG_NET_RETRY_COUNT 3
Heiko Schocher48690d82010-07-20 17:45:02 +0200511#define CONFIG_ETHPRIME "FEC"
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100512
Heiko Schocher7026ead2010-02-09 15:50:27 +0100513/* pass open firmware flat tree */
514#define CONFIG_OF_LIBFDT 1
515#define CONFIG_OF_BOARD_SETUP 1
516#define CONFIG_HWCONFIG 1
517
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100518#endif /* __CONFIG_H */