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wdenkc6097192002-11-03 00:24:07 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2001-2005
wdenkc6097192002-11-03 00:24:07 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/* ------------------------------------------------------------------------- */
25
26/*
27 * board/config.h - configuration options, board specific
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
33/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37
38#define CONFIG_MPC824X 1
39#define CONFIG_MPC8245 1
40#define CONFIG_SANDPOINT 1
41
Wolfgang Denk2ae18242010-10-06 09:05:45 +020042#define CONFIG_SYS_TEXT_BASE 0xFFF00000
43
wdenkc6097192002-11-03 00:24:07 +000044#if 0
45#define USE_DINK32 1
46#else
47#undef USE_DINK32
48#endif
49
50#define CONFIG_CONS_INDEX 3 /* set to '3' for on-chip DUART */
51#define CONFIG_BAUDRATE 9600
52#define CONFIG_DRAM_SPEED 100 /* MHz */
53
wdenk414eec32005-04-02 22:37:54 +000054#define CONFIG_TIMESTAMP /* Print image info with timestamp */
55
wdenkc6097192002-11-03 00:24:07 +000056
Jon Loeligerfe7f7822007-07-08 15:02:44 -050057/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -050058 * BOOTP options
59 */
60#define CONFIG_BOOTP_BOOTFILESIZE
61#define CONFIG_BOOTP_BOOTPATH
62#define CONFIG_BOOTP_GATEWAY
63#define CONFIG_BOOTP_HOSTNAME
64
65
66/*
Jon Loeligerfe7f7822007-07-08 15:02:44 -050067 * Command line configuration.
68 */
69#include <config_cmd_default.h>
70
71#define CONFIG_CMD_DHCP
72#define CONFIG_CMD_ELF
73#define CONFIG_CMD_I2C
74#define CONFIG_CMD_EEPROM
75#define CONFIG_CMD_NFS
76#define CONFIG_CMD_PCI
77#define CONFIG_CMD_SNTP
wdenkc6097192002-11-03 00:24:07 +000078
79
80/*
81 * Miscellaneous configurable options
82 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020083#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
84#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
85#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
86#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
87#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
88#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
89#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
90#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkc6097192002-11-03 00:24:07 +000091
92/*-----------------------------------------------------------------------
93 * PCI stuff
94 *-----------------------------------------------------------------------
95 */
96#define CONFIG_PCI /* include pci support */
97#undef CONFIG_PCI_PNP
98
99#define CONFIG_NET_MULTI /* Multi ethernet cards support */
100
101#define CONFIG_EEPRO100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
wdenkc6097192002-11-03 00:24:07 +0000103#define CONFIG_NATSEMI
104#define CONFIG_NS8382X
105
106#define PCI_ENET0_IOADDR 0x80000000
107#define PCI_ENET0_MEMADDR 0x80000000
108#define PCI_ENET1_IOADDR 0x81000000
109#define PCI_ENET1_MEMADDR 0x81000000
110
111
112/*-----------------------------------------------------------------------
113 * Start addresses for the final memory configuration
114 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkc6097192002-11-03 00:24:07 +0000116 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_SDRAM_BASE 0x00000000
118#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000
wdenkc6097192002-11-03 00:24:07 +0000119
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
wdenkc6097192002-11-03 00:24:07 +0000121
122#if defined (USE_DINK32)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_MONITOR_LEN 0x00030000
124#define CONFIG_SYS_MONITOR_BASE 0x00090000
125#define CONFIG_SYS_RAMBOOT 1
126#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Wolfgang Denk553f0982010-10-26 13:32:32 +0200127#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200129#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkc6097192002-11-03 00:24:07 +0000131#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#undef CONFIG_SYS_RAMBOOT
133#define CONFIG_SYS_MONITOR_LEN 0x00030000
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200134#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
wdenkc6097192002-11-03 00:24:07 +0000135
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136/*#define CONFIG_SYS_GBL_DATA_SIZE 256*/
137#define CONFIG_SYS_GBL_DATA_SIZE 128
wdenkc6097192002-11-03 00:24:07 +0000138
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200140#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
141#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
wdenkc6097192002-11-03 00:24:07 +0000142
143#endif
144
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#define CONFIG_SYS_FLASH_BASE 0xFFF00000
wdenkc6097192002-11-03 00:24:07 +0000146#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_FLASH_SIZE (512 * 1024) /* sandpoint has tiny eeprom */
wdenkc6097192002-11-03 00:24:07 +0000148#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_FLASH_SIZE (1024 * 1024) /* Unity has onboard 1MByte flash */
wdenkc6097192002-11-03 00:24:07 +0000150#endif
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200151#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200152#define CONFIG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */
153#define CONFIG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */
wdenkc6097192002-11-03 00:24:07 +0000154
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
wdenkc6097192002-11-03 00:24:07 +0000156
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
158#define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */
wdenkc6097192002-11-03 00:24:07 +0000159
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_EUMB_ADDR 0xFC000000
wdenkc6097192002-11-03 00:24:07 +0000161
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_ISA_MEM 0xFD000000
163#define CONFIG_SYS_ISA_IO 0xFE000000
wdenkc6097192002-11-03 00:24:07 +0000164
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */
166#define CONFIG_SYS_FLASH_RANGE_SIZE 0x01000000
wdenkc6097192002-11-03 00:24:07 +0000167#define FLASH_BASE0_PRELIM 0xFFF00000 /* sandpoint flash */
168#define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash */
169
170/*
171 * select i2c support configuration
172 *
173 * Supported configurations are {none, software, hardware} drivers.
174 * If the software driver is chosen, there are some additional
175 * configuration items that the driver uses to drive the port pins.
176 */
177#define CONFIG_HARD_I2C 1 /* To enable I2C support */
178#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
180#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenkc6097192002-11-03 00:24:07 +0000181
182#ifdef CONFIG_SOFT_I2C
183#error "Soft I2C is not configured properly. Please review!"
184#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
185#define I2C_ACTIVE (iop->pdir |= 0x00010000)
186#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
187#define I2C_READ ((iop->pdat & 0x00010000) != 0)
188#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
189 else iop->pdat &= ~0x00010000
190#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
191 else iop->pdat &= ~0x00020000
192#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
193#endif /* CONFIG_SOFT_I2C */
194
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */
196#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
197#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
198#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
wdenkc6097192002-11-03 00:24:07 +0000199
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
201#define CONFIG_SYS_FLASH_BANKS { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }
wdenkc6097192002-11-03 00:24:07 +0000202
203/*-----------------------------------------------------------------------
204 * Definitions for initial stack pointer and data area (in DPRAM)
205 */
206
207
Jean-Christophe PLAGNIOL-VILLARDab6878c2008-08-13 01:40:40 +0200208#define CONFIG_WINBOND_83C553 1 /*has a winbond bridge */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */
210#define CONFIG_SYS_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */
211#define CONFIG_SYS_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */
wdenkc6097192002-11-03 00:24:07 +0000212
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
214#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
wdenkc6097192002-11-03 00:24:07 +0000215
216/*
217 * NS87308 Configuration
218 */
Jean-Christophe PLAGNIOL-VILLARD55d6d2d2008-08-13 01:40:40 +0200219#define CONFIG_NS87308 /* Nat Semi super-io controller on ISA bus */
wdenkc6097192002-11-03 00:24:07 +0000220
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_NS87308_BADDR_10 1
wdenkc6097192002-11-03 00:24:07 +0000222
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_NS87308_DEVS ( CONFIG_SYS_NS87308_UART1 | \
224 CONFIG_SYS_NS87308_UART2 | \
225 CONFIG_SYS_NS87308_POWRMAN | \
226 CONFIG_SYS_NS87308_RTC_APC )
wdenkc6097192002-11-03 00:24:07 +0000227
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#undef CONFIG_SYS_NS87308_PS2MOD
wdenkc6097192002-11-03 00:24:07 +0000229
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_NS87308_CS0_BASE 0x0076
231#define CONFIG_SYS_NS87308_CS0_CONF 0x30
232#define CONFIG_SYS_NS87308_CS1_BASE 0x0075
233#define CONFIG_SYS_NS87308_CS1_CONF 0x30
234#define CONFIG_SYS_NS87308_CS2_BASE 0x0074
235#define CONFIG_SYS_NS87308_CS2_CONF 0x30
wdenkc6097192002-11-03 00:24:07 +0000236
237/*
238 * NS16550 Configuration
239 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_NS16550
241#define CONFIG_SYS_NS16550_SERIAL
wdenkc6097192002-11-03 00:24:07 +0000242
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_NS16550_REG_SIZE 1
wdenkc6097192002-11-03 00:24:07 +0000244
wdenkf832d8a2004-06-10 21:55:33 +0000245#if (CONFIG_CONS_INDEX > 2)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_NS16550_CLK CONFIG_DRAM_SPEED*1000000
wdenkf832d8a2004-06-10 21:55:33 +0000247#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_NS16550_CLK 1843200
wdenkf832d8a2004-06-10 21:55:33 +0000249#endif
wdenk49822e22004-06-19 21:19:10 +0000250
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE)
252#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE)
253#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_EUMB_ADDR + 0x4500)
254#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_EUMB_ADDR + 0x4600)
wdenkc6097192002-11-03 00:24:07 +0000255
256/*
257 * Low Level Configuration Settings
258 * (address mappings, register initial values, etc.)
259 * You should know what you are doing if you make changes here.
260 */
261
262#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
263
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_ROMNAL 7 /*rom/flash next access time */
265#define CONFIG_SYS_ROMFAL 11 /*rom/flash access time */
wdenkc6097192002-11-03 00:24:07 +0000266
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_REFINT 430 /* no of clock cycles between CBR refresh cycles */
wdenkc6097192002-11-03 00:24:07 +0000268
269/* the following are for SDRAM only*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define CONFIG_SYS_BSTOPRE 121 /* Burst To Precharge, sets open page interval */
271#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */
272#define CONFIG_SYS_RDLAT 4 /* data latency from read command */
273#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */
274#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
275#define CONFIG_SYS_ACTORW 3 /* Activate to R/W */
276#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
277#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
wdenkc6097192002-11-03 00:24:07 +0000278#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* OBSOLETE! SDMODE Burst length 2=4, 3=8 */
wdenkc6097192002-11-03 00:24:07 +0000280#endif
281
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
283#define CONFIG_SYS_EXTROM 1
284#define CONFIG_SYS_REGDIMM 0
wdenkc6097192002-11-03 00:24:07 +0000285
286
287/* memory bank settings*/
288/*
289 * only bits 20-29 are actually used from these vales to set the
290 * start/end address the upper two bits will be 0, and the lower 20
291 * bits will be set to 0x00000 for a start address, or 0xfffff for an
292 * end address
293 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_BANK0_START 0x00000000
295#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
296#define CONFIG_SYS_BANK0_ENABLE 1
297#define CONFIG_SYS_BANK1_START 0x3ff00000
298#define CONFIG_SYS_BANK1_END 0x3fffffff
299#define CONFIG_SYS_BANK1_ENABLE 0
300#define CONFIG_SYS_BANK2_START 0x3ff00000
301#define CONFIG_SYS_BANK2_END 0x3fffffff
302#define CONFIG_SYS_BANK2_ENABLE 0
303#define CONFIG_SYS_BANK3_START 0x3ff00000
304#define CONFIG_SYS_BANK3_END 0x3fffffff
305#define CONFIG_SYS_BANK3_ENABLE 0
306#define CONFIG_SYS_BANK4_START 0x00000000
307#define CONFIG_SYS_BANK4_END 0x00000000
308#define CONFIG_SYS_BANK4_ENABLE 0
309#define CONFIG_SYS_BANK5_START 0x00000000
310#define CONFIG_SYS_BANK5_END 0x00000000
311#define CONFIG_SYS_BANK5_ENABLE 0
312#define CONFIG_SYS_BANK6_START 0x00000000
313#define CONFIG_SYS_BANK6_END 0x00000000
314#define CONFIG_SYS_BANK6_ENABLE 0
315#define CONFIG_SYS_BANK7_START 0x00000000
316#define CONFIG_SYS_BANK7_END 0x00000000
317#define CONFIG_SYS_BANK7_ENABLE 0
wdenkc6097192002-11-03 00:24:07 +0000318/*
319 * Memory bank enable bitmask, specifying which of the banks defined above
320 are actually present. MSB is for bank #7, LSB is for bank #0.
321 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200322#define CONFIG_SYS_BANK_ENABLE 0x01
wdenkc6097192002-11-03 00:24:07 +0000323
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_ODCR 0xff /* configures line driver impedances, */
wdenkc6097192002-11-03 00:24:07 +0000325 /* see 8240 book for bit definitions */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */
wdenkc6097192002-11-03 00:24:07 +0000327 /* currently accessed page in memory */
328 /* see 8240 book for details */
329
330/* SDRAM 0 - 256MB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
332#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
wdenkc6097192002-11-03 00:24:07 +0000333
334/* stack in DCACHE @ 1GB (no backing mem) */
335#if defined(USE_DINK32)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#define CONFIG_SYS_IBAT1L (0x40000000 | BATL_PP_00 )
337#define CONFIG_SYS_IBAT1U (0x40000000 | BATU_BL_128K )
wdenkc6097192002-11-03 00:24:07 +0000338#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
340#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
wdenkc6097192002-11-03 00:24:07 +0000341#endif
342
343/* PCI memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
345#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
wdenkc6097192002-11-03 00:24:07 +0000346
347/* Flash, config addrs, etc */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200348#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
349#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
wdenkc6097192002-11-03 00:24:07 +0000350
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200351#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
352#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
353#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
354#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
355#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
356#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
357#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
358#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
wdenkc6097192002-11-03 00:24:07 +0000359
360/*
361 * For booting Linux, the board info and command line data
362 * have to be in the first 8 MB of memory, since this is
363 * the maximum mapped by the Linux kernel during initialization.
364 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200365#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkc6097192002-11-03 00:24:07 +0000366/*-----------------------------------------------------------------------
367 * FLASH organization
368 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
370#define CONFIG_SYS_MAX_FLASH_SECT 20 /* max number of sectors on one chip */
wdenkc6097192002-11-03 00:24:07 +0000371
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200372#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
373#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenkc6097192002-11-03 00:24:07 +0000374
375/*-----------------------------------------------------------------------
376 * Cache Configuration
377 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200378#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */
Jon Loeligerfe7f7822007-07-08 15:02:44 -0500379#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200380# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenkc6097192002-11-03 00:24:07 +0000381#endif
382
wdenkc6097192002-11-03 00:24:07 +0000383/* values according to the manual */
384
385#define CONFIG_DRAM_50MHZ 1
386#define CONFIG_SDRAM_50MHZ
387
388#undef NR_8259_INTS
389#define NR_8259_INTS 1
390
391
392#define CONFIG_DISK_SPINUP_TIME 1000000
393
394
395#endif /* __CONFIG_H */