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John Otkend4024bb2007-07-26 17:49:11 +02001/*
2 * (C) Copyright 2000-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2005-2007
6 * Beijing UD Technology Co., Ltd., taihusupport@amcc.com
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30
31#define CONFIG_405EP 1 /* this is a PPC405 CPU */
32#define CONFIG_4xx 1 /* member of PPC4xx family */
33#define CONFIG_TAIHU 1 /* on a taihu board */
34
Stefan Roese72675dc2008-06-06 15:55:21 +020035/*
36 * Include common defines/options for all AMCC eval boards
37 */
38#define CONFIG_HOSTNAME taihu
39#include "amcc-common.h"
40
John Otkend4024bb2007-07-26 17:49:11 +020041#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f */
42
43#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
44
45#define CONFIG_NO_SERIAL_EEPROM
46
47/*----------------------------------------------------------------------------*/
48#ifdef CONFIG_NO_SERIAL_EEPROM
49
50/*
51!-------------------------------------------------------------------------------
52! PLL settings for 333MHz CPU, 111MHz PLB/SDRAM, 55MHz EBC, 33MHz PCI,
53! assuming a 33MHz input clock to the 405EP from the C9531.
54!-------------------------------------------------------------------------------
55*/
56#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
57 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
58 PLL_MALDIV_1 | PLL_PCIDIV_3)
59#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \
60 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
61 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
62#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
63 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
64 PLL_MALDIV_1 | PLL_PCIDIV_1)
65#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \
66 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
67 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
68
69#define PLLMR0_DEFAULT PLLMR0_333_111_55_37
70#define PLLMR1_DEFAULT PLLMR1_333_111_55_37
71#define PLLMR0_DEFAULT_PCI66 PLLMR0_333_111_55_111
72#define PLLMR1_DEFAULT_PCI66 PLLMR1_333_111_55_111
73
74#endif
75/*----------------------------------------------------------------------------*/
76
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020077#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
John Otkend4024bb2007-07-26 17:49:11 +020078
Stefan Roese72675dc2008-06-06 15:55:21 +020079/*
80 * Default environment variables
81 */
82#define CONFIG_EXTRA_ENV_SETTINGS \
83 CONFIG_AMCC_DEF_ENV \
84 CONFIG_AMCC_DEF_ENV_PPC \
85 CONFIG_AMCC_DEF_ENV_NOR_UPD \
John Otkend4024bb2007-07-26 17:49:11 +020086 "kernel_addr=FC000000\0" \
87 "ramdisk_addr=FC180000\0" \
John Otkend4024bb2007-07-26 17:49:11 +020088 ""
John Otkend4024bb2007-07-26 17:49:11 +020089
John Otkend4024bb2007-07-26 17:49:11 +020090#define CONFIG_PHY_ADDR 0x14 /* PHY address */
Stefan Roesea00eccf2008-05-08 11:05:15 +020091#define CONFIG_HAS_ETH0
John Otkend4024bb2007-07-26 17:49:11 +020092#define CONFIG_HAS_ETH1
93#define CONFIG_PHY1_ADDR 0x10 /* EMAC1 PHY address */
John Otkend4024bb2007-07-26 17:49:11 +020094#define CONFIG_PHY_RESET 1
95
Stefan Roese3b3bff42007-08-14 16:36:29 +020096/*
Stefan Roese72675dc2008-06-06 15:55:21 +020097 * Commands additional to the ones defined in amcc-common.h
Stefan Roese3b3bff42007-08-14 16:36:29 +020098 */
Stefan Roese3b3bff42007-08-14 16:36:29 +020099#define CONFIG_CMD_CACHE
Stefan Roese3b3bff42007-08-14 16:36:29 +0200100#define CONFIG_CMD_PCI
Stefan Roese3b3bff42007-08-14 16:36:29 +0200101#define CONFIG_CMD_SDRAM
102#define CONFIG_CMD_SPI
John Otkend4024bb2007-07-26 17:49:11 +0200103
John Otkend4024bb2007-07-26 17:49:11 +0200104#undef CONFIG_SPD_EEPROM /* use SPD EEPROM for setup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105#define CONFIG_SYS_SDRAM_SIZE_PER_BANK 0x04000000 /* 64MB */
106#define CONFIG_SYS_SDRAM_BANKS 2
John Otkend4024bb2007-07-26 17:49:11 +0200107
108/*
109 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
110 */
111#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
112#define CONFIG_SDRAM_BANK1 1 /* init onboard SDRAM bank 1 */
113
114/* SDRAM timings used in datasheet */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
116#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
117#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */
118#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
119#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
John Otkend4024bb2007-07-26 17:49:11 +0200120
121/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
123 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
124 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
John Otkend4024bb2007-07-26 17:49:11 +0200125 * The Linux BASE_BAUD define should match this configuration.
126 * baseBaud = cpuClock/(uartDivisor*16)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
John Otkend4024bb2007-07-26 17:49:11 +0200128 * set Linux BASE_BAUD to 403200.
129 */
Stefan Roese550650d2010-09-20 16:05:31 +0200130#define CONFIG_CONS_INDEX 2 /* Use UART1 */
John Otkend4024bb2007-07-26 17:49:11 +0200131#undef CONFIG_SERIAL_SOFTWARE_FIFO
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
133#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
134#define CONFIG_SYS_BASE_BAUD 691200
John Otkend4024bb2007-07-26 17:49:11 +0200135
John Otkend4024bb2007-07-26 17:49:11 +0200136/*-----------------------------------------------------------------------
137 * I2C stuff
138 *-----------------------------------------------------------------------
139 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
John Otkend4024bb2007-07-26 17:49:11 +0200141
Peter Tyser0f89c542009-04-18 22:34:03 -0500142#define CONFIG_SYS_I2C_NOPROBES { 0x69 } /* avoid i2c probe hangup (why?) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
John Otkend4024bb2007-07-26 17:49:11 +0200144
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C boot EEPROM (24C02W) */
146#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
John Otkend4024bb2007-07-26 17:49:11 +0200147
148#define CONFIG_SOFT_SPI
149#define SPI_SCL spi_scl
150#define SPI_SDA spi_sda
151#define SPI_READ spi_read()
152#define SPI_DELAY udelay(2)
153#ifndef __ASSEMBLY__
154void spi_scl(int);
155void spi_sda(int);
156unsigned char spi_read(void);
157#endif
158
159/* standard dtt sensor configuration */
160#define CONFIG_DTT_DS1775 1
161#define CONFIG_DTT_SENSORS { 0 }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_I2C_DTT_ADDR 0x49
John Otkend4024bb2007-07-26 17:49:11 +0200163
164/*-----------------------------------------------------------------------
165 * PCI stuff
166 *-----------------------------------------------------------------------
167 */
168#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
169#define PCI_HOST_FORCE 1 /* configure as pci host */
170#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
171
172#define CONFIG_PCI /* include pci support */
173#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
174#define CONFIG_PCI_PNP /* do pci plug-and-play */
175 /* resource configuration */
176#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
177
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
179#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
180#define CONFIG_SYS_PCI_CLASSCODE 0x0600 /* PCI Class Code: bridge/host */
181#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
182#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
183#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
184#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
185#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
186#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
John Otkend4024bb2007-07-26 17:49:11 +0200187#define CONFIG_EEPRO100 1
188
189/*-----------------------------------------------------------------------
190 * Start addresses for the final memory configuration
191 * (Set up by the startup code)
John Otkend4024bb2007-07-26 17:49:11 +0200192 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_SYS_FLASH_BASE 0xFFE00000
John Otkend4024bb2007-07-26 17:49:11 +0200194
195/*-----------------------------------------------------------------------
196 * FLASH organization
197 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
199#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
John Otkend4024bb2007-07-26 17:49:11 +0200200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
202#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
John Otkend4024bb2007-07-26 17:49:11 +0200203
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_FLASH_ADDR0 0x555
205#define CONFIG_SYS_FLASH_ADDR1 0x2aa
206#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
John Otkend4024bb2007-07-26 17:49:11 +0200207
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200208#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200209#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200211#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
John Otkend4024bb2007-07-26 17:49:11 +0200212
213/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200214#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
215#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200216#endif /* CONFIG_ENV_IS_IN_FLASH */
John Otkend4024bb2007-07-26 17:49:11 +0200217
218/*-----------------------------------------------------------------------
219 * NVRAM organization
220 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
222#define CONFIG_SYS_NVRAM_SIZE 0x1ff8 /* NVRAM size */
John Otkend4024bb2007-07-26 17:49:11 +0200223
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200224#ifdef CONFIG_ENV_IS_IN_NVRAM
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200225#define CONFIG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
226#define CONFIG_ENV_ADDR \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227 (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env*/
John Otkend4024bb2007-07-26 17:49:11 +0200228#endif
229
230/*-----------------------------------------------------------------------
231 * PPC405 GPIO Configuration
232 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
John Otkend4024bb2007-07-26 17:49:11 +0200234{ \
235/* GPIO Core 0 */ \
236{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast SPI CS */ \
237{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
238{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
239{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
240{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
241{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO5 TS3 */ \
242{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
243{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
244{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
245{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
246{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
247{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
248{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
249{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
250{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 SPI SCLK */ \
251{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 SPI DI */ \
252{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 SPI DO */ \
253{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 PCI INTA */ \
254{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 PCI INTB */ \
255{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 PCI INTC */ \
256{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 PCI INTD */ \
257{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 USB */ \
258{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 EBC */ \
259{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 unused */ \
260{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD UART1 */ \
261{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
262{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
263{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200264{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx UART0 */ \
John Otkend4024bb2007-07-26 17:49:11 +0200265{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
266{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 User LED1 */ \
267{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 User LED2 */ \
268} \
269}
270
John Otkend4024bb2007-07-26 17:49:11 +0200271/*
272 * Init Memory Controller:
273 *
274 * BR0/1 and OR0/1 (FLASH)
275 */
276
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
John Otkend4024bb2007-07-26 17:49:11 +0200278#define FLASH_BASE1_PRELIM 0xFC000000 /* FLASH bank #1 */
279
280/*-----------------------------------------------------------------------
281 * Definitions for initial stack pointer and data area (in data cache)
282 */
283/* use on chip memory (OCM) for temperary stack until sdram is tested */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200284#define CONFIG_SYS_TEMP_STACK_OCM 1
John Otkend4024bb2007-07-26 17:49:11 +0200285
286/* On Chip Memory location */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
288#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
289#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
290#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
John Otkend4024bb2007-07-26 17:49:11 +0200291
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
293#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
294#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
John Otkend4024bb2007-07-26 17:49:11 +0200295
296/*-----------------------------------------------------------------------
297 * External Bus Controller (EBC) Setup
298 */
299
300/* Memory Bank 0 (Flash/SRAM) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_EBC_PB0AP 0x03815600
302#define CONFIG_SYS_EBC_PB0CR 0xFFE3A000 /* BAS=0xFFE,BS=2MB,BU=R/W,BW=16bit */
John Otkend4024bb2007-07-26 17:49:11 +0200303
304/* Memory Bank 1 (NVRAM/RTC) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_EBC_PB1AP 0x05815600
306#define CONFIG_SYS_EBC_PB1CR 0xFC0BA000 /* BAS=0xFc0,BS=32MB,BU=R/W,BW=16bit */
John Otkend4024bb2007-07-26 17:49:11 +0200307
308/* Memory Bank 2 (USB device) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200309#define CONFIG_SYS_EBC_PB2AP 0x03016600
310#define CONFIG_SYS_EBC_PB2CR 0x50018000 /* BAS=0x500,BS=1MB,BU=R/W,BW=8bit */
John Otkend4024bb2007-07-26 17:49:11 +0200311
312/* Memory Bank 3 (LCM and D-flip-flop) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_EBC_PB3AP 0x158FF600
314#define CONFIG_SYS_EBC_PB3CR 0x50118000 /* BAS=0x501,BS=1MB,BU=R/W,BW=8bit */
John Otkend4024bb2007-07-26 17:49:11 +0200315
316/* Memory Bank 4 (not install) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_EBC_PB4AP 0x158FF600
318#define CONFIG_SYS_EBC_PB4CR 0x5021A000
John Otkend4024bb2007-07-26 17:49:11 +0200319
John Otkend4024bb2007-07-26 17:49:11 +0200320#define CPLD_REG0_ADDR 0x50100000
321#define CPLD_REG1_ADDR 0x50100001
Stefan Roesea00eccf2008-05-08 11:05:15 +0200322
John Otkend4024bb2007-07-26 17:49:11 +0200323#endif /* __CONFIG_H */