wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2002 |
| 3 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
| 4 | * Marius Groeger <mgroeger@sysgo.de> |
| 5 | * |
| 6 | * (C) Copyright 2002 |
| 7 | * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> |
| 8 | * |
| 9 | * (C) Copyright 2003 |
| 10 | * Texas Instruments, <www.ti.com> |
| 11 | * Kshitij Gupta <Kshitij@ti.com> |
| 12 | * |
| 13 | * (C) Copyright 2004 |
| 14 | * ARM Ltd. |
| 15 | * Philippe Robin, <philippe.robin@arm.com> |
| 16 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 17 | * SPDX-License-Identifier: GPL-2.0+ |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 18 | */ |
| 19 | |
| 20 | #include <common.h> |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 21 | #include <netdev.h> |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 22 | |
Wolfgang Denk | d87080b | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 23 | DECLARE_GLOBAL_DATA_PTR; |
| 24 | |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 25 | #if defined(CONFIG_SHOW_BOOT_PROGRESS) |
| 26 | void show_boot_progress(int progress) |
| 27 | { |
| 28 | printf("Boot reached stage %d\n", progress); |
| 29 | } |
| 30 | #endif |
| 31 | |
| 32 | #define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF) |
| 33 | |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 34 | /* |
| 35 | * Miscellaneous platform dependent initialisations |
| 36 | */ |
| 37 | |
Stefano Babic | d388298 | 2011-06-24 03:04:38 +0000 | [diff] [blame] | 38 | int board_early_init_f (void) |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 39 | { |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 40 | /* |
| 41 | * set clock frequency: |
| 42 | * VERSATILE_REFCLK is 32KHz |
| 43 | * VERSATILE_TIMCLK is 1MHz |
| 44 | */ |
| 45 | *(volatile unsigned int *)(VERSATILE_SCTL_BASE) |= |
| 46 | ((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) | |
| 47 | (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel)); |
| 48 | |
Stefano Babic | d388298 | 2011-06-24 03:04:38 +0000 | [diff] [blame] | 49 | return 0; |
| 50 | } |
| 51 | |
| 52 | int board_init (void) |
| 53 | { |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 54 | /* arch number of Versatile Board */ |
wdenk | 731215e | 2004-10-10 18:41:04 +0000 | [diff] [blame] | 55 | gd->bd->bi_arch_number = MACH_TYPE_VERSATILE_PB; |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 56 | |
| 57 | /* adress of boot parameters */ |
| 58 | gd->bd->bi_boot_params = 0x00000100; |
| 59 | |
wdenk | bc54f30 | 2004-07-11 18:10:30 +0000 | [diff] [blame] | 60 | gd->flags = 0; |
| 61 | |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 62 | icache_enable (); |
| 63 | |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 64 | return 0; |
| 65 | } |
| 66 | |
| 67 | |
| 68 | int misc_init_r (void) |
| 69 | { |
| 70 | setenv("verify", "n"); |
| 71 | return (0); |
| 72 | } |
| 73 | |
| 74 | /****************************** |
| 75 | Routine: |
| 76 | Description: |
| 77 | ******************************/ |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 78 | int dram_init (void) |
| 79 | { |
Stefano Babic | d388298 | 2011-06-24 03:04:38 +0000 | [diff] [blame] | 80 | /* dram_init must store complete ramsize in gd->ram_size */ |
Stefano Babic | 689d0fa | 2011-08-29 22:49:54 +0000 | [diff] [blame] | 81 | gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, |
Stefano Babic | d388298 | 2011-06-24 03:04:38 +0000 | [diff] [blame] | 82 | PHYS_SDRAM_1_SIZE); |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 83 | return 0; |
| 84 | } |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 85 | |
| 86 | #ifdef CONFIG_CMD_NET |
| 87 | int board_eth_init(bd_t *bis) |
| 88 | { |
| 89 | int rc = 0; |
| 90 | #ifdef CONFIG_SMC91111 |
| 91 | rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); |
| 92 | #endif |
| 93 | return rc; |
| 94 | } |
| 95 | #endif |