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wdenk3d3befa2004-03-14 15:06:13 +00001/*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
6 * (C) Copyright 2002
7 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
8 *
9 * (C) Copyright 2003
10 * Texas Instruments, <www.ti.com>
11 * Kshitij Gupta <Kshitij@ti.com>
12 *
13 * (C) Copyright 2004
14 * ARM Ltd.
15 * Philippe Robin, <philippe.robin@arm.com>
16 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020017 * SPDX-License-Identifier: GPL-2.0+
wdenk3d3befa2004-03-14 15:06:13 +000018 */
19
20#include <common.h>
Ben Warren7194ab82009-10-04 22:37:03 -070021#include <netdev.h>
wdenk3d3befa2004-03-14 15:06:13 +000022
Wolfgang Denkd87080b2006-03-31 18:32:53 +020023DECLARE_GLOBAL_DATA_PTR;
24
wdenk3d3befa2004-03-14 15:06:13 +000025#if defined(CONFIG_SHOW_BOOT_PROGRESS)
26void show_boot_progress(int progress)
27{
28 printf("Boot reached stage %d\n", progress);
29}
30#endif
31
32#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
33
wdenk3d3befa2004-03-14 15:06:13 +000034/*
35 * Miscellaneous platform dependent initialisations
36 */
37
Stefano Babicd3882982011-06-24 03:04:38 +000038int board_early_init_f (void)
wdenk3d3befa2004-03-14 15:06:13 +000039{
wdenk3d3befa2004-03-14 15:06:13 +000040 /*
41 * set clock frequency:
42 * VERSATILE_REFCLK is 32KHz
43 * VERSATILE_TIMCLK is 1MHz
44 */
45 *(volatile unsigned int *)(VERSATILE_SCTL_BASE) |=
46 ((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
47 (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel));
48
Stefano Babicd3882982011-06-24 03:04:38 +000049 return 0;
50}
51
52int board_init (void)
53{
wdenk3d3befa2004-03-14 15:06:13 +000054 /* arch number of Versatile Board */
wdenk731215e2004-10-10 18:41:04 +000055 gd->bd->bi_arch_number = MACH_TYPE_VERSATILE_PB;
wdenk3d3befa2004-03-14 15:06:13 +000056
57 /* adress of boot parameters */
58 gd->bd->bi_boot_params = 0x00000100;
59
wdenkbc54f302004-07-11 18:10:30 +000060 gd->flags = 0;
61
wdenk3d3befa2004-03-14 15:06:13 +000062 icache_enable ();
63
wdenk3d3befa2004-03-14 15:06:13 +000064 return 0;
65}
66
67
68int misc_init_r (void)
69{
70 setenv("verify", "n");
71 return (0);
72}
73
74/******************************
75 Routine:
76 Description:
77******************************/
wdenk3d3befa2004-03-14 15:06:13 +000078int dram_init (void)
79{
Stefano Babicd3882982011-06-24 03:04:38 +000080 /* dram_init must store complete ramsize in gd->ram_size */
Stefano Babic689d0fa2011-08-29 22:49:54 +000081 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
Stefano Babicd3882982011-06-24 03:04:38 +000082 PHYS_SDRAM_1_SIZE);
wdenk3d3befa2004-03-14 15:06:13 +000083 return 0;
84}
Ben Warren7194ab82009-10-04 22:37:03 -070085
86#ifdef CONFIG_CMD_NET
87int board_eth_init(bd_t *bis)
88{
89 int rc = 0;
90#ifdef CONFIG_SMC91111
91 rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
92#endif
93 return rc;
94}
95#endif