Ilya Ledvich | 54e7445 | 2013-11-07 07:57:33 +0200 | [diff] [blame^] | 1 | /* |
| 2 | * SPL specific code for Compulab CM-T335 board |
| 3 | * |
| 4 | * Board functions for Compulab CM-T335 board |
| 5 | * |
| 6 | * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/ |
| 7 | * |
| 8 | * Author: Ilya Ledvich <ilya@compulab.co.il> |
| 9 | * |
| 10 | * SPDX-License-Identifier: GPL-2.0+ |
| 11 | */ |
| 12 | |
| 13 | #include <common.h> |
| 14 | #include <errno.h> |
| 15 | |
| 16 | #include <asm/arch/ddr_defs.h> |
| 17 | #include <asm/arch/clock.h> |
| 18 | #include <asm/arch/clocks_am33xx.h> |
| 19 | #include <asm/arch/sys_proto.h> |
| 20 | #include <asm/arch/hardware_am33xx.h> |
| 21 | #include <asm/sizes.h> |
| 22 | |
| 23 | static const struct ddr_data ddr3_data = { |
| 24 | .datardsratio0 = MT41J128MJT125_RD_DQS, |
| 25 | .datawdsratio0 = MT41J128MJT125_WR_DQS, |
| 26 | .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE, |
| 27 | .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA, |
| 28 | .datadldiff0 = PHY_DLL_LOCK_DIFF, |
| 29 | }; |
| 30 | |
| 31 | static const struct cmd_control ddr3_cmd_ctrl_data = { |
| 32 | .cmd0csratio = MT41J128MJT125_RATIO, |
| 33 | .cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF, |
| 34 | .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT, |
| 35 | |
| 36 | .cmd1csratio = MT41J128MJT125_RATIO, |
| 37 | .cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF, |
| 38 | .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT, |
| 39 | |
| 40 | .cmd2csratio = MT41J128MJT125_RATIO, |
| 41 | .cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF, |
| 42 | .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT, |
| 43 | }; |
| 44 | |
| 45 | static struct emif_regs ddr3_emif_reg_data = { |
| 46 | .sdram_config = MT41J128MJT125_EMIF_SDCFG, |
| 47 | .ref_ctrl = MT41J128MJT125_EMIF_SDREF, |
| 48 | .sdram_tim1 = MT41J128MJT125_EMIF_TIM1, |
| 49 | .sdram_tim2 = MT41J128MJT125_EMIF_TIM2, |
| 50 | .sdram_tim3 = MT41J128MJT125_EMIF_TIM3, |
| 51 | .zq_config = MT41J128MJT125_ZQ_CFG, |
| 52 | .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY | |
| 53 | PHY_EN_DYN_PWRDN, |
| 54 | }; |
| 55 | |
| 56 | const struct dpll_params dpll_ddr = { |
| 57 | /* M N M2 M3 M4 M5 M6 */ |
| 58 | 303, (V_OSCK/1000000) - 1, 1, -1, -1, -1, -1}; |
| 59 | |
| 60 | void am33xx_spl_board_init(void) |
| 61 | { |
| 62 | struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; |
| 63 | |
| 64 | /* Get the frequency */ |
| 65 | dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); |
| 66 | |
| 67 | /* Set CORE Frequencies to OPP100 */ |
| 68 | do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); |
| 69 | |
| 70 | /* Set MPU Frequency to what we detected now that voltages are set */ |
| 71 | do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); |
| 72 | } |
| 73 | |
| 74 | const struct dpll_params *get_dpll_ddr_params(void) |
| 75 | { |
| 76 | return &dpll_ddr; |
| 77 | } |
| 78 | |
| 79 | static void probe_sdram_size(long size) |
| 80 | { |
| 81 | switch (size) { |
| 82 | case SZ_512M: |
| 83 | ddr3_emif_reg_data.sdram_config = MT41J256MJT125_EMIF_SDCFG; |
| 84 | break; |
| 85 | case SZ_256M: |
| 86 | ddr3_emif_reg_data.sdram_config = MT41J128MJT125_EMIF_SDCFG; |
| 87 | break; |
| 88 | case SZ_128M: |
| 89 | ddr3_emif_reg_data.sdram_config = MT41J64MJT125_EMIF_SDCFG; |
| 90 | break; |
| 91 | default: |
| 92 | puts("Failed configuring DRAM, resetting...\n\n"); |
| 93 | reset_cpu(0); |
| 94 | } |
| 95 | debug("%s: setting DRAM size to %ldM\n", __func__, size >> 20); |
| 96 | config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data, |
| 97 | &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); |
| 98 | } |
| 99 | |
| 100 | void sdram_init(void) |
| 101 | { |
| 102 | long size = SZ_1G; |
| 103 | |
| 104 | do { |
| 105 | size = size / 2; |
| 106 | probe_sdram_size(size); |
| 107 | } while (get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, size) < size); |
| 108 | |
| 109 | return; |
| 110 | } |