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TsiChungLiewaa5f1f92008-01-14 17:23:08 -06001/*
2 * Configuation settings for the Freescale MCF5373 FireEngine board.
3 *
Alison Wang2ee03c62012-03-25 19:18:14 +00004 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
TsiChungLiewaa5f1f92008-01-14 17:23:08 -06005 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02007 * SPDX-License-Identifier: GPL-2.0+
TsiChungLiewaa5f1f92008-01-14 17:23:08 -06008 */
9
10/*
11 * board/config.h - configuration options, board specific
12 */
13
14#ifndef _M5373EVB_H
15#define _M5373EVB_H
16
17/*
18 * High Level Configuration Options
19 * (easy to change)
20 */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060021
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060022#define CONFIG_MCFUART
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020023#define CONFIG_SYS_UART_PORT (0)
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060024
25#undef CONFIG_WATCHDOG
26#define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */
27
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020028#define CONFIG_SYS_UNIFY_CACHE
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060029
30#define CONFIG_MCFFEC
31#ifdef CONFIG_MCFFEC
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060032# define CONFIG_MII 1
TsiChung Liew0f3ba7e2008-03-30 01:22:13 -050033# define CONFIG_MII_INIT 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020034# define CONFIG_SYS_DISCOVER_PHY
35# define CONFIG_SYS_RX_ETH_BUFFER 8
36# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060037
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020038# define CONFIG_SYS_FEC0_PINMUX 0
39# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
Wolfgang Denk53677ef2008-05-20 16:00:29 +020040# define MCFFEC_TOUT_LOOP 50000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
42# ifndef CONFIG_SYS_DISCOVER_PHY
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060043# define FECDUPLEX FULL
44# define FECSPEED _100BASET
45# else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020046# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
47# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060048# endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049# endif /* CONFIG_SYS_DISCOVER_PHY */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060050#endif
51
52#define CONFIG_MCFRTC
53#undef RTC_DEBUG
54
55/* Timer */
56#define CONFIG_MCFTMR
57#undef CONFIG_MCFPIT
58
59/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +020060#define CONFIG_SYS_I2C
61#define CONFIG_SYS_I2C_FSL
62#define CONFIG_SYS_FSL_I2C_SPEED 80000
63#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
64#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060066
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060067#define CONFIG_UDP_CHECKSUM
68
69#ifdef CONFIG_MCFFEC
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060070# define CONFIG_IPADDR 192.162.1.2
71# define CONFIG_NETMASK 255.255.255.0
72# define CONFIG_SERVERIP 192.162.1.1
73# define CONFIG_GATEWAYIP 192.162.1.1
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060074#endif /* FEC_ENET */
75
76#define CONFIG_HOSTNAME M5373EVB
77#define CONFIG_EXTRA_ENV_SETTINGS \
78 "netdev=eth0\0" \
Marek Vasut5368c552012-09-23 17:41:24 +020079 "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060080 "u-boot=u-boot.bin\0" \
81 "load=tftp ${loadaddr) ${u-boot}\0" \
82 "upd=run load; run prog\0" \
Jason Jin09933fb2011-08-19 10:10:40 +080083 "prog=prot off 0 3ffff;" \
84 "era 0 3ffff;" \
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060085 "cp.b ${loadaddr} 0 ${filesize};" \
86 "save\0" \
87 ""
88
89#define CONFIG_PRAM 512 /* 512 KB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#define CONFIG_SYS_LONGHELP /* undef to save memory */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060091
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092#define CONFIG_SYS_LOAD_ADDR 0x40010000
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060093
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094#define CONFIG_SYS_CLK 80000000
95#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060096
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#define CONFIG_SYS_MBAR 0xFC000000
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060098
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600100
101/*
102 * Low Level Configuration Settings
103 * (address mappings, register initial values, etc.)
104 * You should know what you are doing if you make changes here.
105 */
106/*-----------------------------------------------------------------------
107 * Definitions for initial stack pointer and data area (in DPRAM)
108 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200110#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_INIT_RAM_CTRL 0x221
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200112#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600114
115/*-----------------------------------------------------------------------
116 * Start addresses for the final memory configuration
117 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600119 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_SDRAM_BASE 0x40000000
121#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
122#define CONFIG_SYS_SDRAM_CFG1 0x53722730
123#define CONFIG_SYS_SDRAM_CFG2 0x56670000
124#define CONFIG_SYS_SDRAM_CTRL 0xE1092000
125#define CONFIG_SYS_SDRAM_EMOD 0x40010000
126#define CONFIG_SYS_SDRAM_MODE 0x018D0000
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600127
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
129#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600130
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
132#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600133
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
135#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600136
137/*
138 * For booting Linux, the board info and command line data
139 * have to be in the first 8 MB of memory, since this is
140 * the maximum mapped by the Linux kernel during initialization ??
141 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
TsiChung Liewd6e4baf2009-01-27 12:57:47 +0000143#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600144
145/*-----------------------------------------------------------------------
146 * FLASH organization
147 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_FLASH_CFI
149#ifdef CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200150# define CONFIG_FLASH_CFI_DRIVER 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
152# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
153# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
154# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
155# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600156#endif
157
Alison Wang2ee03c62012-03-25 19:18:14 +0000158#ifdef CONFIG_NANDFLASH_SIZE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159# define CONFIG_SYS_MAX_NAND_DEVICE 1
160# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
161# define CONFIG_SYS_NAND_SIZE 1
162# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600163# define NAND_ALLOW_ERASE_ALL 1
164# define CONFIG_JFFS2_NAND 1
165# define CONFIG_JFFS2_DEV "nand0"
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166# define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1)
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600167# define CONFIG_JFFS2_PART_OFFSET 0x00000000
168#endif
169
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600171
172/* Configuration for environment
173 * Environment is embedded in u-boot in the second sector of the flash
174 */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200175#define CONFIG_ENV_OFFSET 0x4000
176#define CONFIG_ENV_SECT_SIZE 0x2000
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600177
angelo@sysam.it5296cb12015-03-29 22:54:16 +0200178#define LDS_BOARD_TEXT \
Simon Glass0649cd02017-08-03 12:21:49 -0600179 . = DEFINED(env_offset) ? env_offset : .; \
180 env/embedded.o(.text*);
angelo@sysam.it5296cb12015-03-29 22:54:16 +0200181
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600182/*-----------------------------------------------------------------------
183 * Cache Configuration
184 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_CACHELINE_SIZE 16
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600186
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600187#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200188 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600189#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200190 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600191#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
192#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
193 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
194 CF_ACR_EN | CF_ACR_SM_ALL)
195#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
196 CF_CACR_DCM_P)
197
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600198/*-----------------------------------------------------------------------
199 * Chipselect bank definitions
200 */
201/*
202 * CS0 - NOR Flash 1, 2, 4, or 8MB
203 * CS1 - CompactFlash and registers
204 * CS2 - NAND Flash 16, 32, or 64MB
205 * CS3 - Available
206 * CS4 - Available
207 * CS5 - Available
208 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_CS0_BASE 0
210#define CONFIG_SYS_CS0_MASK 0x007f0001
211#define CONFIG_SYS_CS0_CTRL 0x00001fa0
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600212
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_CS1_BASE 0x10000000
214#define CONFIG_SYS_CS1_MASK 0x001f0001
215#define CONFIG_SYS_CS1_CTRL 0x002A3780
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600216
Alison Wang2ee03c62012-03-25 19:18:14 +0000217#ifdef CONFIG_NANDFLASH_SIZE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CONFIG_SYS_CS2_BASE 0x20000000
Alison Wang2ee03c62012-03-25 19:18:14 +0000219#define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_CS2_CTRL 0x00001f60
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600221#endif
222
223#endif /* _M5373EVB_H */