Benoît Thébaudeau | 112fd2e | 2013-04-23 10:17:44 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2013 ADVANSEE |
| 3 | * Benoît Thébaudeau <benoit.thebaudeau@advansee.com> |
| 4 | * |
| 5 | * Based on Dirk Behme's |
| 6 | * https://github.com/dirkbehme/u-boot-imx6/blob/28b17e9/drivers/misc/imx_otp.c, |
| 7 | * which is based on Freescale's |
| 8 | * http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/tree/drivers/misc/imx_otp.c?h=imx_v2009.08_1.1.0&id=9aa74e6, |
| 9 | * which is: |
| 10 | * Copyright (C) 2011 Freescale Semiconductor, Inc. |
| 11 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 12 | * SPDX-License-Identifier: GPL-2.0+ |
Benoît Thébaudeau | 112fd2e | 2013-04-23 10:17:44 +0000 | [diff] [blame] | 13 | */ |
| 14 | |
| 15 | #include <common.h> |
| 16 | #include <fuse.h> |
| 17 | #include <asm/errno.h> |
| 18 | #include <asm/io.h> |
| 19 | #include <asm/arch/clock.h> |
| 20 | #include <asm/arch/imx-regs.h> |
| 21 | |
| 22 | #define BO_CTRL_WR_UNLOCK 16 |
| 23 | #define BM_CTRL_WR_UNLOCK 0xffff0000 |
| 24 | #define BV_CTRL_WR_UNLOCK_KEY 0x3e77 |
| 25 | #define BM_CTRL_ERROR 0x00000200 |
| 26 | #define BM_CTRL_BUSY 0x00000100 |
| 27 | #define BO_CTRL_ADDR 0 |
| 28 | #define BM_CTRL_ADDR 0x0000007f |
| 29 | |
| 30 | #define BO_TIMING_STROBE_READ 16 |
| 31 | #define BM_TIMING_STROBE_READ 0x003f0000 |
| 32 | #define BV_TIMING_STROBE_READ_NS 37 |
| 33 | #define BO_TIMING_RELAX 12 |
| 34 | #define BM_TIMING_RELAX 0x0000f000 |
| 35 | #define BV_TIMING_RELAX_NS 17 |
| 36 | #define BO_TIMING_STROBE_PROG 0 |
| 37 | #define BM_TIMING_STROBE_PROG 0x00000fff |
| 38 | #define BV_TIMING_STROBE_PROG_US 10 |
| 39 | |
| 40 | #define BM_READ_CTRL_READ_FUSE 0x00000001 |
| 41 | |
| 42 | #define BF(value, field) (((value) << BO_##field) & BM_##field) |
| 43 | |
| 44 | #define WRITE_POSTAMBLE_US 2 |
| 45 | |
| 46 | static void wait_busy(struct ocotp_regs *regs, unsigned int delay_us) |
| 47 | { |
| 48 | while (readl(®s->ctrl) & BM_CTRL_BUSY) |
| 49 | udelay(delay_us); |
| 50 | } |
| 51 | |
| 52 | static void clear_error(struct ocotp_regs *regs) |
| 53 | { |
| 54 | writel(BM_CTRL_ERROR, ®s->ctrl_clr); |
| 55 | } |
| 56 | |
| 57 | static int prepare_access(struct ocotp_regs **regs, u32 bank, u32 word, |
| 58 | int assert, const char *caller) |
| 59 | { |
| 60 | *regs = (struct ocotp_regs *)OCOTP_BASE_ADDR; |
| 61 | |
| 62 | if (bank >= ARRAY_SIZE((*regs)->bank) || |
| 63 | word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 2 || |
| 64 | !assert) { |
| 65 | printf("mxc_ocotp %s(): Invalid argument\n", caller); |
| 66 | return -EINVAL; |
| 67 | } |
| 68 | |
| 69 | enable_ocotp_clk(1); |
| 70 | |
| 71 | wait_busy(*regs, 1); |
| 72 | clear_error(*regs); |
| 73 | |
| 74 | return 0; |
| 75 | } |
| 76 | |
| 77 | static int finish_access(struct ocotp_regs *regs, const char *caller) |
| 78 | { |
| 79 | u32 err; |
| 80 | |
| 81 | err = !!(readl(®s->ctrl) & BM_CTRL_ERROR); |
| 82 | clear_error(regs); |
| 83 | |
Benoît Thébaudeau | 112fd2e | 2013-04-23 10:17:44 +0000 | [diff] [blame] | 84 | if (err) { |
| 85 | printf("mxc_ocotp %s(): Access protect error\n", caller); |
| 86 | return -EIO; |
| 87 | } |
| 88 | |
| 89 | return 0; |
| 90 | } |
| 91 | |
| 92 | static int prepare_read(struct ocotp_regs **regs, u32 bank, u32 word, u32 *val, |
| 93 | const char *caller) |
| 94 | { |
| 95 | return prepare_access(regs, bank, word, val != NULL, caller); |
| 96 | } |
| 97 | |
| 98 | int fuse_read(u32 bank, u32 word, u32 *val) |
| 99 | { |
| 100 | struct ocotp_regs *regs; |
| 101 | int ret; |
| 102 | |
| 103 | ret = prepare_read(®s, bank, word, val, __func__); |
| 104 | if (ret) |
| 105 | return ret; |
| 106 | |
| 107 | *val = readl(®s->bank[bank].fuse_regs[word << 2]); |
| 108 | |
| 109 | return finish_access(regs, __func__); |
| 110 | } |
| 111 | |
| 112 | static void set_timing(struct ocotp_regs *regs) |
| 113 | { |
| 114 | u32 ipg_clk; |
| 115 | u32 relax, strobe_read, strobe_prog; |
| 116 | u32 timing; |
| 117 | |
| 118 | ipg_clk = mxc_get_clock(MXC_IPG_CLK); |
| 119 | |
| 120 | relax = DIV_ROUND_UP(ipg_clk * BV_TIMING_RELAX_NS, 1000000000) - 1; |
| 121 | strobe_read = DIV_ROUND_UP(ipg_clk * BV_TIMING_STROBE_READ_NS, |
| 122 | 1000000000) + 2 * (relax + 1) - 1; |
Masahiro Yamada | 4515992 | 2014-11-07 03:03:26 +0900 | [diff] [blame] | 123 | strobe_prog = DIV_ROUND_CLOSEST(ipg_clk * BV_TIMING_STROBE_PROG_US, |
| 124 | 1000000) + 2 * (relax + 1) - 1; |
Benoît Thébaudeau | 112fd2e | 2013-04-23 10:17:44 +0000 | [diff] [blame] | 125 | |
| 126 | timing = BF(strobe_read, TIMING_STROBE_READ) | |
| 127 | BF(relax, TIMING_RELAX) | |
| 128 | BF(strobe_prog, TIMING_STROBE_PROG); |
| 129 | |
| 130 | clrsetbits_le32(®s->timing, BM_TIMING_STROBE_READ | BM_TIMING_RELAX | |
| 131 | BM_TIMING_STROBE_PROG, timing); |
| 132 | } |
| 133 | |
| 134 | static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word, |
| 135 | int write) |
| 136 | { |
| 137 | u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0; |
| 138 | u32 addr = bank << 3 | word; |
| 139 | |
| 140 | set_timing(regs); |
| 141 | clrsetbits_le32(®s->ctrl, BM_CTRL_WR_UNLOCK | BM_CTRL_ADDR, |
| 142 | BF(wr_unlock, CTRL_WR_UNLOCK) | |
| 143 | BF(addr, CTRL_ADDR)); |
| 144 | } |
| 145 | |
| 146 | int fuse_sense(u32 bank, u32 word, u32 *val) |
| 147 | { |
| 148 | struct ocotp_regs *regs; |
| 149 | int ret; |
| 150 | |
| 151 | ret = prepare_read(®s, bank, word, val, __func__); |
| 152 | if (ret) |
| 153 | return ret; |
| 154 | |
| 155 | setup_direct_access(regs, bank, word, false); |
| 156 | writel(BM_READ_CTRL_READ_FUSE, ®s->read_ctrl); |
| 157 | wait_busy(regs, 1); |
| 158 | *val = readl(®s->read_fuse_data); |
| 159 | |
| 160 | return finish_access(regs, __func__); |
| 161 | } |
| 162 | |
| 163 | static int prepare_write(struct ocotp_regs **regs, u32 bank, u32 word, |
| 164 | const char *caller) |
| 165 | { |
| 166 | return prepare_access(regs, bank, word, true, caller); |
| 167 | } |
| 168 | |
| 169 | int fuse_prog(u32 bank, u32 word, u32 val) |
| 170 | { |
| 171 | struct ocotp_regs *regs; |
| 172 | int ret; |
| 173 | |
| 174 | ret = prepare_write(®s, bank, word, __func__); |
| 175 | if (ret) |
| 176 | return ret; |
| 177 | |
| 178 | setup_direct_access(regs, bank, word, true); |
| 179 | writel(val, ®s->data); |
| 180 | wait_busy(regs, BV_TIMING_STROBE_PROG_US); |
| 181 | udelay(WRITE_POSTAMBLE_US); |
| 182 | |
| 183 | return finish_access(regs, __func__); |
| 184 | } |
| 185 | |
| 186 | int fuse_override(u32 bank, u32 word, u32 val) |
| 187 | { |
| 188 | struct ocotp_regs *regs; |
| 189 | int ret; |
| 190 | |
| 191 | ret = prepare_write(®s, bank, word, __func__); |
| 192 | if (ret) |
| 193 | return ret; |
| 194 | |
| 195 | writel(val, ®s->bank[bank].fuse_regs[word << 2]); |
| 196 | |
| 197 | return finish_access(regs, __func__); |
| 198 | } |