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wdenk42d1f032003-10-15 23:53:47 +00001/*
Srikanth Srinivasanab48ca12010-02-10 17:32:43 +08002 * Copyright 2004,2007-2010 Freescale Semiconductor, Inc.
wdenk42d1f032003-10-15 23:53:47 +00003 * (C) Copyright 2002, 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
5 *
6 * (C) Copyright 2000
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
Andy Fleming75b9d4a2008-08-31 16:33:26 -050028#include <config.h>
wdenk42d1f032003-10-15 23:53:47 +000029#include <common.h>
30#include <watchdog.h>
31#include <command.h>
Andy Fleming80522dc2008-10-30 16:51:33 -050032#include <fsl_esdhc.h>
wdenk42d1f032003-10-15 23:53:47 +000033#include <asm/cache.h>
Sergei Poselenov740280e2008-06-06 15:42:40 +020034#include <asm/io.h>
wdenk42d1f032003-10-15 23:53:47 +000035
James Yang591933c2008-02-08 16:44:53 -060036DECLARE_GLOBAL_DATA_PTR;
37
wdenk42d1f032003-10-15 23:53:47 +000038int checkcpu (void)
39{
wdenk97d80fc2004-06-09 00:34:46 +000040 sys_info_t sysinfo;
wdenk97d80fc2004-06-09 00:34:46 +000041 uint pvr, svr;
Jon Loeligerd9b94f22005-07-25 14:05:07 -050042 uint fam;
wdenk97d80fc2004-06-09 00:34:46 +000043 uint ver;
44 uint major, minor;
Kumar Gala4dbdb762008-06-10 16:53:46 -050045 struct cpu_type *cpu;
Wolfgang Denk08ef89e2008-10-19 02:35:49 +020046 char buf1[32], buf2[32];
Kumar Gala9ce3c222010-04-13 11:07:57 -050047#if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020048 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Kumar Gala9ce3c222010-04-13 11:07:57 -050049#endif /* CONFIG_FSL_CORENET */
Srikanth Srinivasanab48ca12010-02-10 17:32:43 +080050#ifdef CONFIG_DDR_CLK_FREQ
51 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
52 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
53#else
Kumar Gala39aaca12009-03-19 02:46:19 -050054#ifdef CONFIG_FSL_CORENET
55 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
56 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
57#else
Kumar Galaee1e35b2008-05-29 01:21:24 -050058 u32 ddr_ratio = 0;
Srikanth Srinivasanab48ca12010-02-10 17:32:43 +080059#endif /* CONFIG_FSL_CORENET */
Kumar Gala39aaca12009-03-19 02:46:19 -050060#endif /* CONFIG_DDR_CLK_FREQ */
Haiying Wang2fc7eb02009-01-15 11:58:35 -050061 int i;
wdenk42d1f032003-10-15 23:53:47 +000062
wdenk97d80fc2004-06-09 00:34:46 +000063 svr = get_svr();
wdenk97d80fc2004-06-09 00:34:46 +000064 major = SVR_MAJ(svr);
Kumar Galaef50d6c2008-08-12 11:14:19 -050065#ifdef CONFIG_MPC8536
66 major &= 0x7; /* the msb of this nibble is a mfg code */
67#endif
wdenk97d80fc2004-06-09 00:34:46 +000068 minor = SVR_MIN(svr);
69
Poonam Aggrwal0e870982009-07-31 12:08:14 +053070 if (cpu_numcores() > 1) {
Poonam Aggrwal21170c82009-09-03 19:42:40 +053071#ifndef CONFIG_MP
72 puts("Unicore software on multiprocessor system!!\n"
73 "To enable mutlticore build define CONFIG_MP\n");
74#endif
Poonam Aggrwal0e870982009-07-31 12:08:14 +053075 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
76 printf("CPU%d: ", pic->whoami);
77 } else {
78 puts("CPU: ");
79 }
Andy Fleming1ced1212008-02-06 01:19:40 -060080
Poonam Aggrwal0e870982009-07-31 12:08:14 +053081 cpu = gd->cpu;
82
Poonam Aggrwal58442dc2009-09-02 13:35:21 +053083 puts(cpu->name);
84 if (IS_E_PROCESSOR(svr))
85 puts("E");
Andy Fleming1ced1212008-02-06 01:19:40 -060086
wdenk97d80fc2004-06-09 00:34:46 +000087 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
wdenk42d1f032003-10-15 23:53:47 +000088
wdenk6c9e7892005-03-15 22:56:53 +000089 pvr = get_pvr();
Jon Loeligerd9b94f22005-07-25 14:05:07 -050090 fam = PVR_FAM(pvr);
wdenk6c9e7892005-03-15 22:56:53 +000091 ver = PVR_VER(pvr);
92 major = PVR_MAJ(pvr);
93 minor = PVR_MIN(pvr);
94
95 printf("Core: ");
Jon Loeligerd9b94f22005-07-25 14:05:07 -050096 switch (fam) {
97 case PVR_FAM(PVR_85xx):
wdenk6c9e7892005-03-15 22:56:53 +000098 puts("E500");
99 break;
100 default:
101 puts("Unknown");
102 break;
103 }
Kumar Gala0f060c32008-10-23 01:47:38 -0500104
105 if (PVR_MEM(pvr) == 0x03)
106 puts("MC");
107
wdenk6c9e7892005-03-15 22:56:53 +0000108 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
109
wdenk97d80fc2004-06-09 00:34:46 +0000110 get_sys_info(&sysinfo);
111
Kumar Galab29dee32009-02-04 09:35:57 -0600112 puts("Clock Configuration:");
Poonam Aggrwal0e870982009-07-31 12:08:14 +0530113 for (i = 0; i < cpu_numcores(); i++) {
Wolfgang Denk1bba30e2009-02-19 00:41:08 +0100114 if (!(i & 3))
115 printf ("\n ");
Haiying Wang2fc7eb02009-01-15 11:58:35 -0500116 printf("CPU%d:%-4s MHz, ",
117 i,strmhz(buf1, sysinfo.freqProcessor[i]));
Kumar Galab29dee32009-02-04 09:35:57 -0600118 }
119 printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
Kumar Galaee1e35b2008-05-29 01:21:24 -0500120
Kumar Gala39aaca12009-03-19 02:46:19 -0500121#ifdef CONFIG_FSL_CORENET
122 if (ddr_sync == 1) {
123 printf(" DDR:%-4s MHz (%s MT/s data rate) "
124 "(Synchronous), ",
125 strmhz(buf1, sysinfo.freqDDRBus/2),
126 strmhz(buf2, sysinfo.freqDDRBus));
127 } else {
128 printf(" DDR:%-4s MHz (%s MT/s data rate) "
129 "(Asynchronous), ",
130 strmhz(buf1, sysinfo.freqDDRBus/2),
131 strmhz(buf2, sysinfo.freqDDRBus));
132 }
133#else
Kumar Galad4357932007-12-07 04:59:26 -0600134 switch (ddr_ratio) {
135 case 0x0:
Wolfgang Denk08ef89e2008-10-19 02:35:49 +0200136 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
137 strmhz(buf1, sysinfo.freqDDRBus/2),
138 strmhz(buf2, sysinfo.freqDDRBus));
Kumar Galad4357932007-12-07 04:59:26 -0600139 break;
140 case 0x7:
Kumar Gala39aaca12009-03-19 02:46:19 -0500141 printf(" DDR:%-4s MHz (%s MT/s data rate) "
142 "(Synchronous), ",
Wolfgang Denk08ef89e2008-10-19 02:35:49 +0200143 strmhz(buf1, sysinfo.freqDDRBus/2),
144 strmhz(buf2, sysinfo.freqDDRBus));
Kumar Galad4357932007-12-07 04:59:26 -0600145 break;
146 default:
Kumar Gala39aaca12009-03-19 02:46:19 -0500147 printf(" DDR:%-4s MHz (%s MT/s data rate) "
148 "(Asynchronous), ",
Wolfgang Denk08ef89e2008-10-19 02:35:49 +0200149 strmhz(buf1, sysinfo.freqDDRBus/2),
150 strmhz(buf2, sysinfo.freqDDRBus));
Kumar Galad4357932007-12-07 04:59:26 -0600151 break;
152 }
Kumar Gala39aaca12009-03-19 02:46:19 -0500153#endif
wdenk97d80fc2004-06-09 00:34:46 +0000154
Kumar Gala39aaca12009-03-19 02:46:19 -0500155 if (sysinfo.freqLocalBus > LCRR_CLKDIV) {
Trent Piephoada591d2008-12-03 15:16:37 -0800156 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
Kumar Gala39aaca12009-03-19 02:46:19 -0500157 } else {
Trent Piephoada591d2008-12-03 15:16:37 -0800158 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
159 sysinfo.freqLocalBus);
Kumar Gala39aaca12009-03-19 02:46:19 -0500160 }
wdenk97d80fc2004-06-09 00:34:46 +0000161
Andy Fleming1ced1212008-02-06 01:19:40 -0600162#ifdef CONFIG_CPM2
Wolfgang Denk08ef89e2008-10-19 02:35:49 +0200163 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
Andy Fleming1ced1212008-02-06 01:19:40 -0600164#endif
wdenk97d80fc2004-06-09 00:34:46 +0000165
Haiying Wangb3d7f202009-05-20 12:30:29 -0400166#ifdef CONFIG_QE
167 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE));
168#endif
169
Kumar Gala39aaca12009-03-19 02:46:19 -0500170#ifdef CONFIG_SYS_DPAA_FMAN
171 for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
172 printf(" FMAN%d: %s MHz\n", i,
173 strmhz(buf1, sysinfo.freqFMan[i]));
174 }
175#endif
176
177#ifdef CONFIG_SYS_DPAA_PME
178 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME));
179#endif
180
wdenk6c9e7892005-03-15 22:56:53 +0000181 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
wdenk42d1f032003-10-15 23:53:47 +0000182
183 return 0;
184}
185
186
187/* ------------------------------------------------------------------------- */
188
189int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
190{
Kumar Galac3483222009-09-08 13:46:46 -0500191/* Everything after the first generation of PQ3 parts has RSTCR */
192#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
193 defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560)
Sergei Poselenov793670c2008-05-08 14:17:08 +0200194 unsigned long val, msr;
195
wdenk42d1f032003-10-15 23:53:47 +0000196 /*
197 * Initiate hard reset in debug control register DBCR0
Kumar Galac3483222009-09-08 13:46:46 -0500198 * Make sure MSR[DE] = 1. This only resets the core.
wdenk42d1f032003-10-15 23:53:47 +0000199 */
Sergei Poselenov793670c2008-05-08 14:17:08 +0200200 msr = mfmsr ();
201 msr |= MSR_DE;
202 mtmsr (msr);
urwithsughosh@gmail.comdf909682007-09-24 13:32:13 -0400203
Sergei Poselenov793670c2008-05-08 14:17:08 +0200204 val = mfspr(DBCR0);
205 val |= 0x70000000;
206 mtspr(DBCR0,val);
Kumar Galac3483222009-09-08 13:46:46 -0500207#else
208 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
209 out_be32(&gur->rstcr, 0x2); /* HRESET_REQ */
210 udelay(100);
211#endif
Sergei Poselenov793670c2008-05-08 14:17:08 +0200212
wdenk42d1f032003-10-15 23:53:47 +0000213 return 1;
214}
215
216
217/*
218 * Get timebase clock frequency
219 */
220unsigned long get_tbclk (void)
221{
Kumar Gala3c2a67e2009-09-17 01:52:37 -0500222#ifdef CONFIG_FSL_CORENET
223 return (gd->bus_clk + 8) / 16;
224#else
James Yang591933c2008-02-08 16:44:53 -0600225 return (gd->bus_clk + 4UL)/8UL;
Kumar Gala3c2a67e2009-09-17 01:52:37 -0500226#endif
wdenk42d1f032003-10-15 23:53:47 +0000227}
228
229
230#if defined(CONFIG_WATCHDOG)
231void
232watchdog_reset(void)
233{
234 int re_enable = disable_interrupts();
235 reset_85xx_watchdog();
236 if (re_enable) enable_interrupts();
237}
238
239void
240reset_85xx_watchdog(void)
241{
242 /*
243 * Clear TSR(WIS) bit by writing 1
244 */
245 unsigned long val;
Andy Fleming03b81b42007-04-23 01:44:44 -0500246 val = mfspr(SPRN_TSR);
247 val |= TSR_WIS;
248 mtspr(SPRN_TSR, val);
wdenk42d1f032003-10-15 23:53:47 +0000249}
250#endif /* CONFIG_WATCHDOG */
251
Sergei Poselenov740280e2008-06-06 15:42:40 +0200252/*
Sergei Poselenov59f63052008-08-15 15:42:11 +0200253 * Configures a UPM. The function requires the respective MxMR to be set
254 * before calling this function. "size" is the number or entries, not a sizeof.
Sergei Poselenov740280e2008-06-06 15:42:40 +0200255 */
256void upmconfig (uint upm, uint * table, uint size)
257{
258 int i, mdr, mad, old_mad = 0;
259 volatile u32 *mxmr;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
Sergei Poselenov740280e2008-06-06 15:42:40 +0200261 volatile u32 *brp,*orp;
262 volatile u8* dummy = NULL;
263 int upmmask;
264
265 switch (upm) {
266 case UPMA:
267 mxmr = &lbc->mamr;
268 upmmask = BR_MS_UPMA;
269 break;
270 case UPMB:
271 mxmr = &lbc->mbmr;
272 upmmask = BR_MS_UPMB;
273 break;
274 case UPMC:
275 mxmr = &lbc->mcmr;
276 upmmask = BR_MS_UPMC;
277 break;
278 default:
279 printf("%s: Bad UPM index %d to configure\n", __FUNCTION__, upm);
280 hang();
281 }
282
283 /* Find the address for the dummy write transaction */
284 for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8;
285 i++, brp += 2, orp += 2) {
Wolfgang Denke093a242008-06-28 23:34:37 +0200286
Sergei Poselenov740280e2008-06-06 15:42:40 +0200287 /* Look for a valid BR with selected UPM */
Sergei Poselenov59f63052008-08-15 15:42:11 +0200288 if ((in_be32(brp) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) {
289 dummy = (volatile u8*)(in_be32(brp) & BR_BA);
Sergei Poselenov740280e2008-06-06 15:42:40 +0200290 break;
291 }
292 }
293
294 if (i == 8) {
295 printf("Error: %s() could not find matching BR\n", __FUNCTION__);
296 hang();
297 }
298
299 for (i = 0; i < size; i++) {
300 /* 1 */
Sergei Poselenov59f63052008-08-15 15:42:11 +0200301 out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_WARR | i);
Sergei Poselenov740280e2008-06-06 15:42:40 +0200302 /* 2 */
303 out_be32(&lbc->mdr, table[i]);
304 /* 3 */
305 mdr = in_be32(&lbc->mdr);
306 /* 4 */
307 *(volatile u8 *)dummy = 0;
308 /* 5 */
309 do {
Sergei Poselenov59f63052008-08-15 15:42:11 +0200310 mad = in_be32(mxmr) & MxMR_MAD_MSK;
Sergei Poselenov740280e2008-06-06 15:42:40 +0200311 } while (mad <= old_mad && !(!mad && i == (size-1)));
312 old_mad = mad;
313 }
Sergei Poselenov59f63052008-08-15 15:42:11 +0200314 out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_NORM);
Sergei Poselenov740280e2008-06-06 15:42:40 +0200315}
Ben Warrendd354792008-06-23 22:57:27 -0700316
Andy Fleming80522dc2008-10-30 16:51:33 -0500317/*
318 * Initializes on-chip MMC controllers.
319 * to override, implement board_mmc_init()
320 */
321int cpu_mmc_init(bd_t *bis)
322{
323#ifdef CONFIG_FSL_ESDHC
324 return fsl_esdhc_mmc_init(bis);
325#else
326 return 0;
327#endif
328}