Simon Glass | 8ef0757 | 2014-11-12 22:42:07 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2014 Google, Inc |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | #include <common.h> |
Simon Glass | 22e131c | 2014-11-14 20:56:45 -0700 | [diff] [blame] | 8 | #include <cros_ec.h> |
Simon Glass | 801f4f1 | 2015-03-05 12:25:32 -0700 | [diff] [blame] | 9 | #include <dm.h> |
Simon Glass | 437c2b7 | 2014-11-12 22:42:25 -0700 | [diff] [blame] | 10 | #include <asm/gpio.h> |
Bin Meng | 2795573 | 2014-12-12 21:05:23 +0800 | [diff] [blame] | 11 | #include <asm/io.h> |
| 12 | #include <asm/pci.h> |
| 13 | #include <asm/arch/pch.h> |
Simon Glass | 8ef0757 | 2014-11-12 22:42:07 -0700 | [diff] [blame] | 14 | |
| 15 | int arch_early_init_r(void) |
| 16 | { |
Simon Glass | 801f4f1 | 2015-03-05 12:25:32 -0700 | [diff] [blame] | 17 | struct udevice *dev; |
| 18 | int ret; |
| 19 | |
| 20 | /* Make sure the platform controller hub is up and running */ |
| 21 | ret = uclass_get_device(UCLASS_PCH, 0, &dev); |
| 22 | if (ret) |
| 23 | return ret; |
| 24 | |
Simon Glass | 8ef0757 | 2014-11-12 22:42:07 -0700 | [diff] [blame] | 25 | return 0; |
| 26 | } |
| 27 | |
Simon Glass | 437c2b7 | 2014-11-12 22:42:25 -0700 | [diff] [blame] | 28 | static const struct pch_gpio_set1 pch_gpio_set1_mode = { |
| 29 | .gpio0 = GPIO_MODE_GPIO, /* NMI_DBG# */ |
| 30 | .gpio3 = GPIO_MODE_GPIO, /* ALS_INT# */ |
| 31 | .gpio5 = GPIO_MODE_GPIO, /* SIM_DET */ |
| 32 | .gpio7 = GPIO_MODE_GPIO, /* EC_SCI# */ |
| 33 | .gpio8 = GPIO_MODE_GPIO, /* EC_SMI# */ |
| 34 | .gpio9 = GPIO_MODE_GPIO, /* RECOVERY# */ |
| 35 | .gpio10 = GPIO_MODE_GPIO, /* SPD vector D3 */ |
| 36 | .gpio11 = GPIO_MODE_GPIO, /* smbalert#, let's keep it initialized */ |
| 37 | .gpio12 = GPIO_MODE_GPIO, /* TP_INT# */ |
| 38 | .gpio14 = GPIO_MODE_GPIO, /* Touch_INT_L */ |
| 39 | .gpio15 = GPIO_MODE_GPIO, /* EC_LID_OUT# (EC_WAKE#) */ |
| 40 | .gpio21 = GPIO_MODE_GPIO, /* EC_IN_RW */ |
| 41 | .gpio24 = GPIO_MODE_GPIO, /* DDR3L_EN */ |
| 42 | .gpio28 = GPIO_MODE_GPIO, /* SLP_ME_CSW_DEV# */ |
| 43 | }; |
| 44 | |
| 45 | static const struct pch_gpio_set1 pch_gpio_set1_direction = { |
| 46 | .gpio0 = GPIO_DIR_INPUT, |
| 47 | .gpio3 = GPIO_DIR_INPUT, |
| 48 | .gpio5 = GPIO_DIR_INPUT, |
| 49 | .gpio7 = GPIO_DIR_INPUT, |
| 50 | .gpio8 = GPIO_DIR_INPUT, |
| 51 | .gpio9 = GPIO_DIR_INPUT, |
| 52 | .gpio10 = GPIO_DIR_INPUT, |
| 53 | .gpio11 = GPIO_DIR_INPUT, |
| 54 | .gpio12 = GPIO_DIR_INPUT, |
| 55 | .gpio14 = GPIO_DIR_INPUT, |
| 56 | .gpio15 = GPIO_DIR_INPUT, |
| 57 | .gpio21 = GPIO_DIR_INPUT, |
| 58 | .gpio24 = GPIO_DIR_OUTPUT, |
| 59 | .gpio28 = GPIO_DIR_INPUT, |
| 60 | }; |
| 61 | |
| 62 | static const struct pch_gpio_set1 pch_gpio_set1_level = { |
| 63 | .gpio1 = GPIO_LEVEL_HIGH, |
| 64 | .gpio6 = GPIO_LEVEL_HIGH, |
| 65 | .gpio24 = GPIO_LEVEL_LOW, |
| 66 | }; |
| 67 | |
| 68 | static const struct pch_gpio_set1 pch_gpio_set1_invert = { |
| 69 | .gpio7 = GPIO_INVERT, |
| 70 | .gpio8 = GPIO_INVERT, |
| 71 | .gpio12 = GPIO_INVERT, |
| 72 | .gpio14 = GPIO_INVERT, |
| 73 | .gpio15 = GPIO_INVERT, |
| 74 | }; |
| 75 | |
| 76 | static const struct pch_gpio_set2 pch_gpio_set2_mode = { |
| 77 | .gpio36 = GPIO_MODE_GPIO, /* W_DISABLE_L */ |
| 78 | .gpio41 = GPIO_MODE_GPIO, /* SPD vector D0 */ |
| 79 | .gpio42 = GPIO_MODE_GPIO, /* SPD vector D1 */ |
| 80 | .gpio43 = GPIO_MODE_GPIO, /* SPD vector D2 */ |
| 81 | .gpio57 = GPIO_MODE_GPIO, /* PCH_SPI_WP_D */ |
| 82 | .gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */ |
| 83 | }; |
| 84 | |
| 85 | static const struct pch_gpio_set2 pch_gpio_set2_direction = { |
| 86 | .gpio36 = GPIO_DIR_OUTPUT, |
| 87 | .gpio41 = GPIO_DIR_INPUT, |
| 88 | .gpio42 = GPIO_DIR_INPUT, |
| 89 | .gpio43 = GPIO_DIR_INPUT, |
| 90 | .gpio57 = GPIO_DIR_INPUT, |
| 91 | .gpio60 = GPIO_DIR_OUTPUT, |
| 92 | }; |
| 93 | |
| 94 | static const struct pch_gpio_set2 pch_gpio_set2_level = { |
| 95 | .gpio36 = GPIO_LEVEL_HIGH, |
| 96 | .gpio60 = GPIO_LEVEL_HIGH, |
| 97 | }; |
| 98 | |
| 99 | static const struct pch_gpio_set3 pch_gpio_set3_mode = { |
| 100 | }; |
| 101 | |
| 102 | static const struct pch_gpio_set3 pch_gpio_set3_direction = { |
| 103 | }; |
| 104 | |
| 105 | static const struct pch_gpio_set3 pch_gpio_set3_level = { |
| 106 | }; |
| 107 | |
| 108 | static const struct pch_gpio_map link_gpio_map = { |
| 109 | .set1 = { |
| 110 | .mode = &pch_gpio_set1_mode, |
| 111 | .direction = &pch_gpio_set1_direction, |
| 112 | .level = &pch_gpio_set1_level, |
| 113 | .invert = &pch_gpio_set1_invert, |
| 114 | }, |
| 115 | .set2 = { |
| 116 | .mode = &pch_gpio_set2_mode, |
| 117 | .direction = &pch_gpio_set2_direction, |
| 118 | .level = &pch_gpio_set2_level, |
| 119 | }, |
| 120 | .set3 = { |
| 121 | .mode = &pch_gpio_set3_mode, |
| 122 | .direction = &pch_gpio_set3_direction, |
| 123 | .level = &pch_gpio_set3_level, |
| 124 | }, |
| 125 | }; |
| 126 | |
| 127 | int board_early_init_f(void) |
| 128 | { |
| 129 | ich_gpio_set_gpio_map(&link_gpio_map); |
| 130 | |
| 131 | return 0; |
| 132 | } |
Bin Meng | 2795573 | 2014-12-12 21:05:23 +0800 | [diff] [blame] | 133 | |
Bin Meng | b71eec3 | 2014-12-17 15:50:38 +0800 | [diff] [blame] | 134 | void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio) |
Bin Meng | 2795573 | 2014-12-12 21:05:23 +0800 | [diff] [blame] | 135 | { |
| 136 | /* GPIO Set 1 */ |
| 137 | if (gpio->set1.level) |
| 138 | outl(*((u32 *)gpio->set1.level), gpiobase + GP_LVL); |
| 139 | if (gpio->set1.mode) |
| 140 | outl(*((u32 *)gpio->set1.mode), gpiobase + GPIO_USE_SEL); |
| 141 | if (gpio->set1.direction) |
| 142 | outl(*((u32 *)gpio->set1.direction), gpiobase + GP_IO_SEL); |
| 143 | if (gpio->set1.reset) |
| 144 | outl(*((u32 *)gpio->set1.reset), gpiobase + GP_RST_SEL1); |
| 145 | if (gpio->set1.invert) |
| 146 | outl(*((u32 *)gpio->set1.invert), gpiobase + GPI_INV); |
| 147 | if (gpio->set1.blink) |
| 148 | outl(*((u32 *)gpio->set1.blink), gpiobase + GPO_BLINK); |
| 149 | |
| 150 | /* GPIO Set 2 */ |
| 151 | if (gpio->set2.level) |
| 152 | outl(*((u32 *)gpio->set2.level), gpiobase + GP_LVL2); |
| 153 | if (gpio->set2.mode) |
| 154 | outl(*((u32 *)gpio->set2.mode), gpiobase + GPIO_USE_SEL2); |
| 155 | if (gpio->set2.direction) |
| 156 | outl(*((u32 *)gpio->set2.direction), gpiobase + GP_IO_SEL2); |
| 157 | if (gpio->set2.reset) |
| 158 | outl(*((u32 *)gpio->set2.reset), gpiobase + GP_RST_SEL2); |
| 159 | |
| 160 | /* GPIO Set 3 */ |
| 161 | if (gpio->set3.level) |
| 162 | outl(*((u32 *)gpio->set3.level), gpiobase + GP_LVL3); |
| 163 | if (gpio->set3.mode) |
| 164 | outl(*((u32 *)gpio->set3.mode), gpiobase + GPIO_USE_SEL3); |
| 165 | if (gpio->set3.direction) |
| 166 | outl(*((u32 *)gpio->set3.direction), gpiobase + GP_IO_SEL3); |
| 167 | if (gpio->set3.reset) |
| 168 | outl(*((u32 *)gpio->set3.reset), gpiobase + GP_RST_SEL3); |
| 169 | } |