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gerrit.cesnet.cz / github / trini / u-boot / 53c987f51391c1a221b0468aa0f37a3a6ce9181a / . / cpu / mpc85xx / ddr-gen3.c
blob: d7cc9db4e6b04fc509932a0530a2bf546b202929 [file] [log] [blame]
Kumar Gala2a6c2d72008-08-26 21:34:55 -0500[diff] [blame]1/*
2 * Copyright 2008 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
7 */
8
9#include <common.h>
10#include <asm/io.h>
11#include <asm/fsl_ddr_sdram.h>
12
13#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
14#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
15#endif
16
17void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
18 unsigned int ctrl_num)
19{
20 unsigned int i;
21 volatile ccsr_ddr_t *ddr;
22
23 switch (ctrl_num) {
24 case 0:
25 ddr = (void *)CFG_MPC85xx_DDR_ADDR;
26 break;
27 case 1:
28 ddr = (void *)CFG_MPC85xx_DDR2_ADDR;
29 break;
30 default:
31 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
32 return;
33 }
34
35 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
36 if (i == 0) {
37 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
38 out_be32(&ddr->cs0_config, regs->cs[i].config);
39 out_be32(&ddr->cs0_config_2, regs->cs[i].config_2);
40
41 } else if (i == 1) {
42 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
43 out_be32(&ddr->cs1_config, regs->cs[i].config);
44 out_be32(&ddr->cs1_config_2, regs->cs[i].config_2);
45
46 } else if (i == 2) {
47 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
48 out_be32(&ddr->cs2_config, regs->cs[i].config);
49 out_be32(&ddr->cs2_config_2, regs->cs[i].config_2);
50
51 } else if (i == 3) {
52 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
53 out_be32(&ddr->cs3_config, regs->cs[i].config);
54 out_be32(&ddr->cs3_config_2, regs->cs[i].config_2);
55 }
56 }
57
58 out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
59 out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
60 out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
61 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
62 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
63 out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
64 out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
65 out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
66 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
67 out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
68 out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
69 out_be32(&ddr->init_addr, regs->ddr_init_addr);
70 out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
71
72 out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4);
73 out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
74 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
75 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
76 out_be32(&ddr->ddr_pd_cntl, regs->ddr_pd_cntl);
77 out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
78 out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
79 out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
80
81 /*
82 * 32-bit workaround for DDR2
83 * 32_BE
84 */
85 if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2)
86 && in_be32(&ddr->sdram_cfg_2) & 0x80000) {
87 /* set DEBUG_1[31] */
88 u32 temp = in_be32(&ddr->debug_1);
89 out_be32(&ddr->debug_1, temp | 1);
90 }
91
92 /*
93 * 200 painful micro-seconds must elapse between
94 * the DDR clock setup and the DDR config enable.
95 */
96 udelay(200);
97 asm volatile("sync;isync");
98
99 out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
100
101 /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
102 while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
103 udelay(10000); /* throttle polling rate */
104 }
105}