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wdenk2d24a3a2004-06-09 21:50:45 +00001/*
2 * include/configs/mx1ads.h
wdenk49822e22004-06-19 21:19:10 +00003 *
wdenk2d24a3a2004-06-09 21:50:45 +00004 * (c) Copyright 2004
5 * Techware Information Technology, Inc.
6 * http://www.techware.com.tw/
7 *
8 * Ming-Len Wu <minglen_wu@techware.com.tw>
9 *
10 * This is the Configuration setting for Motorola MX1ADS board
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenk281e00a2004-08-01 22:48:16 +000019 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenk2d24a3a2004-06-09 21:50:45 +000020 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
wdenk2d24a3a2004-06-09 21:50:45 +000028#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
wdenk2d24a3a2004-06-09 21:50:45 +000032 * High Level Configuration Options
33 * (easy to change)
34 */
35#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
wdenk281e00a2004-08-01 22:48:16 +000036#define CONFIG_IMX 1 /* It's a Motorola MC9328 SoC */
37#define CONFIG_MX1ADS 1 /* on a Motorola MX1ADS Board */
38#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
39
40/*
41 * Select serial console configuration
42 */
43#define CONFIG_IMX_SERIAL1 /* internal uart 1 */
44/* #define _CONFIG_UART2 */ /* internal uart 2 */
45/* #define CONFIG_SILENT_CONSOLE */ /* use this to disable output */
wdenk2d24a3a2004-06-09 21:50:45 +000046
wdenk49822e22004-06-19 21:19:10 +000047#define BOARD_LATE_INIT 1
wdenk2d24a3a2004-06-09 21:50:45 +000048#define USE_920T_MMU 1
wdenk2d24a3a2004-06-09 21:50:45 +000049
wdenk49822e22004-06-19 21:19:10 +000050#if 0
wdenk2d24a3a2004-06-09 21:50:45 +000051#define CFG_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */
52#define CFG_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */
53#define CFG_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */
wdenk49822e22004-06-19 21:19:10 +000054#endif
wdenk2d24a3a2004-06-09 21:50:45 +000055
56/*
57 * Size of malloc() pool
58 */
59
60#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
wdenk281e00a2004-08-01 22:48:16 +000061
62
wdenk2d24a3a2004-06-09 21:50:45 +000063#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
64
65/*
66 * CS8900 Ethernet drivers
67 */
68#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */
69#define CS8900_BASE 0x15000300
wdenk281e00a2004-08-01 22:48:16 +000070#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */
wdenk2d24a3a2004-06-09 21:50:45 +000071
72/*
73 * select serial console configuration
74 */
75
wdenk281e00a2004-08-01 22:48:16 +000076/* #define CONFIG_UART1 */
wdenk2d24a3a2004-06-09 21:50:45 +000077/* #define CONFIG_UART2 1 */
78
79#define CONFIG_BAUDRATE 115200
80
81/***********************************************************
82 * Command definition
83 ***********************************************************/
84
85#define CONFIG_COMMANDS \
86 (CONFIG_CMD_DFL | \
87 CFG_CMD_CACHE | \
wdenk281e00a2004-08-01 22:48:16 +000088 CFG_CMD_REGINFO | \
wdenk49822e22004-06-19 21:19:10 +000089 CFG_CMD_ELF)
wdenk2d24a3a2004-06-09 21:50:45 +000090
91/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
92#include <cmd_confdefs.h>
93
94#define CONFIG_BOOTDELAY 3
wdenk281e00a2004-08-01 22:48:16 +000095#define CONFIG_BOOTARGS "root=/dev/msdk mem=48M"
wdenk2d24a3a2004-06-09 21:50:45 +000096#define CONFIG_BOOTFILE "mx1ads"
wdenk281e00a2004-08-01 22:48:16 +000097#define CONFIG_BOOTCOMMAND "tftp; bootm"
wdenk2d24a3a2004-06-09 21:50:45 +000098
99#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
100#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
101 /* what's this ? it's not used anywhere */
102#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
103#endif
104
105/*
106 * Miscellaneous configurable options
107 */
wdenk49822e22004-06-19 21:19:10 +0000108
wdenk281e00a2004-08-01 22:48:16 +0000109#define CFG_HUSH_PARSER 1
wdenk2d24a3a2004-06-09 21:50:45 +0000110#define CFG_PROMPT_HUSH_PS2 "> "
wdenk49822e22004-06-19 21:19:10 +0000111
wdenk281e00a2004-08-01 22:48:16 +0000112#define CFG_LONGHELP /* undef to save memory */
wdenk2d24a3a2004-06-09 21:50:45 +0000113
114#ifdef CFG_HUSH_PARSER
115#define CFG_PROMPT "MX1ADS$ " /* Monitor Command Prompt */
116#else
117#define CFG_PROMPT "MX1ADS=> " /* Monitor Command Prompt */
118#endif
119
wdenk281e00a2004-08-01 22:48:16 +0000120#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
121#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
wdenk2d24a3a2004-06-09 21:50:45 +0000122 /* Print Buffer Size */
wdenk281e00a2004-08-01 22:48:16 +0000123#define CFG_MAXARGS 16 /* max number of command args */
wdenk2d24a3a2004-06-09 21:50:45 +0000124#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
125
126#define CFG_MEMTEST_START 0x09000000 /* memtest works on */
127#define CFG_MEMTEST_END 0x0AF00000 /* 63 MB in DRAM */
128
wdenk281e00a2004-08-01 22:48:16 +0000129#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
130#define CFG_LOAD_ADDR 0x08800000 /* default load address */
131/*#define CFG_HZ 1000 */
132#define CFG_HZ 3686400
133#define CFG_CPUSPEED 0x141
wdenk2d24a3a2004-06-09 21:50:45 +0000134
135/* valid baudrates */
136#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
137
138/*-----------------------------------------------------------------------
139 * Stack sizes
140 *
141 * The stack sizes are set up in start.S using the settings below
142 */
143#define CONFIG_STACKSIZE (128*1024) /* regular stack */
144#ifdef CONFIG_USE_IRQ
145#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
146#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
147#endif
148
149/*-----------------------------------------------------------------------
150 * Physical Memory Map
151 */
wdenk49822e22004-06-19 21:19:10 +0000152
wdenk281e00a2004-08-01 22:48:16 +0000153#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */
154#define PHYS_SDRAM_1 0x08000000 /* SDRAM on CSD0 */
155#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
wdenk2d24a3a2004-06-09 21:50:45 +0000156
wdenk281e00a2004-08-01 22:48:16 +0000157#define CFG_MAX_FLASH_BANKS 1 /* 1 bank of SyncFlash */
158#define CFG_FLASH_BASE 0x0C000000 /* SyncFlash on CSD1 */
159#define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */
wdenk2d24a3a2004-06-09 21:50:45 +0000160
161/*-----------------------------------------------------------------------
162 * FLASH and environment organization
163 */
164
wdenk2d24a3a2004-06-09 21:50:45 +0000165#define CONFIG_SYNCFLASH 1
166#define PHYS_FLASH_SIZE 0x01000000
167#define CFG_MAX_FLASH_SECT (16)
wdenk281e00a2004-08-01 22:48:16 +0000168#define CFG_ENV_ADDR (CFG_FLASH_BASE+0x00ff8000)
wdenk49822e22004-06-19 21:19:10 +0000169
wdenk281e00a2004-08-01 22:48:16 +0000170#define CFG_ENV_IS_IN_FLASH 1
171#define CFG_ENV_SIZE 0x04000 /* Total Size of Environment Sector */
wdenk2d24a3a2004-06-09 21:50:45 +0000172#define CFG_ENV_SECT_SIZE 0x100000
wdenk281e00a2004-08-01 22:48:16 +0000173
174/*-----------------------------------------------------------------------
175 * Enable passing ATAGS
176 */
177
178#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
179#define CONFIG_SETUP_MEMORY_TAGS 1
180
181#define CONFIG_SYS_CLK_FREQ 16780000
182#define CONFIG_SYSPLL_CLK_FREQ 16000000
183
wdenk2d24a3a2004-06-09 21:50:45 +0000184#endif /* __CONFIG_H */