stroese | 771e05b | 2004-12-16 18:21:17 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2003 |
| 3 | * Ingo Assmus <ingo.assmus@keymile.com> |
| 4 | * |
| 5 | * based on - Driver for MV64360X ethernet ports |
| 6 | * Copyright (C) 2002 rabeeh@galileo.co.il |
| 7 | * |
| 8 | * See file CREDITS for list of people who contributed to this |
| 9 | * project. |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or |
| 12 | * modify it under the terms of the GNU General Public License as |
| 13 | * published by the Free Software Foundation; either version 2 of |
| 14 | * the License, or (at your option) any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; if not, write to the Free Software |
| 23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 24 | * MA 02111-1307 USA |
| 25 | */ |
| 26 | |
| 27 | /* |
| 28 | * mv_eth.c - header file for the polled mode GT ethernet driver |
| 29 | */ |
| 30 | #include <common.h> |
| 31 | #include <net.h> |
| 32 | #include <malloc.h> |
| 33 | |
| 34 | #include "mv_eth.h" |
| 35 | |
| 36 | /* enable Debug outputs */ |
| 37 | |
| 38 | #undef DEBUG_MV_ETH |
| 39 | |
| 40 | #ifdef DEBUG_MV_ETH |
| 41 | #define DEBUG |
| 42 | #define DP(x) x |
| 43 | #else |
| 44 | #define DP(x) |
| 45 | #endif |
| 46 | |
| 47 | #undef MV64360_CHECKSUM_OFFLOAD |
| 48 | /************************************************************************* |
| 49 | ************************************************************************** |
| 50 | ************************************************************************** |
| 51 | * The first part is the high level driver of the gigE ethernet ports. * |
| 52 | ************************************************************************** |
| 53 | ************************************************************************** |
| 54 | *************************************************************************/ |
| 55 | |
| 56 | /* Definition for configuring driver */ |
| 57 | /* #define UPDATE_STATS_BY_SOFTWARE */ |
| 58 | #undef MV64360_RX_QUEUE_FILL_ON_TASK |
| 59 | |
| 60 | |
| 61 | /* Constants */ |
| 62 | #define MAGIC_ETH_RUNNING 8031971 |
| 63 | #define MV64360_INTERNAL_SRAM_SIZE _256K |
| 64 | #define EXTRA_BYTES 32 |
| 65 | #define WRAP ETH_HLEN + 2 + 4 + 16 |
| 66 | #define BUFFER_MTU dev->mtu + WRAP |
| 67 | #define INT_CAUSE_UNMASK_ALL 0x0007ffff |
| 68 | #define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff |
| 69 | #ifdef MV64360_RX_FILL_ON_TASK |
| 70 | #define INT_CAUSE_MASK_ALL 0x00000000 |
| 71 | #define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL |
| 72 | #define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT |
| 73 | #endif |
| 74 | |
| 75 | /* Read/Write to/from MV64360 internal registers */ |
| 76 | #define MV_REG_READ(offset) my_le32_to_cpu(* (volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset)) |
| 77 | #define MV_REG_WRITE(offset,data) *(volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset) = my_cpu_to_le32 (data) |
| 78 | #define MV_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) |= ((unsigned int)my_cpu_to_le32(bits))) |
| 79 | #define MV_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) &= ~((unsigned int)my_cpu_to_le32(bits))) |
| 80 | |
| 81 | /* Static function declarations */ |
| 82 | static int mv64360_eth_real_open (struct eth_device *eth); |
| 83 | static int mv64360_eth_real_stop (struct eth_device *eth); |
| 84 | static struct net_device_stats *mv64360_eth_get_stats (struct eth_device |
| 85 | *dev); |
| 86 | static void eth_port_init_mac_tables (ETH_PORT eth_port_num); |
| 87 | static void mv64360_eth_update_stat (struct eth_device *dev); |
| 88 | bool db64360_eth_start (struct eth_device *eth); |
| 89 | unsigned int eth_read_mib_counter (ETH_PORT eth_port_num, |
| 90 | unsigned int mib_offset); |
| 91 | int mv64360_eth_receive (struct eth_device *dev); |
| 92 | |
| 93 | int mv64360_eth_xmit (struct eth_device *, volatile void *packet, int length); |
| 94 | |
| 95 | #ifndef UPDATE_STATS_BY_SOFTWARE |
| 96 | static void mv64360_eth_print_stat (struct eth_device *dev); |
| 97 | #endif |
| 98 | /* Processes a received packet */ |
| 99 | extern void NetReceive (volatile uchar *, int); |
| 100 | |
| 101 | extern unsigned int INTERNAL_REG_BASE_ADDR; |
| 102 | |
| 103 | /************************************************* |
| 104 | *Helper functions - used inside the driver only * |
| 105 | *************************************************/ |
| 106 | #ifdef DEBUG_MV_ETH |
| 107 | void print_globals (struct eth_device *dev) |
| 108 | { |
| 109 | printf ("Ethernet PRINT_Globals-Debug function\n"); |
| 110 | printf ("Base Address for ETH_PORT_INFO: %08x\n", |
| 111 | (unsigned int) dev->priv); |
| 112 | printf ("Base Address for mv64360_eth_priv: %08x\n", |
| 113 | (unsigned int) &(((ETH_PORT_INFO *) dev->priv)-> |
| 114 | port_private)); |
| 115 | |
| 116 | printf ("GT Internal Base Address: %08x\n", |
| 117 | INTERNAL_REG_BASE_ADDR); |
| 118 | printf ("Base Address for TX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_tx_desc_area_base[0], MV64360_TX_QUEUE_SIZE); |
| 119 | printf ("Base Address for RX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_rx_desc_area_base[0], MV64360_RX_QUEUE_SIZE); |
| 120 | printf ("Base Address for RX-Buffer: %08x allocated Bytes %d\n", |
| 121 | (unsigned int) ((ETH_PORT_INFO *) dev->priv)-> |
| 122 | p_rx_buffer_base[0], |
| 123 | (MV64360_RX_QUEUE_SIZE * MV64360_RX_BUFFER_SIZE) + 32); |
| 124 | printf ("Base Address for TX-Buffer: %08x allocated Bytes %d\n", |
| 125 | (unsigned int) ((ETH_PORT_INFO *) dev->priv)-> |
| 126 | p_tx_buffer_base[0], |
| 127 | (MV64360_TX_QUEUE_SIZE * MV64360_TX_BUFFER_SIZE) + 32); |
| 128 | } |
| 129 | #endif |
| 130 | |
| 131 | #define my_cpu_to_le32(x) my_le32_to_cpu((x)) |
| 132 | |
| 133 | unsigned long my_le32_to_cpu (unsigned long x) |
| 134 | { |
| 135 | return (((x & 0x000000ffU) << 24) | |
| 136 | ((x & 0x0000ff00U) << 8) | |
| 137 | ((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24)); |
| 138 | } |
| 139 | |
| 140 | |
| 141 | /********************************************************************** |
| 142 | * mv64360_eth_print_phy_status |
| 143 | * |
| 144 | * Prints gigabit ethenret phy status |
| 145 | * |
| 146 | * Input : pointer to ethernet interface network device structure |
| 147 | * Output : N/A |
| 148 | **********************************************************************/ |
| 149 | |
| 150 | static void mv64360_eth_print_phy_status (struct eth_device *dev) |
| 151 | { |
| 152 | struct mv64360_eth_priv *port_private; |
| 153 | unsigned int port_num; |
| 154 | ETH_PORT_INFO *ethernet_private = (ETH_PORT_INFO *) dev->priv; |
| 155 | unsigned int port_status, phy_reg_data; |
| 156 | |
| 157 | port_private = |
| 158 | (struct mv64360_eth_priv *) ethernet_private->port_private; |
| 159 | port_num = port_private->port_num; |
| 160 | |
| 161 | /* Check Link status on phy */ |
| 162 | eth_port_read_smi_reg (port_num, 1, &phy_reg_data); |
| 163 | if (!(phy_reg_data & 0x20)) { |
| 164 | printf ("Ethernet port changed link status to DOWN\n"); |
| 165 | } else { |
| 166 | port_status = |
| 167 | MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num)); |
| 168 | printf ("Ethernet status port %d: Link up", port_num); |
| 169 | printf (", %s", |
| 170 | (port_status & BIT2) ? "Full Duplex" : "Half Duplex"); |
| 171 | if (port_status & BIT4) |
| 172 | printf (", Speed 1 Gbps"); |
| 173 | else |
| 174 | printf (", %s", |
| 175 | (port_status & BIT5) ? "Speed 100 Mbps" : |
| 176 | "Speed 10 Mbps"); |
| 177 | printf ("\n"); |
| 178 | } |
| 179 | } |
| 180 | |
| 181 | /********************************************************************** |
| 182 | * u-boot entry functions for mv64360_eth |
| 183 | * |
| 184 | **********************************************************************/ |
| 185 | int db64360_eth_probe (struct eth_device *dev) |
| 186 | { |
| 187 | return ((int) db64360_eth_start (dev)); |
| 188 | } |
| 189 | |
| 190 | int db64360_eth_poll (struct eth_device *dev) |
| 191 | { |
| 192 | return mv64360_eth_receive (dev); |
| 193 | } |
| 194 | |
| 195 | int db64360_eth_transmit (struct eth_device *dev, volatile void *packet, |
| 196 | int length) |
| 197 | { |
| 198 | mv64360_eth_xmit (dev, packet, length); |
| 199 | return 0; |
| 200 | } |
| 201 | |
| 202 | void db64360_eth_disable (struct eth_device *dev) |
| 203 | { |
| 204 | mv64360_eth_stop (dev); |
| 205 | } |
| 206 | |
| 207 | |
| 208 | void mv6436x_eth_initialize (bd_t * bis) |
| 209 | { |
| 210 | struct eth_device *dev; |
| 211 | ETH_PORT_INFO *ethernet_private; |
| 212 | struct mv64360_eth_priv *port_private; |
| 213 | int devnum, x, temp; |
| 214 | char *s, *e, buf[64]; |
| 215 | |
| 216 | for (devnum = 0; devnum < MV_ETH_DEVS; devnum++) { |
| 217 | dev = calloc (sizeof (*dev), 1); |
| 218 | if (!dev) { |
| 219 | printf ("%s: mv_enet%d allocation failure, %s\n", |
| 220 | __FUNCTION__, devnum, "eth_device structure"); |
| 221 | return; |
| 222 | } |
| 223 | |
| 224 | /* must be less than NAMESIZE (16) */ |
| 225 | sprintf (dev->name, "mv_enet%d", devnum); |
| 226 | |
| 227 | #ifdef DEBUG |
| 228 | printf ("Initializing %s\n", dev->name); |
| 229 | #endif |
| 230 | |
| 231 | /* Extract the MAC address from the environment */ |
| 232 | switch (devnum) { |
| 233 | case 0: |
| 234 | s = "ethaddr"; |
| 235 | break; |
| 236 | |
| 237 | case 1: |
| 238 | s = "eth1addr"; |
| 239 | break; |
| 240 | |
| 241 | case 2: |
| 242 | s = "eth2addr"; |
| 243 | break; |
| 244 | |
| 245 | default: /* this should never happen */ |
| 246 | printf ("%s: Invalid device number %d\n", |
| 247 | __FUNCTION__, devnum); |
| 248 | return; |
| 249 | } |
| 250 | |
| 251 | temp = getenv_r (s, buf, sizeof (buf)); |
| 252 | s = (temp > 0) ? buf : NULL; |
| 253 | |
| 254 | #ifdef DEBUG |
| 255 | printf ("Setting MAC %d to %s\n", devnum, s); |
| 256 | #endif |
| 257 | for (x = 0; x < 6; ++x) { |
| 258 | dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0; |
| 259 | if (s) |
| 260 | s = (*e) ? e + 1 : e; |
| 261 | } |
| 262 | /* ronen - set the MAC addr in the HW */ |
| 263 | eth_port_uc_addr_set (devnum, dev->enetaddr, 0); |
| 264 | |
| 265 | dev->init = (void *) db64360_eth_probe; |
| 266 | dev->halt = (void *) ethernet_phy_reset; |
| 267 | dev->send = (void *) db64360_eth_transmit; |
| 268 | dev->recv = (void *) db64360_eth_poll; |
| 269 | |
Wolfgang Denk | 77ddac9 | 2005-10-13 16:45:02 +0200 | [diff] [blame] | 270 | ethernet_private = |
stroese | 771e05b | 2004-12-16 18:21:17 +0000 | [diff] [blame] | 271 | calloc (sizeof (*ethernet_private), 1); |
Wolfgang Denk | 77ddac9 | 2005-10-13 16:45:02 +0200 | [diff] [blame] | 272 | dev->priv = (void *) ethernet_private; |
stroese | 771e05b | 2004-12-16 18:21:17 +0000 | [diff] [blame] | 273 | if (!ethernet_private) { |
| 274 | printf ("%s: %s allocation failure, %s\n", |
| 275 | __FUNCTION__, dev->name, |
| 276 | "Private Device Structure"); |
| 277 | free (dev); |
| 278 | return; |
| 279 | } |
| 280 | /* start with an zeroed ETH_PORT_INFO */ |
| 281 | memset (ethernet_private, 0, sizeof (ETH_PORT_INFO)); |
| 282 | memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6); |
| 283 | |
| 284 | /* set pointer to memory for stats data structure etc... */ |
Wolfgang Denk | 77ddac9 | 2005-10-13 16:45:02 +0200 | [diff] [blame] | 285 | port_private = |
stroese | 771e05b | 2004-12-16 18:21:17 +0000 | [diff] [blame] | 286 | calloc (sizeof (*ethernet_private), 1); |
Wolfgang Denk | f013dac | 2005-12-04 00:40:34 +0100 | [diff] [blame] | 287 | ethernet_private->port_private = (void *)port_private; |
stroese | 771e05b | 2004-12-16 18:21:17 +0000 | [diff] [blame] | 288 | if (!port_private) { |
| 289 | printf ("%s: %s allocation failure, %s\n", |
| 290 | __FUNCTION__, dev->name, |
| 291 | "Port Private Device Structure"); |
| 292 | |
| 293 | free (ethernet_private); |
| 294 | free (dev); |
| 295 | return; |
| 296 | } |
| 297 | |
| 298 | port_private->stats = |
| 299 | calloc (sizeof (struct net_device_stats), 1); |
| 300 | if (!port_private->stats) { |
| 301 | printf ("%s: %s allocation failure, %s\n", |
| 302 | __FUNCTION__, dev->name, |
| 303 | "Net stat Structure"); |
| 304 | |
| 305 | free (port_private); |
| 306 | free (ethernet_private); |
| 307 | free (dev); |
| 308 | return; |
| 309 | } |
| 310 | memset (ethernet_private->port_private, 0, |
| 311 | sizeof (struct mv64360_eth_priv)); |
| 312 | switch (devnum) { |
| 313 | case 0: |
| 314 | ethernet_private->port_num = ETH_0; |
| 315 | break; |
| 316 | case 1: |
| 317 | ethernet_private->port_num = ETH_1; |
| 318 | break; |
| 319 | case 2: |
| 320 | ethernet_private->port_num = ETH_2; |
| 321 | break; |
| 322 | default: |
| 323 | printf ("Invalid device number %d\n", devnum); |
| 324 | break; |
| 325 | }; |
| 326 | |
| 327 | port_private->port_num = devnum; |
| 328 | /* |
| 329 | * Read MIB counter on the GT in order to reset them, |
| 330 | * then zero all the stats fields in memory |
| 331 | */ |
| 332 | mv64360_eth_update_stat (dev); |
| 333 | memset (port_private->stats, 0, |
| 334 | sizeof (struct net_device_stats)); |
| 335 | /* Extract the MAC address from the environment */ |
| 336 | switch (devnum) { |
| 337 | case 0: |
| 338 | s = "ethaddr"; |
| 339 | break; |
| 340 | |
| 341 | case 1: |
| 342 | s = "eth1addr"; |
| 343 | break; |
| 344 | |
| 345 | case 2: |
| 346 | s = "eth2addr"; |
| 347 | break; |
| 348 | |
| 349 | default: /* this should never happen */ |
| 350 | printf ("%s: Invalid device number %d\n", |
| 351 | __FUNCTION__, devnum); |
| 352 | return; |
| 353 | } |
| 354 | |
| 355 | temp = getenv_r (s, buf, sizeof (buf)); |
| 356 | s = (temp > 0) ? buf : NULL; |
| 357 | |
| 358 | #ifdef DEBUG |
| 359 | printf ("Setting MAC %d to %s\n", devnum, s); |
| 360 | #endif |
| 361 | for (x = 0; x < 6; ++x) { |
| 362 | dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0; |
| 363 | if (s) |
| 364 | s = (*e) ? e + 1 : e; |
| 365 | } |
| 366 | |
| 367 | DP (printf ("Allocating descriptor and buffer rings\n")); |
| 368 | |
| 369 | ethernet_private->p_rx_desc_area_base[0] = |
| 370 | (ETH_RX_DESC *) memalign (16, |
| 371 | RX_DESC_ALIGNED_SIZE * |
| 372 | MV64360_RX_QUEUE_SIZE + 1); |
| 373 | ethernet_private->p_tx_desc_area_base[0] = |
| 374 | (ETH_TX_DESC *) memalign (16, |
| 375 | TX_DESC_ALIGNED_SIZE * |
| 376 | MV64360_TX_QUEUE_SIZE + 1); |
| 377 | |
| 378 | ethernet_private->p_rx_buffer_base[0] = |
| 379 | (char *) memalign (16, |
| 380 | MV64360_RX_QUEUE_SIZE * |
| 381 | MV64360_TX_BUFFER_SIZE + 1); |
| 382 | ethernet_private->p_tx_buffer_base[0] = |
| 383 | (char *) memalign (16, |
| 384 | MV64360_RX_QUEUE_SIZE * |
| 385 | MV64360_TX_BUFFER_SIZE + 1); |
| 386 | |
| 387 | #ifdef DEBUG_MV_ETH |
| 388 | /* DEBUG OUTPUT prints adresses of globals */ |
| 389 | print_globals (dev); |
| 390 | #endif |
| 391 | eth_register (dev); |
| 392 | |
| 393 | } |
| 394 | DP (printf ("%s: exit\n", __FUNCTION__)); |
| 395 | |
| 396 | } |
| 397 | |
| 398 | /********************************************************************** |
| 399 | * mv64360_eth_open |
| 400 | * |
| 401 | * This function is called when openning the network device. The function |
| 402 | * should initialize all the hardware, initialize cyclic Rx/Tx |
| 403 | * descriptors chain and buffers and allocate an IRQ to the network |
| 404 | * device. |
| 405 | * |
| 406 | * Input : a pointer to the network device structure |
| 407 | * / / ronen - changed the output to match net/eth.c needs |
| 408 | * Output : nonzero of success , zero if fails. |
| 409 | * under construction |
| 410 | **********************************************************************/ |
| 411 | |
| 412 | int mv64360_eth_open (struct eth_device *dev) |
| 413 | { |
| 414 | return (mv64360_eth_real_open (dev)); |
| 415 | } |
| 416 | |
| 417 | /* Helper function for mv64360_eth_open */ |
| 418 | static int mv64360_eth_real_open (struct eth_device *dev) |
| 419 | { |
| 420 | |
| 421 | unsigned int queue; |
| 422 | ETH_PORT_INFO *ethernet_private; |
| 423 | struct mv64360_eth_priv *port_private; |
| 424 | unsigned int port_num; |
| 425 | u32 port_status, phy_reg_data; |
| 426 | |
| 427 | ethernet_private = (ETH_PORT_INFO *) dev->priv; |
| 428 | /* ronen - when we update the MAC env params we only update dev->enetaddr |
| 429 | see ./net/eth.c eth_set_enetaddr() */ |
| 430 | memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6); |
| 431 | |
| 432 | port_private = |
| 433 | (struct mv64360_eth_priv *) ethernet_private->port_private; |
| 434 | port_num = port_private->port_num; |
| 435 | |
| 436 | /* Stop RX Queues */ |
| 437 | MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num), |
| 438 | 0x0000ff00); |
| 439 | |
| 440 | /* Clear the ethernet port interrupts */ |
| 441 | MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0); |
| 442 | MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0); |
| 443 | |
| 444 | /* Unmask RX buffer and TX end interrupt */ |
| 445 | MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num), |
| 446 | INT_CAUSE_UNMASK_ALL); |
| 447 | |
| 448 | /* Unmask phy and link status changes interrupts */ |
| 449 | MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), |
| 450 | INT_CAUSE_UNMASK_ALL_EXT); |
| 451 | |
| 452 | /* Set phy address of the port */ |
| 453 | ethernet_private->port_phy_addr = 0x8 + port_num; |
| 454 | |
| 455 | /* Activate the DMA channels etc */ |
| 456 | eth_port_init (ethernet_private); |
| 457 | |
| 458 | |
| 459 | /* "Allocate" setup TX rings */ |
| 460 | |
| 461 | for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) { |
| 462 | unsigned int size; |
| 463 | |
| 464 | port_private->tx_ring_size[queue] = MV64360_TX_QUEUE_SIZE; |
| 465 | size = (port_private->tx_ring_size[queue] * TX_DESC_ALIGNED_SIZE); /*size = no of DESCs times DESC-size */ |
| 466 | ethernet_private->tx_desc_area_size[queue] = size; |
| 467 | |
| 468 | /* first clear desc area completely */ |
| 469 | memset ((void *) ethernet_private->p_tx_desc_area_base[queue], |
| 470 | 0, ethernet_private->tx_desc_area_size[queue]); |
| 471 | |
| 472 | /* initialize tx desc ring with low level driver */ |
| 473 | if (ether_init_tx_desc_ring |
| 474 | (ethernet_private, ETH_Q0, |
| 475 | port_private->tx_ring_size[queue], |
| 476 | MV64360_TX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ , |
| 477 | (unsigned int) ethernet_private-> |
| 478 | p_tx_desc_area_base[queue], |
| 479 | (unsigned int) ethernet_private-> |
| 480 | p_tx_buffer_base[queue]) == false) |
| 481 | printf ("### Error initializing TX Ring\n"); |
| 482 | } |
| 483 | |
| 484 | /* "Allocate" setup RX rings */ |
| 485 | for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) { |
| 486 | unsigned int size; |
| 487 | |
| 488 | /* Meantime RX Ring are fixed - but must be configurable by user */ |
| 489 | port_private->rx_ring_size[queue] = MV64360_RX_QUEUE_SIZE; |
| 490 | size = (port_private->rx_ring_size[queue] * |
| 491 | RX_DESC_ALIGNED_SIZE); |
| 492 | ethernet_private->rx_desc_area_size[queue] = size; |
| 493 | |
| 494 | /* first clear desc area completely */ |
| 495 | memset ((void *) ethernet_private->p_rx_desc_area_base[queue], |
| 496 | 0, ethernet_private->rx_desc_area_size[queue]); |
| 497 | if ((ether_init_rx_desc_ring |
| 498 | (ethernet_private, ETH_Q0, |
| 499 | port_private->rx_ring_size[queue], |
| 500 | MV64360_RX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ , |
| 501 | (unsigned int) ethernet_private-> |
| 502 | p_rx_desc_area_base[queue], |
| 503 | (unsigned int) ethernet_private-> |
| 504 | p_rx_buffer_base[queue])) == false) |
| 505 | printf ("### Error initializing RX Ring\n"); |
| 506 | } |
| 507 | |
| 508 | eth_port_start (ethernet_private); |
| 509 | |
| 510 | /* Set maximum receive buffer to 9700 bytes */ |
| 511 | MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num), |
| 512 | (0x5 << 17) | |
| 513 | (MV_REG_READ |
| 514 | (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num)) |
| 515 | & 0xfff1ffff)); |
| 516 | |
| 517 | /* |
| 518 | * Set ethernet MTU for leaky bucket mechanism to 0 - this will |
| 519 | * disable the leaky bucket mechanism . |
| 520 | */ |
| 521 | |
| 522 | MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0); |
| 523 | port_status = MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num)); |
| 524 | |
| 525 | /* Check Link status on phy */ |
| 526 | eth_port_read_smi_reg (port_num, 1, &phy_reg_data); |
| 527 | if (!(phy_reg_data & 0x20)) { |
| 528 | /* Reset PHY */ |
| 529 | if ((ethernet_phy_reset (port_num)) != true) { |
| 530 | printf ("$$ Warnning: No link on port %d \n", |
| 531 | port_num); |
| 532 | return 0; |
| 533 | } else { |
| 534 | eth_port_read_smi_reg (port_num, 1, &phy_reg_data); |
| 535 | if (!(phy_reg_data & 0x20)) { |
| 536 | printf ("### Error: Phy is not active\n"); |
| 537 | return 0; |
| 538 | } |
| 539 | } |
| 540 | } else { |
| 541 | mv64360_eth_print_phy_status (dev); |
| 542 | } |
| 543 | port_private->eth_running = MAGIC_ETH_RUNNING; |
| 544 | return 1; |
| 545 | } |
| 546 | |
| 547 | |
| 548 | static int mv64360_eth_free_tx_rings (struct eth_device *dev) |
| 549 | { |
| 550 | unsigned int queue; |
| 551 | ETH_PORT_INFO *ethernet_private; |
| 552 | struct mv64360_eth_priv *port_private; |
| 553 | unsigned int port_num; |
| 554 | volatile ETH_TX_DESC *p_tx_curr_desc; |
| 555 | |
| 556 | ethernet_private = (ETH_PORT_INFO *) dev->priv; |
| 557 | port_private = |
| 558 | (struct mv64360_eth_priv *) ethernet_private->port_private; |
| 559 | port_num = port_private->port_num; |
| 560 | |
| 561 | /* Stop Tx Queues */ |
| 562 | MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG (port_num), |
| 563 | 0x0000ff00); |
| 564 | |
| 565 | /* Free TX rings */ |
| 566 | DP (printf ("Clearing previously allocated TX queues... ")); |
| 567 | for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) { |
| 568 | /* Free on TX rings */ |
| 569 | for (p_tx_curr_desc = |
| 570 | ethernet_private->p_tx_desc_area_base[queue]; |
| 571 | ((unsigned int) p_tx_curr_desc <= (unsigned int) |
| 572 | ethernet_private->p_tx_desc_area_base[queue] + |
| 573 | ethernet_private->tx_desc_area_size[queue]); |
| 574 | p_tx_curr_desc = |
| 575 | (ETH_TX_DESC *) ((unsigned int) p_tx_curr_desc + |
| 576 | TX_DESC_ALIGNED_SIZE)) { |
| 577 | /* this is inside for loop */ |
| 578 | if (p_tx_curr_desc->return_info != 0) { |
| 579 | p_tx_curr_desc->return_info = 0; |
| 580 | DP (printf ("freed\n")); |
| 581 | } |
| 582 | } |
| 583 | DP (printf ("Done\n")); |
| 584 | } |
| 585 | return 0; |
| 586 | } |
| 587 | |
| 588 | static int mv64360_eth_free_rx_rings (struct eth_device *dev) |
| 589 | { |
| 590 | unsigned int queue; |
| 591 | ETH_PORT_INFO *ethernet_private; |
| 592 | struct mv64360_eth_priv *port_private; |
| 593 | unsigned int port_num; |
| 594 | volatile ETH_RX_DESC *p_rx_curr_desc; |
| 595 | |
| 596 | ethernet_private = (ETH_PORT_INFO *) dev->priv; |
| 597 | port_private = |
| 598 | (struct mv64360_eth_priv *) ethernet_private->port_private; |
| 599 | port_num = port_private->port_num; |
| 600 | |
| 601 | |
| 602 | /* Stop RX Queues */ |
| 603 | MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num), |
| 604 | 0x0000ff00); |
| 605 | |
| 606 | /* Free RX rings */ |
| 607 | DP (printf ("Clearing previously allocated RX queues... ")); |
| 608 | for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) { |
| 609 | /* Free preallocated skb's on RX rings */ |
| 610 | for (p_rx_curr_desc = |
| 611 | ethernet_private->p_rx_desc_area_base[queue]; |
| 612 | (((unsigned int) p_rx_curr_desc < |
| 613 | ((unsigned int) ethernet_private-> |
| 614 | p_rx_desc_area_base[queue] + |
| 615 | ethernet_private->rx_desc_area_size[queue]))); |
| 616 | p_rx_curr_desc = |
| 617 | (ETH_RX_DESC *) ((unsigned int) p_rx_curr_desc + |
| 618 | RX_DESC_ALIGNED_SIZE)) { |
| 619 | if (p_rx_curr_desc->return_info != 0) { |
| 620 | p_rx_curr_desc->return_info = 0; |
| 621 | DP (printf ("freed\n")); |
| 622 | } |
| 623 | } |
| 624 | DP (printf ("Done\n")); |
| 625 | } |
| 626 | return 0; |
| 627 | } |
| 628 | |
| 629 | /********************************************************************** |
| 630 | * mv64360_eth_stop |
| 631 | * |
| 632 | * This function is used when closing the network device. |
| 633 | * It updates the hardware, |
| 634 | * release all memory that holds buffers and descriptors and release the IRQ. |
| 635 | * Input : a pointer to the device structure |
| 636 | * Output : zero if success , nonzero if fails |
| 637 | *********************************************************************/ |
| 638 | |
| 639 | int mv64360_eth_stop (struct eth_device *dev) |
| 640 | { |
| 641 | ETH_PORT_INFO *ethernet_private; |
| 642 | struct mv64360_eth_priv *port_private; |
| 643 | unsigned int port_num; |
| 644 | |
| 645 | ethernet_private = (ETH_PORT_INFO *) dev->priv; |
| 646 | port_private = |
| 647 | (struct mv64360_eth_priv *) ethernet_private->port_private; |
| 648 | port_num = port_private->port_num; |
| 649 | |
| 650 | /* Disable all gigE address decoder */ |
| 651 | MV_REG_WRITE (MV64360_ETH_BASE_ADDR_ENABLE_REG, 0x3f); |
| 652 | DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__)); |
| 653 | mv64360_eth_real_stop (dev); |
| 654 | |
| 655 | return 0; |
| 656 | }; |
| 657 | |
| 658 | /* Helper function for mv64360_eth_stop */ |
| 659 | |
| 660 | static int mv64360_eth_real_stop (struct eth_device *dev) |
| 661 | { |
| 662 | ETH_PORT_INFO *ethernet_private; |
| 663 | struct mv64360_eth_priv *port_private; |
| 664 | unsigned int port_num; |
| 665 | |
| 666 | ethernet_private = (ETH_PORT_INFO *) dev->priv; |
| 667 | port_private = |
| 668 | (struct mv64360_eth_priv *) ethernet_private->port_private; |
| 669 | port_num = port_private->port_num; |
| 670 | |
| 671 | |
| 672 | mv64360_eth_free_tx_rings (dev); |
| 673 | mv64360_eth_free_rx_rings (dev); |
| 674 | |
| 675 | eth_port_reset (ethernet_private->port_num); |
| 676 | /* Disable ethernet port interrupts */ |
| 677 | MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0); |
| 678 | MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0); |
| 679 | /* Mask RX buffer and TX end interrupt */ |
| 680 | MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num), 0); |
| 681 | /* Mask phy and link status changes interrupts */ |
| 682 | MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), 0); |
| 683 | MV_RESET_REG_BITS (MV64360_CPU_INTERRUPT0_MASK_HIGH, |
| 684 | BIT0 << port_num); |
| 685 | /* Print Network statistics */ |
| 686 | #ifndef UPDATE_STATS_BY_SOFTWARE |
| 687 | /* |
| 688 | * Print statistics (only if ethernet is running), |
| 689 | * then zero all the stats fields in memory |
| 690 | */ |
| 691 | if (port_private->eth_running == MAGIC_ETH_RUNNING) { |
| 692 | port_private->eth_running = 0; |
| 693 | mv64360_eth_print_stat (dev); |
| 694 | } |
| 695 | memset (port_private->stats, 0, sizeof (struct net_device_stats)); |
| 696 | #endif |
| 697 | DP (printf ("\nEthernet stopped ... \n")); |
| 698 | return 0; |
| 699 | } |
| 700 | |
| 701 | |
| 702 | /********************************************************************** |
| 703 | * mv64360_eth_start_xmit |
| 704 | * |
| 705 | * This function is queues a packet in the Tx descriptor for |
| 706 | * required port. |
| 707 | * |
| 708 | * Input : skb - a pointer to socket buffer |
| 709 | * dev - a pointer to the required port |
| 710 | * |
| 711 | * Output : zero upon success |
| 712 | **********************************************************************/ |
| 713 | |
| 714 | int mv64360_eth_xmit (struct eth_device *dev, volatile void *dataPtr, |
| 715 | int dataSize) |
| 716 | { |
| 717 | ETH_PORT_INFO *ethernet_private; |
| 718 | struct mv64360_eth_priv *port_private; |
| 719 | unsigned int port_num; |
| 720 | PKT_INFO pkt_info; |
| 721 | ETH_FUNC_RET_STATUS status; |
| 722 | struct net_device_stats *stats; |
| 723 | ETH_FUNC_RET_STATUS release_result; |
| 724 | |
| 725 | ethernet_private = (ETH_PORT_INFO *) dev->priv; |
| 726 | port_private = |
| 727 | (struct mv64360_eth_priv *) ethernet_private->port_private; |
| 728 | port_num = port_private->port_num; |
| 729 | |
| 730 | stats = port_private->stats; |
| 731 | |
| 732 | /* Update packet info data structure */ |
| 733 | pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC; /* DMA owned, first last */ |
| 734 | pkt_info.byte_cnt = dataSize; |
| 735 | pkt_info.buf_ptr = (unsigned int) dataPtr; |
Wolfgang Denk | d87080b | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 736 | pkt_info.return_info = 0; |
stroese | 771e05b | 2004-12-16 18:21:17 +0000 | [diff] [blame] | 737 | |
| 738 | status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info); |
| 739 | if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) { |
| 740 | printf ("Error on transmitting packet .."); |
| 741 | if (status == ETH_QUEUE_FULL) |
| 742 | printf ("ETH Queue is full. \n"); |
| 743 | if (status == ETH_QUEUE_LAST_RESOURCE) |
| 744 | printf ("ETH Queue: using last available resource. \n"); |
| 745 | goto error; |
| 746 | } |
| 747 | |
| 748 | /* Update statistics and start of transmittion time */ |
| 749 | stats->tx_bytes += dataSize; |
| 750 | stats->tx_packets++; |
| 751 | |
| 752 | /* Check if packet(s) is(are) transmitted correctly (release everything) */ |
| 753 | do { |
| 754 | release_result = |
| 755 | eth_tx_return_desc (ethernet_private, ETH_Q0, |
| 756 | &pkt_info); |
| 757 | switch (release_result) { |
| 758 | case ETH_OK: |
| 759 | DP (printf ("descriptor released\n")); |
| 760 | if (pkt_info.cmd_sts & BIT0) { |
| 761 | printf ("Error in TX\n"); |
| 762 | stats->tx_errors++; |
| 763 | |
| 764 | } |
| 765 | break; |
| 766 | case ETH_RETRY: |
| 767 | DP (printf ("transmission still in process\n")); |
| 768 | break; |
| 769 | |
| 770 | case ETH_ERROR: |
| 771 | printf ("routine can not access Tx desc ring\n"); |
| 772 | break; |
| 773 | |
| 774 | case ETH_END_OF_JOB: |
| 775 | DP (printf ("the routine has nothing to release\n")); |
| 776 | break; |
| 777 | default: /* should not happen */ |
| 778 | break; |
| 779 | } |
| 780 | } while (release_result == ETH_OK); |
| 781 | |
| 782 | |
| 783 | return 0; /* success */ |
| 784 | error: |
| 785 | return 1; /* Failed - higher layers will free the skb */ |
| 786 | } |
| 787 | |
| 788 | /********************************************************************** |
| 789 | * mv64360_eth_receive |
| 790 | * |
| 791 | * This function is forward packets that are received from the port's |
| 792 | * queues toward kernel core or FastRoute them to another interface. |
| 793 | * |
| 794 | * Input : dev - a pointer to the required interface |
| 795 | * max - maximum number to receive (0 means unlimted) |
| 796 | * |
| 797 | * Output : number of served packets |
| 798 | **********************************************************************/ |
| 799 | |
| 800 | int mv64360_eth_receive (struct eth_device *dev) |
| 801 | { |
| 802 | ETH_PORT_INFO *ethernet_private; |
| 803 | struct mv64360_eth_priv *port_private; |
| 804 | unsigned int port_num; |
| 805 | PKT_INFO pkt_info; |
| 806 | struct net_device_stats *stats; |
| 807 | |
| 808 | |
| 809 | ethernet_private = (ETH_PORT_INFO *) dev->priv; |
| 810 | port_private = |
| 811 | (struct mv64360_eth_priv *) ethernet_private->port_private; |
| 812 | port_num = port_private->port_num; |
| 813 | stats = port_private->stats; |
| 814 | |
| 815 | while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) == |
| 816 | ETH_OK)) { |
| 817 | |
| 818 | #ifdef DEBUG_MV_ETH |
| 819 | if (pkt_info.byte_cnt != 0) { |
| 820 | printf ("%s: Received %d byte Packet @ 0x%x\n", |
| 821 | __FUNCTION__, pkt_info.byte_cnt, |
| 822 | pkt_info.buf_ptr); |
| 823 | } |
| 824 | #endif |
| 825 | /* Update statistics. Note byte count includes 4 byte CRC count */ |
| 826 | stats->rx_packets++; |
| 827 | stats->rx_bytes += pkt_info.byte_cnt; |
| 828 | |
| 829 | /* |
| 830 | * In case received a packet without first / last bits on OR the error |
| 831 | * summary bit is on, the packets needs to be dropeed. |
| 832 | */ |
| 833 | if (((pkt_info. |
| 834 | cmd_sts & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) != |
| 835 | (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) |
| 836 | || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) { |
| 837 | stats->rx_dropped++; |
| 838 | |
| 839 | printf ("Received packet spread on multiple descriptors\n"); |
| 840 | |
| 841 | /* Is this caused by an error ? */ |
| 842 | if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) { |
| 843 | stats->rx_errors++; |
| 844 | } |
| 845 | |
| 846 | /* free these descriptors again without forwarding them to the higher layers */ |
| 847 | pkt_info.buf_ptr &= ~0x7; /* realign buffer again */ |
| 848 | pkt_info.byte_cnt = 0x0000; /* Reset Byte count */ |
| 849 | |
| 850 | if (eth_rx_return_buff |
| 851 | (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) { |
| 852 | printf ("Error while returning the RX Desc to Ring\n"); |
| 853 | } else { |
| 854 | DP (printf ("RX Desc returned to Ring\n")); |
| 855 | } |
| 856 | /* /free these descriptors again */ |
| 857 | } else { |
| 858 | |
| 859 | /* !!! call higher layer processing */ |
| 860 | #ifdef DEBUG_MV_ETH |
| 861 | printf ("\nNow send it to upper layer protocols (NetReceive) ...\n"); |
| 862 | #endif |
| 863 | /* let the upper layer handle the packet */ |
| 864 | NetReceive ((uchar *) pkt_info.buf_ptr, |
| 865 | (int) pkt_info.byte_cnt); |
| 866 | |
| 867 | /* **************************************************************** */ |
| 868 | /* free descriptor */ |
| 869 | pkt_info.buf_ptr &= ~0x7; /* realign buffer again */ |
| 870 | pkt_info.byte_cnt = 0x0000; /* Reset Byte count */ |
| 871 | DP (printf |
| 872 | ("RX: pkt_info.buf_ptr = %x\n", |
| 873 | pkt_info.buf_ptr)); |
| 874 | if (eth_rx_return_buff |
| 875 | (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) { |
| 876 | printf ("Error while returning the RX Desc to Ring\n"); |
| 877 | } else { |
| 878 | DP (printf ("RX Desc returned to Ring\n")); |
| 879 | } |
| 880 | |
| 881 | /* **************************************************************** */ |
| 882 | |
| 883 | } |
| 884 | } |
| 885 | mv64360_eth_get_stats (dev); /* update statistics */ |
| 886 | return 1; |
| 887 | } |
| 888 | |
| 889 | /********************************************************************** |
| 890 | * mv64360_eth_get_stats |
| 891 | * |
| 892 | * Returns a pointer to the interface statistics. |
| 893 | * |
| 894 | * Input : dev - a pointer to the required interface |
| 895 | * |
| 896 | * Output : a pointer to the interface's statistics |
| 897 | **********************************************************************/ |
| 898 | |
| 899 | static struct net_device_stats *mv64360_eth_get_stats (struct eth_device *dev) |
| 900 | { |
| 901 | ETH_PORT_INFO *ethernet_private; |
| 902 | struct mv64360_eth_priv *port_private; |
| 903 | unsigned int port_num; |
| 904 | |
| 905 | ethernet_private = (ETH_PORT_INFO *) dev->priv; |
| 906 | port_private = |
| 907 | (struct mv64360_eth_priv *) ethernet_private->port_private; |
| 908 | port_num = port_private->port_num; |
| 909 | |
| 910 | mv64360_eth_update_stat (dev); |
| 911 | |
| 912 | return port_private->stats; |
| 913 | } |
| 914 | |
| 915 | |
| 916 | /********************************************************************** |
| 917 | * mv64360_eth_update_stat |
| 918 | * |
| 919 | * Update the statistics structure in the private data structure |
| 920 | * |
| 921 | * Input : pointer to ethernet interface network device structure |
| 922 | * Output : N/A |
| 923 | **********************************************************************/ |
| 924 | |
| 925 | static void mv64360_eth_update_stat (struct eth_device *dev) |
| 926 | { |
| 927 | ETH_PORT_INFO *ethernet_private; |
| 928 | struct mv64360_eth_priv *port_private; |
| 929 | struct net_device_stats *stats; |
| 930 | unsigned int port_num; |
| 931 | volatile unsigned int dummy; |
| 932 | |
| 933 | ethernet_private = (ETH_PORT_INFO *) dev->priv; |
| 934 | port_private = |
| 935 | (struct mv64360_eth_priv *) ethernet_private->port_private; |
| 936 | port_num = port_private->port_num; |
| 937 | stats = port_private->stats; |
| 938 | |
| 939 | /* These are false updates */ |
| 940 | stats->rx_packets += (unsigned long) |
| 941 | eth_read_mib_counter (ethernet_private->port_num, |
| 942 | ETH_MIB_GOOD_FRAMES_RECEIVED); |
| 943 | stats->tx_packets += (unsigned long) |
| 944 | eth_read_mib_counter (ethernet_private->port_num, |
| 945 | ETH_MIB_GOOD_FRAMES_SENT); |
| 946 | stats->rx_bytes += (unsigned long) |
| 947 | eth_read_mib_counter (ethernet_private->port_num, |
| 948 | ETH_MIB_GOOD_OCTETS_RECEIVED_LOW); |
| 949 | /* |
| 950 | * Ideally this should be as follows - |
| 951 | * |
| 952 | * stats->rx_bytes += stats->rx_bytes + |
| 953 | * ((unsigned long) ethReadMibCounter (ethernet_private->port_num , |
| 954 | * ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32); |
| 955 | * |
| 956 | * But the unsigned long in PowerPC and MIPS are 32bit. So the next read |
| 957 | * is just a dummy read for proper work of the GigE port |
| 958 | */ |
| 959 | dummy = eth_read_mib_counter (ethernet_private->port_num, |
| 960 | ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH); |
| 961 | stats->tx_bytes += (unsigned long) |
| 962 | eth_read_mib_counter (ethernet_private->port_num, |
| 963 | ETH_MIB_GOOD_OCTETS_SENT_LOW); |
| 964 | dummy = eth_read_mib_counter (ethernet_private->port_num, |
| 965 | ETH_MIB_GOOD_OCTETS_SENT_HIGH); |
| 966 | stats->rx_errors += (unsigned long) |
| 967 | eth_read_mib_counter (ethernet_private->port_num, |
| 968 | ETH_MIB_MAC_RECEIVE_ERROR); |
| 969 | |
| 970 | /* Rx dropped is for received packet with CRC error */ |
| 971 | stats->rx_dropped += |
| 972 | (unsigned long) eth_read_mib_counter (ethernet_private-> |
| 973 | port_num, |
| 974 | ETH_MIB_BAD_CRC_EVENT); |
| 975 | stats->multicast += (unsigned long) |
| 976 | eth_read_mib_counter (ethernet_private->port_num, |
| 977 | ETH_MIB_MULTICAST_FRAMES_RECEIVED); |
| 978 | stats->collisions += |
| 979 | (unsigned long) eth_read_mib_counter (ethernet_private-> |
| 980 | port_num, |
| 981 | ETH_MIB_COLLISION) + |
| 982 | (unsigned long) eth_read_mib_counter (ethernet_private-> |
| 983 | port_num, |
| 984 | ETH_MIB_LATE_COLLISION); |
| 985 | /* detailed rx errors */ |
| 986 | stats->rx_length_errors += |
| 987 | (unsigned long) eth_read_mib_counter (ethernet_private-> |
| 988 | port_num, |
| 989 | ETH_MIB_UNDERSIZE_RECEIVED) |
| 990 | + |
| 991 | (unsigned long) eth_read_mib_counter (ethernet_private-> |
| 992 | port_num, |
| 993 | ETH_MIB_OVERSIZE_RECEIVED); |
| 994 | /* detailed tx errors */ |
| 995 | } |
| 996 | |
| 997 | #ifndef UPDATE_STATS_BY_SOFTWARE |
| 998 | /********************************************************************** |
| 999 | * mv64360_eth_print_stat |
| 1000 | * |
| 1001 | * Update the statistics structure in the private data structure |
| 1002 | * |
| 1003 | * Input : pointer to ethernet interface network device structure |
| 1004 | * Output : N/A |
| 1005 | **********************************************************************/ |
| 1006 | |
| 1007 | static void mv64360_eth_print_stat (struct eth_device *dev) |
| 1008 | { |
| 1009 | ETH_PORT_INFO *ethernet_private; |
| 1010 | struct mv64360_eth_priv *port_private; |
| 1011 | struct net_device_stats *stats; |
| 1012 | unsigned int port_num; |
| 1013 | |
| 1014 | ethernet_private = (ETH_PORT_INFO *) dev->priv; |
| 1015 | port_private = |
| 1016 | (struct mv64360_eth_priv *) ethernet_private->port_private; |
| 1017 | port_num = port_private->port_num; |
| 1018 | stats = port_private->stats; |
| 1019 | |
| 1020 | /* These are false updates */ |
| 1021 | printf ("\n### Network statistics: ###\n"); |
| 1022 | printf ("--------------------------\n"); |
| 1023 | printf (" Packets received: %ld\n", stats->rx_packets); |
| 1024 | printf (" Packets send: %ld\n", stats->tx_packets); |
| 1025 | printf (" Received bytes: %ld\n", stats->rx_bytes); |
| 1026 | printf (" Send bytes: %ld\n", stats->tx_bytes); |
| 1027 | if (stats->rx_errors != 0) |
| 1028 | printf (" Rx Errors: %ld\n", |
| 1029 | stats->rx_errors); |
| 1030 | if (stats->rx_dropped != 0) |
| 1031 | printf (" Rx dropped (CRC Errors): %ld\n", |
| 1032 | stats->rx_dropped); |
| 1033 | if (stats->multicast != 0) |
| 1034 | printf (" Rx mulicast frames: %ld\n", |
| 1035 | stats->multicast); |
| 1036 | if (stats->collisions != 0) |
| 1037 | printf (" No. of collisions: %ld\n", |
| 1038 | stats->collisions); |
| 1039 | if (stats->rx_length_errors != 0) |
| 1040 | printf (" Rx length errors: %ld\n", |
| 1041 | stats->rx_length_errors); |
| 1042 | } |
| 1043 | #endif |
| 1044 | |
| 1045 | /************************************************************************** |
| 1046 | *network_start - Network Kick Off Routine UBoot |
| 1047 | *Inputs : |
| 1048 | *Outputs : |
| 1049 | **************************************************************************/ |
| 1050 | |
| 1051 | bool db64360_eth_start (struct eth_device *dev) |
| 1052 | { |
| 1053 | return (mv64360_eth_open (dev)); /* calls real open */ |
| 1054 | } |
| 1055 | |
| 1056 | /************************************************************************* |
| 1057 | ************************************************************************** |
| 1058 | ************************************************************************** |
| 1059 | * The second part is the low level driver of the gigE ethernet ports. * |
| 1060 | ************************************************************************** |
| 1061 | ************************************************************************** |
| 1062 | *************************************************************************/ |
| 1063 | /* |
| 1064 | * based on Linux code |
| 1065 | * arch/ppc/galileo/EVB64360/mv64360_eth.c - Driver for MV64360X ethernet ports |
| 1066 | * Copyright (C) 2002 rabeeh@galileo.co.il |
| 1067 | |
| 1068 | * This program is free software; you can redistribute it and/or |
| 1069 | * modify it under the terms of the GNU General Public License |
| 1070 | * as published by the Free Software Foundation; either version 2 |
| 1071 | * of the License, or (at your option) any later version. |
| 1072 | |
| 1073 | * This program is distributed in the hope that it will be useful, |
| 1074 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 1075 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 1076 | * GNU General Public License for more details. |
| 1077 | |
| 1078 | * You should have received a copy of the GNU General Public License |
| 1079 | * along with this program; if not, write to the Free Software |
| 1080 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| 1081 | * |
| 1082 | */ |
| 1083 | |
| 1084 | /******************************************************************************** |
| 1085 | * Marvell's Gigabit Ethernet controller low level driver |
| 1086 | * |
| 1087 | * DESCRIPTION: |
| 1088 | * This file introduce low level API to Marvell's Gigabit Ethernet |
| 1089 | * controller. This Gigabit Ethernet Controller driver API controls |
| 1090 | * 1) Operations (i.e. port init, start, reset etc'). |
| 1091 | * 2) Data flow (i.e. port send, receive etc'). |
| 1092 | * Each Gigabit Ethernet port is controlled via ETH_PORT_INFO |
| 1093 | * struct. |
| 1094 | * This struct includes user configuration information as well as |
| 1095 | * driver internal data needed for its operations. |
| 1096 | * |
| 1097 | * Supported Features: |
| 1098 | * - This low level driver is OS independent. Allocating memory for |
| 1099 | * the descriptor rings and buffers are not within the scope of |
| 1100 | * this driver. |
| 1101 | * - The user is free from Rx/Tx queue managing. |
| 1102 | * - This low level driver introduce functionality API that enable |
| 1103 | * the to operate Marvell's Gigabit Ethernet Controller in a |
| 1104 | * convenient way. |
| 1105 | * - Simple Gigabit Ethernet port operation API. |
| 1106 | * - Simple Gigabit Ethernet port data flow API. |
| 1107 | * - Data flow and operation API support per queue functionality. |
| 1108 | * - Support cached descriptors for better performance. |
| 1109 | * - Enable access to all four DRAM banks and internal SRAM memory |
| 1110 | * spaces. |
| 1111 | * - PHY access and control API. |
| 1112 | * - Port control register configuration API. |
| 1113 | * - Full control over Unicast and Multicast MAC configurations. |
| 1114 | * |
| 1115 | * Operation flow: |
| 1116 | * |
| 1117 | * Initialization phase |
| 1118 | * This phase complete the initialization of the ETH_PORT_INFO |
| 1119 | * struct. |
| 1120 | * User information regarding port configuration has to be set |
| 1121 | * prior to calling the port initialization routine. For example, |
| 1122 | * the user has to assign the port_phy_addr field which is board |
| 1123 | * depended parameter. |
| 1124 | * In this phase any port Tx/Rx activity is halted, MIB counters |
| 1125 | * are cleared, PHY address is set according to user parameter and |
| 1126 | * access to DRAM and internal SRAM memory spaces. |
| 1127 | * |
| 1128 | * Driver ring initialization |
| 1129 | * Allocating memory for the descriptor rings and buffers is not |
| 1130 | * within the scope of this driver. Thus, the user is required to |
| 1131 | * allocate memory for the descriptors ring and buffers. Those |
| 1132 | * memory parameters are used by the Rx and Tx ring initialization |
| 1133 | * routines in order to curve the descriptor linked list in a form |
| 1134 | * of a ring. |
| 1135 | * Note: Pay special attention to alignment issues when using |
| 1136 | * cached descriptors/buffers. In this phase the driver store |
| 1137 | * information in the ETH_PORT_INFO struct regarding each queue |
| 1138 | * ring. |
| 1139 | * |
| 1140 | * Driver start |
| 1141 | * This phase prepares the Ethernet port for Rx and Tx activity. |
| 1142 | * It uses the information stored in the ETH_PORT_INFO struct to |
| 1143 | * initialize the various port registers. |
| 1144 | * |
| 1145 | * Data flow: |
| 1146 | * All packet references to/from the driver are done using PKT_INFO |
| 1147 | * struct. |
| 1148 | * This struct is a unified struct used with Rx and Tx operations. |
| 1149 | * This way the user is not required to be familiar with neither |
| 1150 | * Tx nor Rx descriptors structures. |
| 1151 | * The driver's descriptors rings are management by indexes. |
| 1152 | * Those indexes controls the ring resources and used to indicate |
| 1153 | * a SW resource error: |
| 1154 | * 'current' |
| 1155 | * This index points to the current available resource for use. For |
| 1156 | * example in Rx process this index will point to the descriptor |
| 1157 | * that will be passed to the user upon calling the receive routine. |
| 1158 | * In Tx process, this index will point to the descriptor |
| 1159 | * that will be assigned with the user packet info and transmitted. |
| 1160 | * 'used' |
| 1161 | * This index points to the descriptor that need to restore its |
| 1162 | * resources. For example in Rx process, using the Rx buffer return |
| 1163 | * API will attach the buffer returned in packet info to the |
| 1164 | * descriptor pointed by 'used'. In Tx process, using the Tx |
| 1165 | * descriptor return will merely return the user packet info with |
| 1166 | * the command status of the transmitted buffer pointed by the |
| 1167 | * 'used' index. Nevertheless, it is essential to use this routine |
| 1168 | * to update the 'used' index. |
| 1169 | * 'first' |
| 1170 | * This index supports Tx Scatter-Gather. It points to the first |
| 1171 | * descriptor of a packet assembled of multiple buffers. For example |
| 1172 | * when in middle of Such packet we have a Tx resource error the |
| 1173 | * 'curr' index get the value of 'first' to indicate that the ring |
| 1174 | * returned to its state before trying to transmit this packet. |
| 1175 | * |
| 1176 | * Receive operation: |
| 1177 | * The eth_port_receive API set the packet information struct, |
| 1178 | * passed by the caller, with received information from the |
| 1179 | * 'current' SDMA descriptor. |
| 1180 | * It is the user responsibility to return this resource back |
| 1181 | * to the Rx descriptor ring to enable the reuse of this source. |
| 1182 | * Return Rx resource is done using the eth_rx_return_buff API. |
| 1183 | * |
| 1184 | * Transmit operation: |
| 1185 | * The eth_port_send API supports Scatter-Gather which enables to |
| 1186 | * send a packet spanned over multiple buffers. This means that |
| 1187 | * for each packet info structure given by the user and put into |
| 1188 | * the Tx descriptors ring, will be transmitted only if the 'LAST' |
| 1189 | * bit will be set in the packet info command status field. This |
| 1190 | * API also consider restriction regarding buffer alignments and |
| 1191 | * sizes. |
| 1192 | * The user must return a Tx resource after ensuring the buffer |
| 1193 | * has been transmitted to enable the Tx ring indexes to update. |
| 1194 | * |
| 1195 | * BOARD LAYOUT |
| 1196 | * This device is on-board. No jumper diagram is necessary. |
| 1197 | * |
| 1198 | * EXTERNAL INTERFACE |
| 1199 | * |
| 1200 | * Prior to calling the initialization routine eth_port_init() the user |
| 1201 | * must set the following fields under ETH_PORT_INFO struct: |
| 1202 | * port_num User Ethernet port number. |
| 1203 | * port_phy_addr User PHY address of Ethernet port. |
| 1204 | * port_mac_addr[6] User defined port MAC address. |
| 1205 | * port_config User port configuration value. |
| 1206 | * port_config_extend User port config extend value. |
| 1207 | * port_sdma_config User port SDMA config value. |
| 1208 | * port_serial_control User port serial control value. |
| 1209 | * *port_virt_to_phys () User function to cast virtual addr to CPU bus addr. |
| 1210 | * *port_private User scratch pad for user specific data structures. |
| 1211 | * |
| 1212 | * This driver introduce a set of default values: |
| 1213 | * PORT_CONFIG_VALUE Default port configuration value |
| 1214 | * PORT_CONFIG_EXTEND_VALUE Default port extend configuration value |
| 1215 | * PORT_SDMA_CONFIG_VALUE Default sdma control value |
| 1216 | * PORT_SERIAL_CONTROL_VALUE Default port serial control value |
| 1217 | * |
| 1218 | * This driver data flow is done using the PKT_INFO struct which is |
| 1219 | * a unified struct for Rx and Tx operations: |
| 1220 | * byte_cnt Tx/Rx descriptor buffer byte count. |
| 1221 | * l4i_chk CPU provided TCP Checksum. For Tx operation only. |
| 1222 | * cmd_sts Tx/Rx descriptor command status. |
| 1223 | * buf_ptr Tx/Rx descriptor buffer pointer. |
| 1224 | * return_info Tx/Rx user resource return information. |
| 1225 | * |
| 1226 | * |
| 1227 | * EXTERNAL SUPPORT REQUIREMENTS |
| 1228 | * |
| 1229 | * This driver requires the following external support: |
| 1230 | * |
| 1231 | * D_CACHE_FLUSH_LINE (address, address offset) |
| 1232 | * |
| 1233 | * This macro applies assembly code to flush and invalidate cache |
| 1234 | * line. |
| 1235 | * address - address base. |
| 1236 | * address offset - address offset |
| 1237 | * |
| 1238 | * |
| 1239 | * CPU_PIPE_FLUSH |
| 1240 | * |
| 1241 | * This macro applies assembly code to flush the CPU pipeline. |
| 1242 | * |
| 1243 | *******************************************************************************/ |
| 1244 | /* includes */ |
| 1245 | |
| 1246 | /* defines */ |
| 1247 | /* SDMA command macros */ |
| 1248 | #define ETH_ENABLE_TX_QUEUE(tx_queue, eth_port) \ |
| 1249 | MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), (1 << tx_queue)) |
| 1250 | |
| 1251 | #define ETH_DISABLE_TX_QUEUE(tx_queue, eth_port) \ |
| 1252 | MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port),\ |
| 1253 | (1 << (8 + tx_queue))) |
| 1254 | |
| 1255 | #define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \ |
| 1256 | MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << rx_queue)) |
| 1257 | |
| 1258 | #define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \ |
| 1259 | MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << (8 + rx_queue))) |
| 1260 | |
| 1261 | #define CURR_RFD_GET(p_curr_desc, queue) \ |
| 1262 | ((p_curr_desc) = p_eth_port_ctrl->p_rx_curr_desc_q[queue]) |
| 1263 | |
| 1264 | #define CURR_RFD_SET(p_curr_desc, queue) \ |
| 1265 | (p_eth_port_ctrl->p_rx_curr_desc_q[queue] = (p_curr_desc)) |
| 1266 | |
| 1267 | #define USED_RFD_GET(p_used_desc, queue) \ |
| 1268 | ((p_used_desc) = p_eth_port_ctrl->p_rx_used_desc_q[queue]) |
| 1269 | |
| 1270 | #define USED_RFD_SET(p_used_desc, queue)\ |
| 1271 | (p_eth_port_ctrl->p_rx_used_desc_q[queue] = (p_used_desc)) |
| 1272 | |
| 1273 | |
| 1274 | #define CURR_TFD_GET(p_curr_desc, queue) \ |
| 1275 | ((p_curr_desc) = p_eth_port_ctrl->p_tx_curr_desc_q[queue]) |
| 1276 | |
| 1277 | #define CURR_TFD_SET(p_curr_desc, queue) \ |
| 1278 | (p_eth_port_ctrl->p_tx_curr_desc_q[queue] = (p_curr_desc)) |
| 1279 | |
| 1280 | #define USED_TFD_GET(p_used_desc, queue) \ |
| 1281 | ((p_used_desc) = p_eth_port_ctrl->p_tx_used_desc_q[queue]) |
| 1282 | |
| 1283 | #define USED_TFD_SET(p_used_desc, queue) \ |
| 1284 | (p_eth_port_ctrl->p_tx_used_desc_q[queue] = (p_used_desc)) |
| 1285 | |
| 1286 | #define FIRST_TFD_GET(p_first_desc, queue) \ |
| 1287 | ((p_first_desc) = p_eth_port_ctrl->p_tx_first_desc_q[queue]) |
| 1288 | |
| 1289 | #define FIRST_TFD_SET(p_first_desc, queue) \ |
| 1290 | (p_eth_port_ctrl->p_tx_first_desc_q[queue] = (p_first_desc)) |
| 1291 | |
| 1292 | |
| 1293 | /* Macros that save access to desc in order to find next desc pointer */ |
| 1294 | #define RX_NEXT_DESC_PTR(p_rx_desc, queue) (ETH_RX_DESC*)(((((unsigned int)p_rx_desc - (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + RX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->rx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) |
| 1295 | |
| 1296 | #define TX_NEXT_DESC_PTR(p_tx_desc, queue) (ETH_TX_DESC*)(((((unsigned int)p_tx_desc - (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + TX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->tx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) |
| 1297 | |
| 1298 | #define LINK_UP_TIMEOUT 100000 |
| 1299 | #define PHY_BUSY_TIMEOUT 10000000 |
| 1300 | |
| 1301 | /* locals */ |
| 1302 | |
| 1303 | /* PHY routines */ |
| 1304 | static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr); |
| 1305 | static int ethernet_phy_get (ETH_PORT eth_port_num); |
| 1306 | |
| 1307 | /* Ethernet Port routines */ |
| 1308 | static void eth_set_access_control (ETH_PORT eth_port_num, |
| 1309 | ETH_WIN_PARAM * param); |
| 1310 | static bool eth_port_uc_addr (ETH_PORT eth_port_num, unsigned char uc_nibble, |
| 1311 | ETH_QUEUE queue, int option); |
| 1312 | #if 0 /* FIXME */ |
| 1313 | static bool eth_port_smc_addr (ETH_PORT eth_port_num, |
| 1314 | unsigned char mc_byte, |
| 1315 | ETH_QUEUE queue, int option); |
| 1316 | static bool eth_port_omc_addr (ETH_PORT eth_port_num, |
| 1317 | unsigned char crc8, |
| 1318 | ETH_QUEUE queue, int option); |
| 1319 | #endif |
| 1320 | |
| 1321 | static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr, |
| 1322 | int byte_count); |
| 1323 | |
| 1324 | void eth_dbg (ETH_PORT_INFO * p_eth_port_ctrl); |
| 1325 | |
| 1326 | |
| 1327 | typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK; |
| 1328 | u32 mv_get_dram_bank_base_addr (MEMORY_BANK bank) |
| 1329 | { |
| 1330 | u32 result = 0; |
| 1331 | u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE); |
| 1332 | |
| 1333 | if (enable & (1 << bank)) |
| 1334 | return 0; |
| 1335 | if (bank == BANK0) |
| 1336 | result = MV_REG_READ (MV64360_CS_0_BASE_ADDR); |
| 1337 | if (bank == BANK1) |
| 1338 | result = MV_REG_READ (MV64360_CS_1_BASE_ADDR); |
| 1339 | if (bank == BANK2) |
| 1340 | result = MV_REG_READ (MV64360_CS_2_BASE_ADDR); |
| 1341 | if (bank == BANK3) |
| 1342 | result = MV_REG_READ (MV64360_CS_3_BASE_ADDR); |
| 1343 | result &= 0x0000ffff; |
| 1344 | result = result << 16; |
| 1345 | return result; |
| 1346 | } |
| 1347 | |
| 1348 | u32 mv_get_dram_bank_size (MEMORY_BANK bank) |
| 1349 | { |
| 1350 | u32 result = 0; |
| 1351 | u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE); |
| 1352 | |
| 1353 | if (enable & (1 << bank)) |
| 1354 | return 0; |
| 1355 | if (bank == BANK0) |
| 1356 | result = MV_REG_READ (MV64360_CS_0_SIZE); |
| 1357 | if (bank == BANK1) |
| 1358 | result = MV_REG_READ (MV64360_CS_1_SIZE); |
| 1359 | if (bank == BANK2) |
| 1360 | result = MV_REG_READ (MV64360_CS_2_SIZE); |
| 1361 | if (bank == BANK3) |
| 1362 | result = MV_REG_READ (MV64360_CS_3_SIZE); |
| 1363 | result += 1; |
| 1364 | result &= 0x0000ffff; |
| 1365 | result = result << 16; |
| 1366 | return result; |
| 1367 | } |
| 1368 | |
| 1369 | u32 mv_get_internal_sram_base (void) |
| 1370 | { |
| 1371 | u32 result; |
| 1372 | |
| 1373 | result = MV_REG_READ (MV64360_INTEGRATED_SRAM_BASE_ADDR); |
| 1374 | result &= 0x0000ffff; |
| 1375 | result = result << 16; |
| 1376 | return result; |
| 1377 | } |
| 1378 | |
| 1379 | /******************************************************************************* |
| 1380 | * eth_port_init - Initialize the Ethernet port driver |
| 1381 | * |
| 1382 | * DESCRIPTION: |
| 1383 | * This function prepares the ethernet port to start its activity: |
| 1384 | * 1) Completes the ethernet port driver struct initialization toward port |
| 1385 | * start routine. |
| 1386 | * 2) Resets the device to a quiescent state in case of warm reboot. |
| 1387 | * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM. |
| 1388 | * 4) Clean MAC tables. The reset status of those tables is unknown. |
| 1389 | * 5) Set PHY address. |
| 1390 | * Note: Call this routine prior to eth_port_start routine and after setting |
| 1391 | * user values in the user fields of Ethernet port control struct (i.e. |
| 1392 | * port_phy_addr). |
| 1393 | * |
| 1394 | * INPUT: |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame^] | 1395 | * ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct |
stroese | 771e05b | 2004-12-16 18:21:17 +0000 | [diff] [blame] | 1396 | * |
| 1397 | * OUTPUT: |
| 1398 | * See description. |
| 1399 | * |
| 1400 | * RETURN: |
| 1401 | * None. |
| 1402 | * |
| 1403 | *******************************************************************************/ |
| 1404 | static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl) |
| 1405 | { |
| 1406 | int queue; |
| 1407 | ETH_WIN_PARAM win_param; |
| 1408 | |
| 1409 | p_eth_port_ctrl->port_config = PORT_CONFIG_VALUE; |
| 1410 | p_eth_port_ctrl->port_config_extend = PORT_CONFIG_EXTEND_VALUE; |
| 1411 | p_eth_port_ctrl->port_sdma_config = PORT_SDMA_CONFIG_VALUE; |
| 1412 | p_eth_port_ctrl->port_serial_control = PORT_SERIAL_CONTROL_VALUE; |
| 1413 | |
| 1414 | p_eth_port_ctrl->port_rx_queue_command = 0; |
| 1415 | p_eth_port_ctrl->port_tx_queue_command = 0; |
| 1416 | |
| 1417 | /* Zero out SW structs */ |
| 1418 | for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) { |
| 1419 | CURR_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue); |
| 1420 | USED_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue); |
| 1421 | p_eth_port_ctrl->rx_resource_err[queue] = false; |
| 1422 | } |
| 1423 | |
| 1424 | for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) { |
| 1425 | CURR_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); |
| 1426 | USED_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); |
| 1427 | FIRST_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); |
| 1428 | p_eth_port_ctrl->tx_resource_err[queue] = false; |
| 1429 | } |
| 1430 | |
| 1431 | eth_port_reset (p_eth_port_ctrl->port_num); |
| 1432 | |
| 1433 | /* Set access parameters for DRAM bank 0 */ |
| 1434 | win_param.win = ETH_WIN0; /* Use Ethernet window 0 */ |
| 1435 | win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ |
| 1436 | win_param.attributes = EBAR_ATTR_DRAM_CS0; /* Enable DRAM bank */ |
| 1437 | #ifndef CONFIG_NOT_COHERENT_CACHE |
| 1438 | win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; |
| 1439 | #endif |
| 1440 | win_param.high_addr = 0; |
| 1441 | /* Get bank base */ |
| 1442 | win_param.base_addr = mv_get_dram_bank_base_addr (BANK0); |
| 1443 | win_param.size = mv_get_dram_bank_size (BANK0); /* Get bank size */ |
| 1444 | if (win_param.size == 0) |
| 1445 | win_param.enable = 0; |
| 1446 | else |
| 1447 | win_param.enable = 1; /* Enable the access */ |
| 1448 | win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ |
| 1449 | |
| 1450 | /* Set the access control for address window (EPAPR) READ & WRITE */ |
| 1451 | eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); |
| 1452 | |
| 1453 | /* Set access parameters for DRAM bank 1 */ |
| 1454 | win_param.win = ETH_WIN1; /* Use Ethernet window 1 */ |
| 1455 | win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ |
| 1456 | win_param.attributes = EBAR_ATTR_DRAM_CS1; /* Enable DRAM bank */ |
| 1457 | #ifndef CONFIG_NOT_COHERENT_CACHE |
| 1458 | win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; |
| 1459 | #endif |
| 1460 | win_param.high_addr = 0; |
| 1461 | /* Get bank base */ |
| 1462 | win_param.base_addr = mv_get_dram_bank_base_addr (BANK1); |
| 1463 | win_param.size = mv_get_dram_bank_size (BANK1); /* Get bank size */ |
| 1464 | if (win_param.size == 0) |
| 1465 | win_param.enable = 0; |
| 1466 | else |
| 1467 | win_param.enable = 1; /* Enable the access */ |
| 1468 | win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ |
| 1469 | |
| 1470 | /* Set the access control for address window (EPAPR) READ & WRITE */ |
| 1471 | eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); |
| 1472 | |
| 1473 | /* Set access parameters for DRAM bank 2 */ |
| 1474 | win_param.win = ETH_WIN2; /* Use Ethernet window 2 */ |
| 1475 | win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ |
| 1476 | win_param.attributes = EBAR_ATTR_DRAM_CS2; /* Enable DRAM bank */ |
| 1477 | #ifndef CONFIG_NOT_COHERENT_CACHE |
| 1478 | win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; |
| 1479 | #endif |
| 1480 | win_param.high_addr = 0; |
| 1481 | /* Get bank base */ |
| 1482 | win_param.base_addr = mv_get_dram_bank_base_addr (BANK2); |
| 1483 | win_param.size = mv_get_dram_bank_size (BANK2); /* Get bank size */ |
| 1484 | if (win_param.size == 0) |
| 1485 | win_param.enable = 0; |
| 1486 | else |
| 1487 | win_param.enable = 1; /* Enable the access */ |
| 1488 | win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ |
| 1489 | |
| 1490 | /* Set the access control for address window (EPAPR) READ & WRITE */ |
| 1491 | eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); |
| 1492 | |
| 1493 | /* Set access parameters for DRAM bank 3 */ |
| 1494 | win_param.win = ETH_WIN3; /* Use Ethernet window 3 */ |
| 1495 | win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ |
| 1496 | win_param.attributes = EBAR_ATTR_DRAM_CS3; /* Enable DRAM bank */ |
| 1497 | #ifndef CONFIG_NOT_COHERENT_CACHE |
| 1498 | win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; |
| 1499 | #endif |
| 1500 | win_param.high_addr = 0; |
| 1501 | /* Get bank base */ |
| 1502 | win_param.base_addr = mv_get_dram_bank_base_addr (BANK3); |
| 1503 | win_param.size = mv_get_dram_bank_size (BANK3); /* Get bank size */ |
| 1504 | if (win_param.size == 0) |
| 1505 | win_param.enable = 0; |
| 1506 | else |
| 1507 | win_param.enable = 1; /* Enable the access */ |
| 1508 | win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ |
| 1509 | |
| 1510 | /* Set the access control for address window (EPAPR) READ & WRITE */ |
| 1511 | eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); |
| 1512 | |
| 1513 | /* Set access parameters for Internal SRAM */ |
| 1514 | win_param.win = ETH_WIN4; /* Use Ethernet window 0 */ |
| 1515 | win_param.target = EBAR_TARGET_CBS; /* Target - Internal SRAM */ |
| 1516 | win_param.attributes = EBAR_ATTR_CBS_SRAM | EBAR_ATTR_CBS_SRAM_BLOCK0; |
| 1517 | win_param.high_addr = 0; |
| 1518 | win_param.base_addr = mv_get_internal_sram_base (); /* Get base addr */ |
| 1519 | win_param.size = MV64360_INTERNAL_SRAM_SIZE; /* Get bank size */ |
| 1520 | win_param.enable = 1; /* Enable the access */ |
| 1521 | win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ |
| 1522 | |
| 1523 | /* Set the access control for address window (EPAPR) READ & WRITE */ |
| 1524 | eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); |
| 1525 | |
| 1526 | eth_port_init_mac_tables (p_eth_port_ctrl->port_num); |
| 1527 | |
| 1528 | ethernet_phy_set (p_eth_port_ctrl->port_num, |
| 1529 | p_eth_port_ctrl->port_phy_addr); |
| 1530 | |
| 1531 | return; |
| 1532 | |
| 1533 | } |
| 1534 | |
| 1535 | /******************************************************************************* |
| 1536 | * eth_port_start - Start the Ethernet port activity. |
| 1537 | * |
| 1538 | * DESCRIPTION: |
| 1539 | * This routine prepares the Ethernet port for Rx and Tx activity: |
| 1540 | * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that |
| 1541 | * has been initialized a descriptor's ring (using ether_init_tx_desc_ring |
| 1542 | * for Tx and ether_init_rx_desc_ring for Rx) |
| 1543 | * 2. Initialize and enable the Ethernet configuration port by writing to |
| 1544 | * the port's configuration and command registers. |
| 1545 | * 3. Initialize and enable the SDMA by writing to the SDMA's |
| 1546 | * configuration and command registers. |
| 1547 | * After completing these steps, the ethernet port SDMA can starts to |
| 1548 | * perform Rx and Tx activities. |
| 1549 | * |
| 1550 | * Note: Each Rx and Tx queue descriptor's list must be initialized prior |
| 1551 | * to calling this function (use ether_init_tx_desc_ring for Tx queues and |
| 1552 | * ether_init_rx_desc_ring for Rx queues). |
| 1553 | * |
| 1554 | * INPUT: |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame^] | 1555 | * ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct |
stroese | 771e05b | 2004-12-16 18:21:17 +0000 | [diff] [blame] | 1556 | * |
| 1557 | * OUTPUT: |
| 1558 | * Ethernet port is ready to receive and transmit. |
| 1559 | * |
| 1560 | * RETURN: |
| 1561 | * false if the port PHY is not up. |
| 1562 | * true otherwise. |
| 1563 | * |
| 1564 | *******************************************************************************/ |
| 1565 | static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl) |
| 1566 | { |
| 1567 | int queue; |
| 1568 | volatile ETH_TX_DESC *p_tx_curr_desc; |
| 1569 | volatile ETH_RX_DESC *p_rx_curr_desc; |
| 1570 | unsigned int phy_reg_data; |
| 1571 | ETH_PORT eth_port_num = p_eth_port_ctrl->port_num; |
| 1572 | |
| 1573 | |
| 1574 | /* Assignment of Tx CTRP of given queue */ |
| 1575 | for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) { |
| 1576 | CURR_TFD_GET (p_tx_curr_desc, queue); |
| 1577 | MV_REG_WRITE ((MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_0 |
| 1578 | (eth_port_num) |
| 1579 | + (4 * queue)), |
| 1580 | ((unsigned int) p_tx_curr_desc)); |
| 1581 | |
| 1582 | } |
| 1583 | |
| 1584 | /* Assignment of Rx CRDP of given queue */ |
| 1585 | for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) { |
| 1586 | CURR_RFD_GET (p_rx_curr_desc, queue); |
| 1587 | MV_REG_WRITE ((MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_0 |
| 1588 | (eth_port_num) |
| 1589 | + (4 * queue)), |
| 1590 | ((unsigned int) p_rx_curr_desc)); |
| 1591 | |
| 1592 | if (p_rx_curr_desc != NULL) |
| 1593 | /* Add the assigned Ethernet address to the port's address table */ |
| 1594 | eth_port_uc_addr_set (p_eth_port_ctrl->port_num, |
| 1595 | p_eth_port_ctrl->port_mac_addr, |
| 1596 | queue); |
| 1597 | } |
| 1598 | |
| 1599 | /* Assign port configuration and command. */ |
| 1600 | MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num), |
| 1601 | p_eth_port_ctrl->port_config); |
| 1602 | |
| 1603 | MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num), |
| 1604 | p_eth_port_ctrl->port_config_extend); |
| 1605 | |
| 1606 | MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), |
| 1607 | p_eth_port_ctrl->port_serial_control); |
| 1608 | |
| 1609 | MV_SET_REG_BITS (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), |
| 1610 | ETH_SERIAL_PORT_ENABLE); |
| 1611 | |
| 1612 | /* Assign port SDMA configuration */ |
| 1613 | MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num), |
| 1614 | p_eth_port_ctrl->port_sdma_config); |
| 1615 | |
| 1616 | MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT |
| 1617 | (eth_port_num), 0x3fffffff); |
| 1618 | MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG |
| 1619 | (eth_port_num), 0x03fffcff); |
| 1620 | /* Turn off the port/queue bandwidth limitation */ |
| 1621 | MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (eth_port_num), 0x0); |
| 1622 | |
| 1623 | /* Enable port Rx. */ |
| 1624 | MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (eth_port_num), |
| 1625 | p_eth_port_ctrl->port_rx_queue_command); |
| 1626 | |
| 1627 | /* Check if link is up */ |
| 1628 | eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data); |
| 1629 | |
| 1630 | if (!(phy_reg_data & 0x20)) |
| 1631 | return false; |
| 1632 | |
| 1633 | return true; |
| 1634 | } |
| 1635 | |
| 1636 | /******************************************************************************* |
| 1637 | * eth_port_uc_addr_set - This function Set the port Unicast address. |
| 1638 | * |
| 1639 | * DESCRIPTION: |
| 1640 | * This function Set the port Ethernet MAC address. |
| 1641 | * |
| 1642 | * INPUT: |
| 1643 | * ETH_PORT eth_port_num Port number. |
| 1644 | * char * p_addr Address to be set |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame^] | 1645 | * ETH_QUEUE queue Rx queue number for this MAC address. |
stroese | 771e05b | 2004-12-16 18:21:17 +0000 | [diff] [blame] | 1646 | * |
| 1647 | * OUTPUT: |
| 1648 | * Set MAC address low and high registers. also calls eth_port_uc_addr() |
| 1649 | * To set the unicast table with the proper information. |
| 1650 | * |
| 1651 | * RETURN: |
| 1652 | * N/A. |
| 1653 | * |
| 1654 | *******************************************************************************/ |
| 1655 | static void eth_port_uc_addr_set (ETH_PORT eth_port_num, |
| 1656 | unsigned char *p_addr, ETH_QUEUE queue) |
| 1657 | { |
| 1658 | unsigned int mac_h; |
| 1659 | unsigned int mac_l; |
| 1660 | |
| 1661 | mac_l = (p_addr[4] << 8) | (p_addr[5]); |
| 1662 | mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | |
| 1663 | (p_addr[2] << 8) | (p_addr[3] << 0); |
| 1664 | |
| 1665 | MV_REG_WRITE (MV64360_ETH_MAC_ADDR_LOW (eth_port_num), mac_l); |
| 1666 | MV_REG_WRITE (MV64360_ETH_MAC_ADDR_HIGH (eth_port_num), mac_h); |
| 1667 | |
| 1668 | /* Accept frames of this address */ |
| 1669 | eth_port_uc_addr (eth_port_num, p_addr[5], queue, ACCEPT_MAC_ADDR); |
| 1670 | |
| 1671 | return; |
| 1672 | } |
| 1673 | |
| 1674 | /******************************************************************************* |
| 1675 | * eth_port_uc_addr - This function Set the port unicast address table |
| 1676 | * |
| 1677 | * DESCRIPTION: |
| 1678 | * This function locates the proper entry in the Unicast table for the |
| 1679 | * specified MAC nibble and sets its properties according to function |
| 1680 | * parameters. |
| 1681 | * |
| 1682 | * INPUT: |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame^] | 1683 | * ETH_PORT eth_port_num Port number. |
stroese | 771e05b | 2004-12-16 18:21:17 +0000 | [diff] [blame] | 1684 | * unsigned char uc_nibble Unicast MAC Address last nibble. |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame^] | 1685 | * ETH_QUEUE queue Rx queue number for this MAC address. |
| 1686 | * int option 0 = Add, 1 = remove address. |
stroese | 771e05b | 2004-12-16 18:21:17 +0000 | [diff] [blame] | 1687 | * |
| 1688 | * OUTPUT: |
| 1689 | * This function add/removes MAC addresses from the port unicast address |
| 1690 | * table. |
| 1691 | * |
| 1692 | * RETURN: |
| 1693 | * true is output succeeded. |
| 1694 | * false if option parameter is invalid. |
| 1695 | * |
| 1696 | *******************************************************************************/ |
| 1697 | static bool eth_port_uc_addr (ETH_PORT eth_port_num, |
| 1698 | unsigned char uc_nibble, |
| 1699 | ETH_QUEUE queue, int option) |
| 1700 | { |
| 1701 | unsigned int unicast_reg; |
| 1702 | unsigned int tbl_offset; |
| 1703 | unsigned int reg_offset; |
| 1704 | |
| 1705 | /* Locate the Unicast table entry */ |
| 1706 | uc_nibble = (0xf & uc_nibble); |
| 1707 | tbl_offset = (uc_nibble / 4) * 4; /* Register offset from unicast table base */ |
| 1708 | reg_offset = uc_nibble % 4; /* Entry offset within the above register */ |
| 1709 | |
| 1710 | switch (option) { |
| 1711 | case REJECT_MAC_ADDR: |
| 1712 | /* Clear accepts frame bit at specified unicast DA table entry */ |
| 1713 | unicast_reg = |
| 1714 | MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE |
| 1715 | (eth_port_num) |
| 1716 | + tbl_offset)); |
| 1717 | |
| 1718 | unicast_reg &= (0x0E << (8 * reg_offset)); |
| 1719 | |
| 1720 | MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE |
| 1721 | (eth_port_num) |
| 1722 | + tbl_offset), unicast_reg); |
| 1723 | break; |
| 1724 | |
| 1725 | case ACCEPT_MAC_ADDR: |
| 1726 | /* Set accepts frame bit at unicast DA filter table entry */ |
| 1727 | unicast_reg = |
| 1728 | MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE |
| 1729 | (eth_port_num) |
| 1730 | + tbl_offset)); |
| 1731 | |
| 1732 | unicast_reg |= ((0x01 | queue) << (8 * reg_offset)); |
| 1733 | |
| 1734 | MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE |
| 1735 | (eth_port_num) |
| 1736 | + tbl_offset), unicast_reg); |
| 1737 | |
| 1738 | break; |
| 1739 | |
| 1740 | default: |
| 1741 | return false; |
| 1742 | } |
| 1743 | return true; |
| 1744 | } |
| 1745 | |
| 1746 | #if 0 /* FIXME */ |
| 1747 | /******************************************************************************* |
| 1748 | * eth_port_mc_addr - Multicast address settings. |
| 1749 | * |
| 1750 | * DESCRIPTION: |
| 1751 | * This API controls the MV device MAC multicast support. |
| 1752 | * The MV device supports multicast using two tables: |
| 1753 | * 1) Special Multicast Table for MAC addresses of the form |
| 1754 | * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF). |
| 1755 | * The MAC DA[7:0] bits are used as a pointer to the Special Multicast |
| 1756 | * Table entries in the DA-Filter table. |
| 1757 | * In this case, the function calls eth_port_smc_addr() routine to set the |
| 1758 | * Special Multicast Table. |
| 1759 | * 2) Other Multicast Table for multicast of another type. A CRC-8bit |
| 1760 | * is used as an index to the Other Multicast Table entries in the |
| 1761 | * DA-Filter table. |
| 1762 | * In this case, the function calculates the CRC-8bit value and calls |
| 1763 | * eth_port_omc_addr() routine to set the Other Multicast Table. |
| 1764 | * INPUT: |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame^] | 1765 | * ETH_PORT eth_port_num Port number. |
| 1766 | * unsigned char *p_addr Unicast MAC Address. |
| 1767 | * ETH_QUEUE queue Rx queue number for this MAC address. |
| 1768 | * int option 0 = Add, 1 = remove address. |
stroese | 771e05b | 2004-12-16 18:21:17 +0000 | [diff] [blame] | 1769 | * |
| 1770 | * OUTPUT: |
| 1771 | * See description. |
| 1772 | * |
| 1773 | * RETURN: |
| 1774 | * true is output succeeded. |
| 1775 | * false if add_address_table_entry( ) failed. |
| 1776 | * |
| 1777 | *******************************************************************************/ |
| 1778 | static void eth_port_mc_addr (ETH_PORT eth_port_num, |
| 1779 | unsigned char *p_addr, |
| 1780 | ETH_QUEUE queue, int option) |
| 1781 | { |
| 1782 | unsigned int mac_h; |
| 1783 | unsigned int mac_l; |
| 1784 | unsigned char crc_result = 0; |
| 1785 | int mac_array[48]; |
| 1786 | int crc[8]; |
| 1787 | int i; |
| 1788 | |
| 1789 | |
| 1790 | if ((p_addr[0] == 0x01) && |
| 1791 | (p_addr[1] == 0x00) && |
| 1792 | (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) |
| 1793 | |
| 1794 | eth_port_smc_addr (eth_port_num, p_addr[5], queue, option); |
| 1795 | else { |
| 1796 | /* Calculate CRC-8 out of the given address */ |
| 1797 | mac_h = (p_addr[0] << 8) | (p_addr[1]); |
| 1798 | mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) | |
| 1799 | (p_addr[4] << 8) | (p_addr[5] << 0); |
| 1800 | |
| 1801 | for (i = 0; i < 32; i++) |
| 1802 | mac_array[i] = (mac_l >> i) & 0x1; |
| 1803 | for (i = 32; i < 48; i++) |
| 1804 | mac_array[i] = (mac_h >> (i - 32)) & 0x1; |
| 1805 | |
| 1806 | |
| 1807 | crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ |
| 1808 | mac_array[39] ^ mac_array[35] ^ mac_array[34] ^ |
| 1809 | mac_array[31] ^ mac_array[30] ^ mac_array[28] ^ |
| 1810 | mac_array[23] ^ mac_array[21] ^ mac_array[19] ^ |
| 1811 | mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ |
| 1812 | mac_array[12] ^ mac_array[8] ^ mac_array[7] ^ |
| 1813 | mac_array[6] ^ mac_array[0]; |
| 1814 | |
| 1815 | crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ |
| 1816 | mac_array[43] ^ mac_array[41] ^ mac_array[39] ^ |
| 1817 | mac_array[36] ^ mac_array[34] ^ mac_array[32] ^ |
| 1818 | mac_array[30] ^ mac_array[29] ^ mac_array[28] ^ |
| 1819 | mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ |
| 1820 | mac_array[21] ^ mac_array[20] ^ mac_array[18] ^ |
| 1821 | mac_array[17] ^ mac_array[16] ^ mac_array[15] ^ |
| 1822 | mac_array[14] ^ mac_array[13] ^ mac_array[12] ^ |
| 1823 | mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ |
| 1824 | mac_array[0]; |
| 1825 | |
| 1826 | crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ |
| 1827 | mac_array[43] ^ mac_array[42] ^ mac_array[39] ^ |
| 1828 | mac_array[37] ^ mac_array[34] ^ mac_array[33] ^ |
| 1829 | mac_array[29] ^ mac_array[28] ^ mac_array[25] ^ |
| 1830 | mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ |
| 1831 | mac_array[15] ^ mac_array[13] ^ mac_array[12] ^ |
| 1832 | mac_array[10] ^ mac_array[8] ^ mac_array[6] ^ |
| 1833 | mac_array[2] ^ mac_array[1] ^ mac_array[0]; |
| 1834 | |
| 1835 | crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ |
| 1836 | mac_array[43] ^ mac_array[40] ^ mac_array[38] ^ |
| 1837 | mac_array[35] ^ mac_array[34] ^ mac_array[30] ^ |
| 1838 | mac_array[29] ^ mac_array[26] ^ mac_array[25] ^ |
| 1839 | mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ |
| 1840 | mac_array[14] ^ mac_array[13] ^ mac_array[11] ^ |
| 1841 | mac_array[9] ^ mac_array[7] ^ mac_array[3] ^ |
| 1842 | mac_array[2] ^ mac_array[1]; |
| 1843 | |
| 1844 | crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ |
| 1845 | mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ |
| 1846 | mac_array[35] ^ mac_array[31] ^ mac_array[30] ^ |
| 1847 | mac_array[27] ^ mac_array[26] ^ mac_array[24] ^ |
| 1848 | mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ |
| 1849 | mac_array[14] ^ mac_array[12] ^ mac_array[10] ^ |
| 1850 | mac_array[8] ^ mac_array[4] ^ mac_array[3] ^ |
| 1851 | mac_array[2]; |
| 1852 | |
| 1853 | crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ |
| 1854 | mac_array[42] ^ mac_array[40] ^ mac_array[37] ^ |
| 1855 | mac_array[36] ^ mac_array[32] ^ mac_array[31] ^ |
| 1856 | mac_array[28] ^ mac_array[27] ^ mac_array[25] ^ |
| 1857 | mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ |
| 1858 | mac_array[15] ^ mac_array[13] ^ mac_array[11] ^ |
| 1859 | mac_array[9] ^ mac_array[5] ^ mac_array[4] ^ |
| 1860 | mac_array[3]; |
| 1861 | |
| 1862 | crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ |
| 1863 | mac_array[41] ^ mac_array[38] ^ mac_array[37] ^ |
| 1864 | mac_array[33] ^ mac_array[32] ^ mac_array[29] ^ |
| 1865 | mac_array[28] ^ mac_array[26] ^ mac_array[21] ^ |
| 1866 | mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ |
| 1867 | mac_array[14] ^ mac_array[12] ^ mac_array[10] ^ |
| 1868 | mac_array[6] ^ mac_array[5] ^ mac_array[4]; |
| 1869 | |
| 1870 | crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ |
| 1871 | mac_array[39] ^ mac_array[38] ^ mac_array[34] ^ |
| 1872 | mac_array[33] ^ mac_array[30] ^ mac_array[29] ^ |
| 1873 | mac_array[27] ^ mac_array[22] ^ mac_array[20] ^ |
| 1874 | mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ |
| 1875 | mac_array[13] ^ mac_array[11] ^ mac_array[7] ^ |
| 1876 | mac_array[6] ^ mac_array[5]; |
| 1877 | |
| 1878 | for (i = 0; i < 8; i++) |
| 1879 | crc_result = crc_result | (crc[i] << i); |
| 1880 | |
| 1881 | eth_port_omc_addr (eth_port_num, crc_result, queue, option); |
| 1882 | } |
| 1883 | return; |
| 1884 | } |
| 1885 | |
| 1886 | /******************************************************************************* |
| 1887 | * eth_port_smc_addr - Special Multicast address settings. |
| 1888 | * |
| 1889 | * DESCRIPTION: |
| 1890 | * This routine controls the MV device special MAC multicast support. |
| 1891 | * The Special Multicast Table for MAC addresses supports MAC of the form |
| 1892 | * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF). |
| 1893 | * The MAC DA[7:0] bits are used as a pointer to the Special Multicast |
| 1894 | * Table entries in the DA-Filter table. |
| 1895 | * This function set the Special Multicast Table appropriate entry |
| 1896 | * according to the argument given. |
| 1897 | * |
| 1898 | * INPUT: |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame^] | 1899 | * ETH_PORT eth_port_num Port number. |
| 1900 | * unsigned char mc_byte Multicast addr last byte (MAC DA[7:0] bits). |
| 1901 | * ETH_QUEUE queue Rx queue number for this MAC address. |
| 1902 | * int option 0 = Add, 1 = remove address. |
stroese | 771e05b | 2004-12-16 18:21:17 +0000 | [diff] [blame] | 1903 | * |
| 1904 | * OUTPUT: |
| 1905 | * See description. |
| 1906 | * |
| 1907 | * RETURN: |
| 1908 | * true is output succeeded. |
| 1909 | * false if option parameter is invalid. |
| 1910 | * |
| 1911 | *******************************************************************************/ |
| 1912 | static bool eth_port_smc_addr (ETH_PORT eth_port_num, |
| 1913 | unsigned char mc_byte, |
| 1914 | ETH_QUEUE queue, int option) |
| 1915 | { |
| 1916 | unsigned int smc_table_reg; |
| 1917 | unsigned int tbl_offset; |
| 1918 | unsigned int reg_offset; |
| 1919 | |
| 1920 | /* Locate the SMC table entry */ |
| 1921 | tbl_offset = (mc_byte / 4) * 4; /* Register offset from SMC table base */ |
| 1922 | reg_offset = mc_byte % 4; /* Entry offset within the above register */ |
| 1923 | queue &= 0x7; |
| 1924 | |
| 1925 | switch (option) { |
| 1926 | case REJECT_MAC_ADDR: |
| 1927 | /* Clear accepts frame bit at specified Special DA table entry */ |
| 1928 | smc_table_reg = |
| 1929 | MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); |
| 1930 | smc_table_reg &= (0x0E << (8 * reg_offset)); |
| 1931 | |
| 1932 | MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg); |
| 1933 | break; |
| 1934 | |
| 1935 | case ACCEPT_MAC_ADDR: |
| 1936 | /* Set accepts frame bit at specified Special DA table entry */ |
| 1937 | smc_table_reg = |
| 1938 | MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); |
| 1939 | smc_table_reg |= ((0x01 | queue) << (8 * reg_offset)); |
| 1940 | |
| 1941 | MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg); |
| 1942 | break; |
| 1943 | |
| 1944 | default: |
| 1945 | return false; |
| 1946 | } |
| 1947 | return true; |
| 1948 | } |
| 1949 | |
| 1950 | /******************************************************************************* |
| 1951 | * eth_port_omc_addr - Multicast address settings. |
| 1952 | * |
| 1953 | * DESCRIPTION: |
| 1954 | * This routine controls the MV device Other MAC multicast support. |
| 1955 | * The Other Multicast Table is used for multicast of another type. |
| 1956 | * A CRC-8bit is used as an index to the Other Multicast Table entries |
| 1957 | * in the DA-Filter table. |
| 1958 | * The function gets the CRC-8bit value from the calling routine and |
| 1959 | * set the Other Multicast Table appropriate entry according to the |
| 1960 | * CRC-8 argument given. |
| 1961 | * |
| 1962 | * INPUT: |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame^] | 1963 | * ETH_PORT eth_port_num Port number. |
| 1964 | * unsigned char crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1). |
| 1965 | * ETH_QUEUE queue Rx queue number for this MAC address. |
| 1966 | * int option 0 = Add, 1 = remove address. |
stroese | 771e05b | 2004-12-16 18:21:17 +0000 | [diff] [blame] | 1967 | * |
| 1968 | * OUTPUT: |
| 1969 | * See description. |
| 1970 | * |
| 1971 | * RETURN: |
| 1972 | * true is output succeeded. |
| 1973 | * false if option parameter is invalid. |
| 1974 | * |
| 1975 | *******************************************************************************/ |
| 1976 | static bool eth_port_omc_addr (ETH_PORT eth_port_num, |
| 1977 | unsigned char crc8, |
| 1978 | ETH_QUEUE queue, int option) |
| 1979 | { |
| 1980 | unsigned int omc_table_reg; |
| 1981 | unsigned int tbl_offset; |
| 1982 | unsigned int reg_offset; |
| 1983 | |
| 1984 | /* Locate the OMC table entry */ |
| 1985 | tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ |
| 1986 | reg_offset = crc8 % 4; /* Entry offset within the above register */ |
| 1987 | queue &= 0x7; |
| 1988 | |
| 1989 | switch (option) { |
| 1990 | case REJECT_MAC_ADDR: |
| 1991 | /* Clear accepts frame bit at specified Other DA table entry */ |
| 1992 | omc_table_reg = |
| 1993 | MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); |
| 1994 | omc_table_reg &= (0x0E << (8 * reg_offset)); |
| 1995 | |
| 1996 | MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg); |
| 1997 | break; |
| 1998 | |
| 1999 | case ACCEPT_MAC_ADDR: |
| 2000 | /* Set accepts frame bit at specified Other DA table entry */ |
| 2001 | omc_table_reg = |
| 2002 | MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); |
| 2003 | omc_table_reg |= ((0x01 | queue) << (8 * reg_offset)); |
| 2004 | |
| 2005 | MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg); |
| 2006 | break; |
| 2007 | |
| 2008 | default: |
| 2009 | return false; |
| 2010 | } |
| 2011 | return true; |
| 2012 | } |
| 2013 | #endif |
| 2014 | |
| 2015 | /******************************************************************************* |
| 2016 | * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables |
| 2017 | * |
| 2018 | * DESCRIPTION: |
| 2019 | * Go through all the DA filter tables (Unicast, Special Multicast & Other |
| 2020 | * Multicast) and set each entry to 0. |
| 2021 | * |
| 2022 | * INPUT: |
| 2023 | * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. |
| 2024 | * |
| 2025 | * OUTPUT: |
| 2026 | * Multicast and Unicast packets are rejected. |
| 2027 | * |
| 2028 | * RETURN: |
| 2029 | * None. |
| 2030 | * |
| 2031 | *******************************************************************************/ |
| 2032 | static void eth_port_init_mac_tables (ETH_PORT eth_port_num) |
| 2033 | { |
| 2034 | int table_index; |
| 2035 | |
| 2036 | /* Clear DA filter unicast table (Ex_dFUT) */ |
| 2037 | for (table_index = 0; table_index <= 0xC; table_index += 4) |
| 2038 | MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE |
| 2039 | (eth_port_num) + table_index), 0); |
| 2040 | |
| 2041 | for (table_index = 0; table_index <= 0xFC; table_index += 4) { |
| 2042 | /* Clear DA filter special multicast table (Ex_dFSMT) */ |
| 2043 | MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0); |
| 2044 | /* Clear DA filter other multicast table (Ex_dFOMT) */ |
| 2045 | MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0); |
| 2046 | } |
| 2047 | } |
| 2048 | |
| 2049 | /******************************************************************************* |
| 2050 | * eth_clear_mib_counters - Clear all MIB counters |
| 2051 | * |
| 2052 | * DESCRIPTION: |
| 2053 | * This function clears all MIB counters of a specific ethernet port. |
| 2054 | * A read from the MIB counter will reset the counter. |
| 2055 | * |
| 2056 | * INPUT: |
| 2057 | * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. |
| 2058 | * |
| 2059 | * OUTPUT: |
| 2060 | * After reading all MIB counters, the counters resets. |
| 2061 | * |
| 2062 | * RETURN: |
| 2063 | * MIB counter value. |
| 2064 | * |
| 2065 | *******************************************************************************/ |
| 2066 | static void eth_clear_mib_counters (ETH_PORT eth_port_num) |
| 2067 | { |
| 2068 | int i; |
| 2069 | unsigned int dummy; |
| 2070 | |
| 2071 | /* Perform dummy reads from MIB counters */ |
| 2072 | for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION; |
| 2073 | i += 4) |
| 2074 | dummy = MV_REG_READ ((MV64360_ETH_MIB_COUNTERS_BASE |
| 2075 | (eth_port_num) + i)); |
| 2076 | |
| 2077 | return; |
| 2078 | } |
| 2079 | |
| 2080 | /******************************************************************************* |
| 2081 | * eth_read_mib_counter - Read a MIB counter |
| 2082 | * |
| 2083 | * DESCRIPTION: |
| 2084 | * This function reads a MIB counter of a specific ethernet port. |
| 2085 | * NOTE - If read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, then the |
| 2086 | * following read must be from ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH |
| 2087 | * register. The same applies for ETH_MIB_GOOD_OCTETS_SENT_LOW and |
| 2088 | * ETH_MIB_GOOD_OCTETS_SENT_HIGH |
| 2089 | * |
| 2090 | * INPUT: |
| 2091 | * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. |
| 2092 | * unsigned int mib_offset MIB counter offset (use ETH_MIB_... macros). |
| 2093 | * |
| 2094 | * OUTPUT: |
| 2095 | * After reading the MIB counter, the counter resets. |
| 2096 | * |
| 2097 | * RETURN: |
| 2098 | * MIB counter value. |
| 2099 | * |
| 2100 | *******************************************************************************/ |
| 2101 | unsigned int eth_read_mib_counter (ETH_PORT eth_port_num, |
| 2102 | unsigned int mib_offset) |
| 2103 | { |
| 2104 | return (MV_REG_READ (MV64360_ETH_MIB_COUNTERS_BASE (eth_port_num) |
| 2105 | + mib_offset)); |
| 2106 | } |
| 2107 | |
| 2108 | /******************************************************************************* |
| 2109 | * ethernet_phy_set - Set the ethernet port PHY address. |
| 2110 | * |
| 2111 | * DESCRIPTION: |
| 2112 | * This routine set the ethernet port PHY address according to given |
| 2113 | * parameter. |
| 2114 | * |
| 2115 | * INPUT: |
| 2116 | * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. |
| 2117 | * |
| 2118 | * OUTPUT: |
| 2119 | * Set PHY Address Register with given PHY address parameter. |
| 2120 | * |
| 2121 | * RETURN: |
| 2122 | * None. |
| 2123 | * |
| 2124 | *******************************************************************************/ |
| 2125 | static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr) |
| 2126 | { |
| 2127 | unsigned int reg_data; |
| 2128 | |
| 2129 | reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG); |
| 2130 | |
| 2131 | reg_data &= ~(0x1F << (5 * eth_port_num)); |
| 2132 | reg_data |= (phy_addr << (5 * eth_port_num)); |
| 2133 | |
| 2134 | MV_REG_WRITE (MV64360_ETH_PHY_ADDR_REG, reg_data); |
| 2135 | |
| 2136 | return; |
| 2137 | } |
| 2138 | |
| 2139 | /******************************************************************************* |
| 2140 | * ethernet_phy_get - Get the ethernet port PHY address. |
| 2141 | * |
| 2142 | * DESCRIPTION: |
| 2143 | * This routine returns the given ethernet port PHY address. |
| 2144 | * |
| 2145 | * INPUT: |
| 2146 | * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. |
| 2147 | * |
| 2148 | * OUTPUT: |
| 2149 | * None. |
| 2150 | * |
| 2151 | * RETURN: |
| 2152 | * PHY address. |
| 2153 | * |
| 2154 | *******************************************************************************/ |
| 2155 | static int ethernet_phy_get (ETH_PORT eth_port_num) |
| 2156 | { |
| 2157 | unsigned int reg_data; |
| 2158 | |
| 2159 | reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG); |
| 2160 | |
| 2161 | return ((reg_data >> (5 * eth_port_num)) & 0x1f); |
| 2162 | } |
| 2163 | |
| 2164 | /******************************************************************************* |
| 2165 | * ethernet_phy_reset - Reset Ethernet port PHY. |
| 2166 | * |
| 2167 | * DESCRIPTION: |
| 2168 | * This routine utilize the SMI interface to reset the ethernet port PHY. |
| 2169 | * The routine waits until the link is up again or link up is timeout. |
| 2170 | * |
| 2171 | * INPUT: |
| 2172 | * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. |
| 2173 | * |
| 2174 | * OUTPUT: |
| 2175 | * The ethernet port PHY renew its link. |
| 2176 | * |
| 2177 | * RETURN: |
| 2178 | * None. |
| 2179 | * |
| 2180 | *******************************************************************************/ |
| 2181 | static bool ethernet_phy_reset (ETH_PORT eth_port_num) |
| 2182 | { |
| 2183 | unsigned int time_out = 50; |
| 2184 | unsigned int phy_reg_data; |
| 2185 | |
| 2186 | /* Reset the PHY */ |
| 2187 | eth_port_read_smi_reg (eth_port_num, 0, &phy_reg_data); |
| 2188 | phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */ |
| 2189 | eth_port_write_smi_reg (eth_port_num, 0, phy_reg_data); |
| 2190 | |
| 2191 | /* Poll on the PHY LINK */ |
| 2192 | do { |
| 2193 | eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data); |
| 2194 | |
| 2195 | if (time_out-- == 0) |
| 2196 | return false; |
| 2197 | } |
| 2198 | while (!(phy_reg_data & 0x20)); |
| 2199 | |
| 2200 | return true; |
| 2201 | } |
| 2202 | |
| 2203 | /******************************************************************************* |
| 2204 | * eth_port_reset - Reset Ethernet port |
| 2205 | * |
| 2206 | * DESCRIPTION: |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame^] | 2207 | * This routine resets the chip by aborting any SDMA engine activity and |
stroese | 771e05b | 2004-12-16 18:21:17 +0000 | [diff] [blame] | 2208 | * clearing the MIB counters. The Receiver and the Transmit unit are in |
| 2209 | * idle state after this command is performed and the port is disabled. |
| 2210 | * |
| 2211 | * INPUT: |
| 2212 | * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. |
| 2213 | * |
| 2214 | * OUTPUT: |
| 2215 | * Channel activity is halted. |
| 2216 | * |
| 2217 | * RETURN: |
| 2218 | * None. |
| 2219 | * |
| 2220 | *******************************************************************************/ |
| 2221 | static void eth_port_reset (ETH_PORT eth_port_num) |
| 2222 | { |
| 2223 | unsigned int reg_data; |
| 2224 | |
| 2225 | /* Stop Tx port activity. Check port Tx activity. */ |
| 2226 | reg_data = |
| 2227 | MV_REG_READ (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG |
| 2228 | (eth_port_num)); |
| 2229 | |
| 2230 | if (reg_data & 0xFF) { |
| 2231 | /* Issue stop command for active channels only */ |
| 2232 | MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG |
| 2233 | (eth_port_num), (reg_data << 8)); |
| 2234 | |
| 2235 | /* Wait for all Tx activity to terminate. */ |
| 2236 | do { |
| 2237 | /* Check port cause register that all Tx queues are stopped */ |
| 2238 | reg_data = |
| 2239 | MV_REG_READ |
| 2240 | (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG |
| 2241 | (eth_port_num)); |
| 2242 | } |
| 2243 | while (reg_data & 0xFF); |
| 2244 | } |
| 2245 | |
| 2246 | /* Stop Rx port activity. Check port Rx activity. */ |
| 2247 | reg_data = |
| 2248 | MV_REG_READ (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG |
| 2249 | (eth_port_num)); |
| 2250 | |
| 2251 | if (reg_data & 0xFF) { |
| 2252 | /* Issue stop command for active channels only */ |
| 2253 | MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG |
| 2254 | (eth_port_num), (reg_data << 8)); |
| 2255 | |
| 2256 | /* Wait for all Rx activity to terminate. */ |
| 2257 | do { |
| 2258 | /* Check port cause register that all Rx queues are stopped */ |
| 2259 | reg_data = |
| 2260 | MV_REG_READ |
| 2261 | (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG |
| 2262 | (eth_port_num)); |
| 2263 | } |
| 2264 | while (reg_data & 0xFF); |
| 2265 | } |
| 2266 | |
| 2267 | |
| 2268 | /* Clear all MIB counters */ |
| 2269 | eth_clear_mib_counters (eth_port_num); |
| 2270 | |
| 2271 | /* Reset the Enable bit in the Configuration Register */ |
| 2272 | reg_data = |
| 2273 | MV_REG_READ (MV64360_ETH_PORT_SERIAL_CONTROL_REG |
| 2274 | (eth_port_num)); |
| 2275 | reg_data &= ~ETH_SERIAL_PORT_ENABLE; |
| 2276 | MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), |
| 2277 | reg_data); |
| 2278 | |
| 2279 | return; |
| 2280 | } |
| 2281 | |
| 2282 | #if 0 /* Not needed here */ |
| 2283 | /******************************************************************************* |
| 2284 | * ethernet_set_config_reg - Set specified bits in configuration register. |
| 2285 | * |
| 2286 | * DESCRIPTION: |
| 2287 | * This function sets specified bits in the given ethernet |
| 2288 | * configuration register. |
| 2289 | * |
| 2290 | * INPUT: |
| 2291 | * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. |
| 2292 | * unsigned int value 32 bit value. |
| 2293 | * |
| 2294 | * OUTPUT: |
| 2295 | * The set bits in the value parameter are set in the configuration |
| 2296 | * register. |
| 2297 | * |
| 2298 | * RETURN: |
| 2299 | * None. |
| 2300 | * |
| 2301 | *******************************************************************************/ |
| 2302 | static void ethernet_set_config_reg (ETH_PORT eth_port_num, |
| 2303 | unsigned int value) |
| 2304 | { |
| 2305 | unsigned int eth_config_reg; |
| 2306 | |
| 2307 | eth_config_reg = |
| 2308 | MV_REG_READ (MV64360_ETH_PORT_CONFIG_REG (eth_port_num)); |
| 2309 | eth_config_reg |= value; |
| 2310 | MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num), |
| 2311 | eth_config_reg); |
| 2312 | |
| 2313 | return; |
| 2314 | } |
| 2315 | #endif |
| 2316 | |
| 2317 | #if 0 /* FIXME */ |
| 2318 | /******************************************************************************* |
| 2319 | * ethernet_reset_config_reg - Reset specified bits in configuration register. |
| 2320 | * |
| 2321 | * DESCRIPTION: |
| 2322 | * This function resets specified bits in the given Ethernet |
| 2323 | * configuration register. |
| 2324 | * |
| 2325 | * INPUT: |
| 2326 | * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. |
| 2327 | * unsigned int value 32 bit value. |
| 2328 | * |
| 2329 | * OUTPUT: |
| 2330 | * The set bits in the value parameter are reset in the configuration |
| 2331 | * register. |
| 2332 | * |
| 2333 | * RETURN: |
| 2334 | * None. |
| 2335 | * |
| 2336 | *******************************************************************************/ |
| 2337 | static void ethernet_reset_config_reg (ETH_PORT eth_port_num, |
| 2338 | unsigned int value) |
| 2339 | { |
| 2340 | unsigned int eth_config_reg; |
| 2341 | |
| 2342 | eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG |
| 2343 | (eth_port_num)); |
| 2344 | eth_config_reg &= ~value; |
| 2345 | MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num), |
| 2346 | eth_config_reg); |
| 2347 | |
| 2348 | return; |
| 2349 | } |
| 2350 | #endif |
| 2351 | |
| 2352 | #if 0 /* Not needed here */ |
| 2353 | /******************************************************************************* |
| 2354 | * ethernet_get_config_reg - Get the port configuration register |
| 2355 | * |
| 2356 | * DESCRIPTION: |
| 2357 | * This function returns the configuration register value of the given |
| 2358 | * ethernet port. |
| 2359 | * |
| 2360 | * INPUT: |
| 2361 | * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. |
| 2362 | * |
| 2363 | * OUTPUT: |
| 2364 | * None. |
| 2365 | * |
| 2366 | * RETURN: |
| 2367 | * Port configuration register value. |
| 2368 | * |
| 2369 | *******************************************************************************/ |
| 2370 | static unsigned int ethernet_get_config_reg (ETH_PORT eth_port_num) |
| 2371 | { |
| 2372 | unsigned int eth_config_reg; |
| 2373 | |
| 2374 | eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG |
| 2375 | (eth_port_num)); |
| 2376 | return eth_config_reg; |
| 2377 | } |
| 2378 | |
| 2379 | #endif |
| 2380 | |
| 2381 | /******************************************************************************* |
| 2382 | * eth_port_read_smi_reg - Read PHY registers |
| 2383 | * |
| 2384 | * DESCRIPTION: |
| 2385 | * This routine utilize the SMI interface to interact with the PHY in |
| 2386 | * order to perform PHY register read. |
| 2387 | * |
| 2388 | * INPUT: |
| 2389 | * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. |
| 2390 | * unsigned int phy_reg PHY register address offset. |
| 2391 | * unsigned int *value Register value buffer. |
| 2392 | * |
| 2393 | * OUTPUT: |
| 2394 | * Write the value of a specified PHY register into given buffer. |
| 2395 | * |
| 2396 | * RETURN: |
| 2397 | * false if the PHY is busy or read data is not in valid state. |
| 2398 | * true otherwise. |
| 2399 | * |
| 2400 | *******************************************************************************/ |
| 2401 | static bool eth_port_read_smi_reg (ETH_PORT eth_port_num, |
| 2402 | unsigned int phy_reg, unsigned int *value) |
| 2403 | { |
| 2404 | unsigned int reg_value; |
| 2405 | unsigned int time_out = PHY_BUSY_TIMEOUT; |
| 2406 | int phy_addr; |
| 2407 | |
| 2408 | phy_addr = ethernet_phy_get (eth_port_num); |
| 2409 | /* printf(" Phy-Port %d has addess %d \n",eth_port_num, phy_addr );*/ |
| 2410 | |
| 2411 | /* first check that it is not busy */ |
| 2412 | do { |
| 2413 | reg_value = MV_REG_READ (MV64360_ETH_SMI_REG); |
| 2414 | if (time_out-- == 0) { |
| 2415 | return false; |
| 2416 | } |
| 2417 | } |
| 2418 | while (reg_value & ETH_SMI_BUSY); |
| 2419 | |
| 2420 | /* not busy */ |
| 2421 | |
| 2422 | MV_REG_WRITE (MV64360_ETH_SMI_REG, |
| 2423 | (phy_addr << 16) | (phy_reg << 21) | |
| 2424 | ETH_SMI_OPCODE_READ); |
| 2425 | |
| 2426 | time_out = PHY_BUSY_TIMEOUT; /* initialize the time out var again */ |
| 2427 | |
| 2428 | do { |
| 2429 | reg_value = MV_REG_READ (MV64360_ETH_SMI_REG); |
| 2430 | if (time_out-- == 0) { |
| 2431 | return false; |
| 2432 | } |
| 2433 | } |
| 2434 | while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID); /* Bit set equ operation done */ |
| 2435 | |
| 2436 | /* Wait for the data to update in the SMI register */ |
| 2437 | #define PHY_UPDATE_TIMEOUT 10000 |
| 2438 | for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++); |
| 2439 | |
| 2440 | reg_value = MV_REG_READ (MV64360_ETH_SMI_REG); |
| 2441 | |
| 2442 | *value = reg_value & 0xffff; |
| 2443 | |
| 2444 | return true; |
| 2445 | } |
| 2446 | |
| 2447 | /******************************************************************************* |
| 2448 | * eth_port_write_smi_reg - Write to PHY registers |
| 2449 | * |
| 2450 | * DESCRIPTION: |
| 2451 | * This routine utilize the SMI interface to interact with the PHY in |
| 2452 | * order to perform writes to PHY registers. |
| 2453 | * |
| 2454 | * INPUT: |
| 2455 | * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. |
| 2456 | * unsigned int phy_reg PHY register address offset. |
| 2457 | * unsigned int value Register value. |
| 2458 | * |
| 2459 | * OUTPUT: |
| 2460 | * Write the given value to the specified PHY register. |
| 2461 | * |
| 2462 | * RETURN: |
| 2463 | * false if the PHY is busy. |
| 2464 | * true otherwise. |
| 2465 | * |
| 2466 | *******************************************************************************/ |
| 2467 | static bool eth_port_write_smi_reg (ETH_PORT eth_port_num, |
| 2468 | unsigned int phy_reg, unsigned int value) |
| 2469 | { |
| 2470 | unsigned int reg_value; |
| 2471 | unsigned int time_out = PHY_BUSY_TIMEOUT; |
| 2472 | int phy_addr; |
| 2473 | |
| 2474 | phy_addr = ethernet_phy_get (eth_port_num); |
| 2475 | |
| 2476 | /* first check that it is not busy */ |
| 2477 | do { |
| 2478 | reg_value = MV_REG_READ (MV64360_ETH_SMI_REG); |
| 2479 | if (time_out-- == 0) { |
| 2480 | return false; |
| 2481 | } |
| 2482 | } |
| 2483 | while (reg_value & ETH_SMI_BUSY); |
| 2484 | |
| 2485 | /* not busy */ |
| 2486 | MV_REG_WRITE (MV64360_ETH_SMI_REG, |
| 2487 | (phy_addr << 16) | (phy_reg << 21) | |
| 2488 | ETH_SMI_OPCODE_WRITE | (value & 0xffff)); |
| 2489 | return true; |
| 2490 | } |
| 2491 | |
| 2492 | /******************************************************************************* |
| 2493 | * eth_set_access_control - Config address decode parameters for Ethernet unit |
| 2494 | * |
| 2495 | * DESCRIPTION: |
| 2496 | * This function configures the address decode parameters for the Gigabit |
| 2497 | * Ethernet Controller according the given parameters struct. |
| 2498 | * |
| 2499 | * INPUT: |
| 2500 | * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. |
| 2501 | * ETH_WIN_PARAM *param Address decode parameter struct. |
| 2502 | * |
| 2503 | * OUTPUT: |
| 2504 | * An access window is opened using the given access parameters. |
| 2505 | * |
| 2506 | * RETURN: |
| 2507 | * None. |
| 2508 | * |
| 2509 | *******************************************************************************/ |
| 2510 | static void eth_set_access_control (ETH_PORT eth_port_num, |
| 2511 | ETH_WIN_PARAM * param) |
| 2512 | { |
| 2513 | unsigned int access_prot_reg; |
| 2514 | |
| 2515 | /* Set access control register */ |
| 2516 | access_prot_reg = MV_REG_READ (MV64360_ETH_ACCESS_PROTECTION_REG |
| 2517 | (eth_port_num)); |
| 2518 | access_prot_reg &= (~(3 << (param->win * 2))); /* clear window permission */ |
| 2519 | access_prot_reg |= (param->access_ctrl << (param->win * 2)); |
| 2520 | MV_REG_WRITE (MV64360_ETH_ACCESS_PROTECTION_REG (eth_port_num), |
| 2521 | access_prot_reg); |
| 2522 | |
| 2523 | /* Set window Size reg (SR) */ |
| 2524 | MV_REG_WRITE ((MV64360_ETH_SIZE_REG_0 + |
| 2525 | (ETH_SIZE_REG_GAP * param->win)), |
| 2526 | (((param->size / 0x10000) - 1) << 16)); |
| 2527 | |
| 2528 | /* Set window Base address reg (BA) */ |
| 2529 | MV_REG_WRITE ((MV64360_ETH_BAR_0 + (ETH_BAR_GAP * param->win)), |
| 2530 | (param->target | param->attributes | param->base_addr)); |
| 2531 | /* High address remap reg (HARR) */ |
| 2532 | if (param->win < 4) |
| 2533 | MV_REG_WRITE ((MV64360_ETH_HIGH_ADDR_REMAP_REG_0 + |
| 2534 | (ETH_HIGH_ADDR_REMAP_REG_GAP * param->win)), |
| 2535 | param->high_addr); |
| 2536 | |
| 2537 | /* Base address enable reg (BARER) */ |
| 2538 | if (param->enable == 1) |
| 2539 | MV_RESET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG, |
| 2540 | (1 << param->win)); |
| 2541 | else |
| 2542 | MV_SET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG, |
| 2543 | (1 << param->win)); |
| 2544 | } |
| 2545 | |
| 2546 | /******************************************************************************* |
| 2547 | * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory. |
| 2548 | * |
| 2549 | * DESCRIPTION: |
| 2550 | * This function prepares a Rx chained list of descriptors and packet |
| 2551 | * buffers in a form of a ring. The routine must be called after port |
| 2552 | * initialization routine and before port start routine. |
| 2553 | * The Ethernet SDMA engine uses CPU bus addresses to access the various |
| 2554 | * devices in the system (i.e. DRAM). This function uses the ethernet |
| 2555 | * struct 'virtual to physical' routine (set by the user) to set the ring |
| 2556 | * with physical addresses. |
| 2557 | * |
| 2558 | * INPUT: |
| 2559 | * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame^] | 2560 | * ETH_QUEUE rx_queue Number of Rx queue. |
| 2561 | * int rx_desc_num Number of Rx descriptors |
| 2562 | * int rx_buff_size Size of Rx buffer |
stroese | 771e05b | 2004-12-16 18:21:17 +0000 | [diff] [blame] | 2563 | * unsigned int rx_desc_base_addr Rx descriptors memory area base addr. |
| 2564 | * unsigned int rx_buff_base_addr Rx buffer memory area base addr. |
| 2565 | * |
| 2566 | * OUTPUT: |
| 2567 | * The routine updates the Ethernet port control struct with information |
| 2568 | * regarding the Rx descriptors and buffers. |
| 2569 | * |
| 2570 | * RETURN: |
| 2571 | * false if the given descriptors memory area is not aligned according to |
| 2572 | * Ethernet SDMA specifications. |
| 2573 | * true otherwise. |
| 2574 | * |
| 2575 | *******************************************************************************/ |
| 2576 | static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl, |
| 2577 | ETH_QUEUE rx_queue, |
| 2578 | int rx_desc_num, |
| 2579 | int rx_buff_size, |
| 2580 | unsigned int rx_desc_base_addr, |
| 2581 | unsigned int rx_buff_base_addr) |
| 2582 | { |
| 2583 | ETH_RX_DESC *p_rx_desc; |
| 2584 | ETH_RX_DESC *p_rx_prev_desc; /* pointer to link with the last descriptor */ |
| 2585 | unsigned int buffer_addr; |
| 2586 | int ix; /* a counter */ |
| 2587 | |
| 2588 | |
| 2589 | p_rx_desc = (ETH_RX_DESC *) rx_desc_base_addr; |
| 2590 | p_rx_prev_desc = p_rx_desc; |
| 2591 | buffer_addr = rx_buff_base_addr; |
| 2592 | |
| 2593 | /* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */ |
| 2594 | if (rx_buff_base_addr & 0xF) |
| 2595 | return false; |
| 2596 | |
| 2597 | /* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes */ |
| 2598 | if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE)) |
| 2599 | return false; |
| 2600 | |
| 2601 | /* Rx buffers must be 64-bit aligned. */ |
| 2602 | if ((rx_buff_base_addr + rx_buff_size) & 0x7) |
| 2603 | return false; |
| 2604 | |
| 2605 | /* initialize the Rx descriptors ring */ |
| 2606 | for (ix = 0; ix < rx_desc_num; ix++) { |
| 2607 | p_rx_desc->buf_size = rx_buff_size; |
| 2608 | p_rx_desc->byte_cnt = 0x0000; |
| 2609 | p_rx_desc->cmd_sts = |
| 2610 | ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT; |
| 2611 | p_rx_desc->next_desc_ptr = |
| 2612 | ((unsigned int) p_rx_desc) + RX_DESC_ALIGNED_SIZE; |
| 2613 | p_rx_desc->buf_ptr = buffer_addr; |
| 2614 | p_rx_desc->return_info = 0x00000000; |
| 2615 | D_CACHE_FLUSH_LINE (p_rx_desc, 0); |
| 2616 | buffer_addr += rx_buff_size; |
| 2617 | p_rx_prev_desc = p_rx_desc; |
| 2618 | p_rx_desc = (ETH_RX_DESC *) |
| 2619 | ((unsigned int) p_rx_desc + RX_DESC_ALIGNED_SIZE); |
| 2620 | } |
| 2621 | |
| 2622 | /* Closing Rx descriptors ring */ |
| 2623 | p_rx_prev_desc->next_desc_ptr = (rx_desc_base_addr); |
| 2624 | D_CACHE_FLUSH_LINE (p_rx_prev_desc, 0); |
| 2625 | |
| 2626 | /* Save Rx desc pointer to driver struct. */ |
| 2627 | CURR_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue); |
| 2628 | USED_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue); |
| 2629 | |
| 2630 | p_eth_port_ctrl->p_rx_desc_area_base[rx_queue] = |
| 2631 | (ETH_RX_DESC *) rx_desc_base_addr; |
| 2632 | p_eth_port_ctrl->rx_desc_area_size[rx_queue] = |
| 2633 | rx_desc_num * RX_DESC_ALIGNED_SIZE; |
| 2634 | |
| 2635 | p_eth_port_ctrl->port_rx_queue_command |= (1 << rx_queue); |
| 2636 | |
| 2637 | return true; |
| 2638 | } |
| 2639 | |
| 2640 | /******************************************************************************* |
| 2641 | * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory. |
| 2642 | * |
| 2643 | * DESCRIPTION: |
| 2644 | * This function prepares a Tx chained list of descriptors and packet |
| 2645 | * buffers in a form of a ring. The routine must be called after port |
| 2646 | * initialization routine and before port start routine. |
| 2647 | * The Ethernet SDMA engine uses CPU bus addresses to access the various |
| 2648 | * devices in the system (i.e. DRAM). This function uses the ethernet |
| 2649 | * struct 'virtual to physical' routine (set by the user) to set the ring |
| 2650 | * with physical addresses. |
| 2651 | * |
| 2652 | * INPUT: |
| 2653 | * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame^] | 2654 | * ETH_QUEUE tx_queue Number of Tx queue. |
| 2655 | * int tx_desc_num Number of Tx descriptors |
| 2656 | * int tx_buff_size Size of Tx buffer |
stroese | 771e05b | 2004-12-16 18:21:17 +0000 | [diff] [blame] | 2657 | * unsigned int tx_desc_base_addr Tx descriptors memory area base addr. |
| 2658 | * unsigned int tx_buff_base_addr Tx buffer memory area base addr. |
| 2659 | * |
| 2660 | * OUTPUT: |
| 2661 | * The routine updates the Ethernet port control struct with information |
| 2662 | * regarding the Tx descriptors and buffers. |
| 2663 | * |
| 2664 | * RETURN: |
| 2665 | * false if the given descriptors memory area is not aligned according to |
| 2666 | * Ethernet SDMA specifications. |
| 2667 | * true otherwise. |
| 2668 | * |
| 2669 | *******************************************************************************/ |
| 2670 | static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl, |
| 2671 | ETH_QUEUE tx_queue, |
| 2672 | int tx_desc_num, |
| 2673 | int tx_buff_size, |
| 2674 | unsigned int tx_desc_base_addr, |
| 2675 | unsigned int tx_buff_base_addr) |
| 2676 | { |
| 2677 | |
| 2678 | ETH_TX_DESC *p_tx_desc; |
| 2679 | ETH_TX_DESC *p_tx_prev_desc; |
| 2680 | unsigned int buffer_addr; |
| 2681 | int ix; /* a counter */ |
| 2682 | |
| 2683 | |
| 2684 | /* save the first desc pointer to link with the last descriptor */ |
| 2685 | p_tx_desc = (ETH_TX_DESC *) tx_desc_base_addr; |
| 2686 | p_tx_prev_desc = p_tx_desc; |
| 2687 | buffer_addr = tx_buff_base_addr; |
| 2688 | |
| 2689 | /* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */ |
| 2690 | if (tx_buff_base_addr & 0xF) |
| 2691 | return false; |
| 2692 | |
| 2693 | /* Tx buffers are limited to 64K bytes and Minimum size is 8 bytes */ |
| 2694 | if ((tx_buff_size > TX_BUFFER_MAX_SIZE) |
| 2695 | || (tx_buff_size < TX_BUFFER_MIN_SIZE)) |
| 2696 | return false; |
| 2697 | |
| 2698 | /* Initialize the Tx descriptors ring */ |
| 2699 | for (ix = 0; ix < tx_desc_num; ix++) { |
| 2700 | p_tx_desc->byte_cnt = 0x0000; |
| 2701 | p_tx_desc->l4i_chk = 0x0000; |
| 2702 | p_tx_desc->cmd_sts = 0x00000000; |
| 2703 | p_tx_desc->next_desc_ptr = |
| 2704 | ((unsigned int) p_tx_desc) + TX_DESC_ALIGNED_SIZE; |
| 2705 | |
| 2706 | p_tx_desc->buf_ptr = buffer_addr; |
| 2707 | p_tx_desc->return_info = 0x00000000; |
| 2708 | D_CACHE_FLUSH_LINE (p_tx_desc, 0); |
| 2709 | buffer_addr += tx_buff_size; |
| 2710 | p_tx_prev_desc = p_tx_desc; |
| 2711 | p_tx_desc = (ETH_TX_DESC *) |
| 2712 | ((unsigned int) p_tx_desc + TX_DESC_ALIGNED_SIZE); |
| 2713 | |
| 2714 | } |
| 2715 | /* Closing Tx descriptors ring */ |
| 2716 | p_tx_prev_desc->next_desc_ptr = tx_desc_base_addr; |
| 2717 | D_CACHE_FLUSH_LINE (p_tx_prev_desc, 0); |
| 2718 | /* Set Tx desc pointer in driver struct. */ |
| 2719 | CURR_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue); |
| 2720 | USED_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue); |
| 2721 | |
| 2722 | /* Init Tx ring base and size parameters */ |
| 2723 | p_eth_port_ctrl->p_tx_desc_area_base[tx_queue] = |
| 2724 | (ETH_TX_DESC *) tx_desc_base_addr; |
| 2725 | p_eth_port_ctrl->tx_desc_area_size[tx_queue] = |
| 2726 | (tx_desc_num * TX_DESC_ALIGNED_SIZE); |
| 2727 | |
| 2728 | /* Add the queue to the list of Tx queues of this port */ |
| 2729 | p_eth_port_ctrl->port_tx_queue_command |= (1 << tx_queue); |
| 2730 | |
| 2731 | return true; |
| 2732 | } |
| 2733 | |
| 2734 | /******************************************************************************* |
| 2735 | * eth_port_send - Send an Ethernet packet |
| 2736 | * |
| 2737 | * DESCRIPTION: |
| 2738 | * This routine send a given packet described by p_pktinfo parameter. It |
| 2739 | * supports transmitting of a packet spaned over multiple buffers. The |
| 2740 | * routine updates 'curr' and 'first' indexes according to the packet |
| 2741 | * segment passed to the routine. In case the packet segment is first, |
| 2742 | * the 'first' index is update. In any case, the 'curr' index is updated. |
| 2743 | * If the routine get into Tx resource error it assigns 'curr' index as |
| 2744 | * 'first'. This way the function can abort Tx process of multiple |
| 2745 | * descriptors per packet. |
| 2746 | * |
| 2747 | * INPUT: |
| 2748 | * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame^] | 2749 | * ETH_QUEUE tx_queue Number of Tx queue. |
stroese | 771e05b | 2004-12-16 18:21:17 +0000 | [diff] [blame] | 2750 | * PKT_INFO *p_pkt_info User packet buffer. |
| 2751 | * |
| 2752 | * OUTPUT: |
| 2753 | * Tx ring 'curr' and 'first' indexes are updated. |
| 2754 | * |
| 2755 | * RETURN: |
| 2756 | * ETH_QUEUE_FULL in case of Tx resource error. |
| 2757 | * ETH_ERROR in case the routine can not access Tx desc ring. |
| 2758 | * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource. |
| 2759 | * ETH_OK otherwise. |
| 2760 | * |
| 2761 | *******************************************************************************/ |
| 2762 | static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl, |
| 2763 | ETH_QUEUE tx_queue, |
| 2764 | PKT_INFO * p_pkt_info) |
| 2765 | { |
| 2766 | volatile ETH_TX_DESC *p_tx_desc_first; |
| 2767 | volatile ETH_TX_DESC *p_tx_desc_curr; |
| 2768 | volatile ETH_TX_DESC *p_tx_next_desc_curr; |
| 2769 | volatile ETH_TX_DESC *p_tx_desc_used; |
| 2770 | unsigned int command_status; |
| 2771 | |
| 2772 | /* Do not process Tx ring in case of Tx ring resource error */ |
| 2773 | if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true) |
| 2774 | return ETH_QUEUE_FULL; |
| 2775 | |
| 2776 | /* Get the Tx Desc ring indexes */ |
| 2777 | CURR_TFD_GET (p_tx_desc_curr, tx_queue); |
| 2778 | USED_TFD_GET (p_tx_desc_used, tx_queue); |
| 2779 | |
| 2780 | if (p_tx_desc_curr == NULL) |
| 2781 | return ETH_ERROR; |
| 2782 | |
| 2783 | /* The following parameters are used to save readings from memory */ |
| 2784 | p_tx_next_desc_curr = TX_NEXT_DESC_PTR (p_tx_desc_curr, tx_queue); |
| 2785 | command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC; |
| 2786 | |
| 2787 | if (command_status & (ETH_TX_FIRST_DESC)) { |
| 2788 | /* Update first desc */ |
| 2789 | FIRST_TFD_SET (p_tx_desc_curr, tx_queue); |
| 2790 | p_tx_desc_first = p_tx_desc_curr; |
| 2791 | } else { |
| 2792 | FIRST_TFD_GET (p_tx_desc_first, tx_queue); |
| 2793 | command_status |= ETH_BUFFER_OWNED_BY_DMA; |
| 2794 | } |
| 2795 | |
| 2796 | /* Buffers with a payload smaller than 8 bytes must be aligned to 64-bit */ |
| 2797 | /* boundary. We use the memory allocated for Tx descriptor. This memory */ |
| 2798 | /* located in TX_BUF_OFFSET_IN_DESC offset within the Tx descriptor. */ |
| 2799 | if (p_pkt_info->byte_cnt <= 8) { |
| 2800 | printf ("You have failed in the < 8 bytes errata - fixme\n"); /* RABEEH - TBD */ |
| 2801 | return ETH_ERROR; |
| 2802 | |
| 2803 | p_tx_desc_curr->buf_ptr = |
| 2804 | (unsigned int) p_tx_desc_curr + TX_BUF_OFFSET_IN_DESC; |
| 2805 | eth_b_copy (p_pkt_info->buf_ptr, p_tx_desc_curr->buf_ptr, |
| 2806 | p_pkt_info->byte_cnt); |
| 2807 | } else |
| 2808 | p_tx_desc_curr->buf_ptr = p_pkt_info->buf_ptr; |
| 2809 | |
| 2810 | p_tx_desc_curr->byte_cnt = p_pkt_info->byte_cnt; |
| 2811 | p_tx_desc_curr->return_info = p_pkt_info->return_info; |
| 2812 | |
| 2813 | if (p_pkt_info->cmd_sts & (ETH_TX_LAST_DESC)) { |
| 2814 | /* Set last desc with DMA ownership and interrupt enable. */ |
| 2815 | p_tx_desc_curr->cmd_sts = command_status | |
| 2816 | ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT; |
| 2817 | |
| 2818 | if (p_tx_desc_curr != p_tx_desc_first) |
| 2819 | p_tx_desc_first->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA; |
| 2820 | |
| 2821 | /* Flush CPU pipe */ |
| 2822 | |
| 2823 | D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0); |
| 2824 | D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_first, 0); |
| 2825 | CPU_PIPE_FLUSH; |
| 2826 | |
| 2827 | /* Apply send command */ |
| 2828 | ETH_ENABLE_TX_QUEUE (tx_queue, p_eth_port_ctrl->port_num); |
| 2829 | |
| 2830 | /* Finish Tx packet. Update first desc in case of Tx resource error */ |
| 2831 | p_tx_desc_first = p_tx_next_desc_curr; |
| 2832 | FIRST_TFD_SET (p_tx_desc_first, tx_queue); |
| 2833 | |
| 2834 | } else { |
| 2835 | p_tx_desc_curr->cmd_sts = command_status; |
| 2836 | D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0); |
| 2837 | } |
| 2838 | |
| 2839 | /* Check for ring index overlap in the Tx desc ring */ |
| 2840 | if (p_tx_next_desc_curr == p_tx_desc_used) { |
| 2841 | /* Update the current descriptor */ |
| 2842 | CURR_TFD_SET (p_tx_desc_first, tx_queue); |
| 2843 | |
| 2844 | p_eth_port_ctrl->tx_resource_err[tx_queue] = true; |
| 2845 | return ETH_QUEUE_LAST_RESOURCE; |
| 2846 | } else { |
| 2847 | /* Update the current descriptor */ |
| 2848 | CURR_TFD_SET (p_tx_next_desc_curr, tx_queue); |
| 2849 | return ETH_OK; |
| 2850 | } |
| 2851 | } |
| 2852 | |
| 2853 | /******************************************************************************* |
| 2854 | * eth_tx_return_desc - Free all used Tx descriptors |
| 2855 | * |
| 2856 | * DESCRIPTION: |
| 2857 | * This routine returns the transmitted packet information to the caller. |
| 2858 | * It uses the 'first' index to support Tx desc return in case a transmit |
| 2859 | * of a packet spanned over multiple buffer still in process. |
| 2860 | * In case the Tx queue was in "resource error" condition, where there are |
| 2861 | * no available Tx resources, the function resets the resource error flag. |
| 2862 | * |
| 2863 | * INPUT: |
| 2864 | * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame^] | 2865 | * ETH_QUEUE tx_queue Number of Tx queue. |
stroese | 771e05b | 2004-12-16 18:21:17 +0000 | [diff] [blame] | 2866 | * PKT_INFO *p_pkt_info User packet buffer. |
| 2867 | * |
| 2868 | * OUTPUT: |
| 2869 | * Tx ring 'first' and 'used' indexes are updated. |
| 2870 | * |
| 2871 | * RETURN: |
| 2872 | * ETH_ERROR in case the routine can not access Tx desc ring. |
| 2873 | * ETH_RETRY in case there is transmission in process. |
| 2874 | * ETH_END_OF_JOB if the routine has nothing to release. |
| 2875 | * ETH_OK otherwise. |
| 2876 | * |
| 2877 | *******************************************************************************/ |
| 2878 | static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO * |
| 2879 | p_eth_port_ctrl, |
| 2880 | ETH_QUEUE tx_queue, |
| 2881 | PKT_INFO * p_pkt_info) |
| 2882 | { |
| 2883 | volatile ETH_TX_DESC *p_tx_desc_used = NULL; |
| 2884 | volatile ETH_TX_DESC *p_tx_desc_first = NULL; |
| 2885 | unsigned int command_status; |
| 2886 | |
| 2887 | |
| 2888 | /* Get the Tx Desc ring indexes */ |
| 2889 | USED_TFD_GET (p_tx_desc_used, tx_queue); |
| 2890 | FIRST_TFD_GET (p_tx_desc_first, tx_queue); |
| 2891 | |
| 2892 | |
| 2893 | /* Sanity check */ |
| 2894 | if (p_tx_desc_used == NULL) |
| 2895 | return ETH_ERROR; |
| 2896 | |
| 2897 | command_status = p_tx_desc_used->cmd_sts; |
| 2898 | |
| 2899 | /* Still transmitting... */ |
| 2900 | if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { |
| 2901 | D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); |
| 2902 | return ETH_RETRY; |
| 2903 | } |
| 2904 | |
| 2905 | /* Stop release. About to overlap the current available Tx descriptor */ |
| 2906 | if ((p_tx_desc_used == p_tx_desc_first) && |
| 2907 | (p_eth_port_ctrl->tx_resource_err[tx_queue] == false)) { |
| 2908 | D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); |
| 2909 | return ETH_END_OF_JOB; |
| 2910 | } |
| 2911 | |
| 2912 | /* Pass the packet information to the caller */ |
| 2913 | p_pkt_info->cmd_sts = command_status; |
| 2914 | p_pkt_info->return_info = p_tx_desc_used->return_info; |
| 2915 | p_tx_desc_used->return_info = 0; |
| 2916 | |
| 2917 | /* Update the next descriptor to release. */ |
| 2918 | USED_TFD_SET (TX_NEXT_DESC_PTR (p_tx_desc_used, tx_queue), tx_queue); |
| 2919 | |
| 2920 | /* Any Tx return cancels the Tx resource error status */ |
| 2921 | if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true) |
| 2922 | p_eth_port_ctrl->tx_resource_err[tx_queue] = false; |
| 2923 | |
| 2924 | D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); |
| 2925 | |
| 2926 | return ETH_OK; |
| 2927 | |
| 2928 | } |
| 2929 | |
| 2930 | /******************************************************************************* |
| 2931 | * eth_port_receive - Get received information from Rx ring. |
| 2932 | * |
| 2933 | * DESCRIPTION: |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame^] | 2934 | * This routine returns the received data to the caller. There is no |
stroese | 771e05b | 2004-12-16 18:21:17 +0000 | [diff] [blame] | 2935 | * data copying during routine operation. All information is returned |
| 2936 | * using pointer to packet information struct passed from the caller. |
| 2937 | * If the routine exhausts Rx ring resources then the resource error flag |
| 2938 | * is set. |
| 2939 | * |
| 2940 | * INPUT: |
| 2941 | * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame^] | 2942 | * ETH_QUEUE rx_queue Number of Rx queue. |
stroese | 771e05b | 2004-12-16 18:21:17 +0000 | [diff] [blame] | 2943 | * PKT_INFO *p_pkt_info User packet buffer. |
| 2944 | * |
| 2945 | * OUTPUT: |
| 2946 | * Rx ring current and used indexes are updated. |
| 2947 | * |
| 2948 | * RETURN: |
| 2949 | * ETH_ERROR in case the routine can not access Rx desc ring. |
| 2950 | * ETH_QUEUE_FULL if Rx ring resources are exhausted. |
| 2951 | * ETH_END_OF_JOB if there is no received data. |
| 2952 | * ETH_OK otherwise. |
| 2953 | * |
| 2954 | *******************************************************************************/ |
| 2955 | static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl, |
| 2956 | ETH_QUEUE rx_queue, |
| 2957 | PKT_INFO * p_pkt_info) |
| 2958 | { |
| 2959 | volatile ETH_RX_DESC *p_rx_curr_desc; |
| 2960 | volatile ETH_RX_DESC *p_rx_next_curr_desc; |
| 2961 | volatile ETH_RX_DESC *p_rx_used_desc; |
| 2962 | unsigned int command_status; |
| 2963 | |
| 2964 | /* Do not process Rx ring in case of Rx ring resource error */ |
| 2965 | if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) { |
| 2966 | printf ("\nRx Queue is full ...\n"); |
| 2967 | return ETH_QUEUE_FULL; |
| 2968 | } |
| 2969 | |
| 2970 | /* Get the Rx Desc ring 'curr and 'used' indexes */ |
| 2971 | CURR_RFD_GET (p_rx_curr_desc, rx_queue); |
| 2972 | USED_RFD_GET (p_rx_used_desc, rx_queue); |
| 2973 | |
| 2974 | /* Sanity check */ |
| 2975 | if (p_rx_curr_desc == NULL) |
| 2976 | return ETH_ERROR; |
| 2977 | |
| 2978 | /* The following parameters are used to save readings from memory */ |
| 2979 | p_rx_next_curr_desc = RX_NEXT_DESC_PTR (p_rx_curr_desc, rx_queue); |
| 2980 | command_status = p_rx_curr_desc->cmd_sts; |
| 2981 | |
| 2982 | /* Nothing to receive... */ |
| 2983 | if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame^] | 2984 | /* DP(printf("Rx: command_status: %08x\n", command_status)); */ |
stroese | 771e05b | 2004-12-16 18:21:17 +0000 | [diff] [blame] | 2985 | D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0); |
| 2986 | /* DP(printf("\nETH_END_OF_JOB ...\n"));*/ |
| 2987 | return ETH_END_OF_JOB; |
| 2988 | } |
| 2989 | |
| 2990 | p_pkt_info->byte_cnt = (p_rx_curr_desc->byte_cnt) - RX_BUF_OFFSET; |
| 2991 | p_pkt_info->cmd_sts = command_status; |
| 2992 | p_pkt_info->buf_ptr = (p_rx_curr_desc->buf_ptr) + RX_BUF_OFFSET; |
| 2993 | p_pkt_info->return_info = p_rx_curr_desc->return_info; |
| 2994 | p_pkt_info->l4i_chk = p_rx_curr_desc->buf_size; /* IP fragment indicator */ |
| 2995 | |
| 2996 | /* Clean the return info field to indicate that the packet has been */ |
| 2997 | /* moved to the upper layers */ |
| 2998 | p_rx_curr_desc->return_info = 0; |
| 2999 | |
| 3000 | /* Update 'curr' in data structure */ |
| 3001 | CURR_RFD_SET (p_rx_next_curr_desc, rx_queue); |
| 3002 | |
| 3003 | /* Rx descriptors resource exhausted. Set the Rx ring resource error flag */ |
| 3004 | if (p_rx_next_curr_desc == p_rx_used_desc) |
| 3005 | p_eth_port_ctrl->rx_resource_err[rx_queue] = true; |
| 3006 | |
| 3007 | D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0); |
| 3008 | CPU_PIPE_FLUSH; |
| 3009 | return ETH_OK; |
| 3010 | } |
| 3011 | |
| 3012 | /******************************************************************************* |
| 3013 | * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring. |
| 3014 | * |
| 3015 | * DESCRIPTION: |
| 3016 | * This routine returns a Rx buffer back to the Rx ring. It retrieves the |
| 3017 | * next 'used' descriptor and attached the returned buffer to it. |
| 3018 | * In case the Rx ring was in "resource error" condition, where there are |
| 3019 | * no available Rx resources, the function resets the resource error flag. |
| 3020 | * |
| 3021 | * INPUT: |
| 3022 | * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame^] | 3023 | * ETH_QUEUE rx_queue Number of Rx queue. |
stroese | 771e05b | 2004-12-16 18:21:17 +0000 | [diff] [blame] | 3024 | * PKT_INFO *p_pkt_info Information on the returned buffer. |
| 3025 | * |
| 3026 | * OUTPUT: |
| 3027 | * New available Rx resource in Rx descriptor ring. |
| 3028 | * |
| 3029 | * RETURN: |
| 3030 | * ETH_ERROR in case the routine can not access Rx desc ring. |
| 3031 | * ETH_OK otherwise. |
| 3032 | * |
| 3033 | *******************************************************************************/ |
| 3034 | static ETH_FUNC_RET_STATUS eth_rx_return_buff (ETH_PORT_INFO * |
| 3035 | p_eth_port_ctrl, |
| 3036 | ETH_QUEUE rx_queue, |
| 3037 | PKT_INFO * p_pkt_info) |
| 3038 | { |
| 3039 | volatile ETH_RX_DESC *p_used_rx_desc; /* Where to return Rx resource */ |
| 3040 | |
| 3041 | /* Get 'used' Rx descriptor */ |
| 3042 | USED_RFD_GET (p_used_rx_desc, rx_queue); |
| 3043 | |
| 3044 | /* Sanity check */ |
| 3045 | if (p_used_rx_desc == NULL) |
| 3046 | return ETH_ERROR; |
| 3047 | |
| 3048 | p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr; |
| 3049 | p_used_rx_desc->return_info = p_pkt_info->return_info; |
| 3050 | p_used_rx_desc->byte_cnt = p_pkt_info->byte_cnt; |
| 3051 | p_used_rx_desc->buf_size = MV64360_RX_BUFFER_SIZE; /* Reset Buffer size */ |
| 3052 | |
| 3053 | /* Flush the write pipe */ |
| 3054 | CPU_PIPE_FLUSH; |
| 3055 | |
| 3056 | /* Return the descriptor to DMA ownership */ |
| 3057 | p_used_rx_desc->cmd_sts = |
| 3058 | ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT; |
| 3059 | |
| 3060 | /* Flush descriptor and CPU pipe */ |
| 3061 | D_CACHE_FLUSH_LINE ((unsigned int) p_used_rx_desc, 0); |
| 3062 | CPU_PIPE_FLUSH; |
| 3063 | |
| 3064 | /* Move the used descriptor pointer to the next descriptor */ |
| 3065 | USED_RFD_SET (RX_NEXT_DESC_PTR (p_used_rx_desc, rx_queue), rx_queue); |
| 3066 | |
| 3067 | /* Any Rx return cancels the Rx resource error status */ |
| 3068 | if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) |
| 3069 | p_eth_port_ctrl->rx_resource_err[rx_queue] = false; |
| 3070 | |
| 3071 | return ETH_OK; |
| 3072 | } |
| 3073 | |
| 3074 | /******************************************************************************* |
| 3075 | * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path |
| 3076 | * |
| 3077 | * DESCRIPTION: |
| 3078 | * This routine sets the RX coalescing interrupt mechanism parameter. |
| 3079 | * This parameter is a timeout counter, that counts in 64 t_clk |
| 3080 | * chunks ; that when timeout event occurs a maskable interrupt |
| 3081 | * occurs. |
| 3082 | * The parameter is calculated using the tClk of the MV-643xx chip |
| 3083 | * , and the required delay of the interrupt in usec. |
| 3084 | * |
| 3085 | * INPUT: |
| 3086 | * ETH_PORT eth_port_num Ethernet port number |
| 3087 | * unsigned int t_clk t_clk of the MV-643xx chip in HZ units |
| 3088 | * unsigned int delay Delay in usec |
| 3089 | * |
| 3090 | * OUTPUT: |
| 3091 | * Interrupt coalescing mechanism value is set in MV-643xx chip. |
| 3092 | * |
| 3093 | * RETURN: |
| 3094 | * The interrupt coalescing value set in the gigE port. |
| 3095 | * |
| 3096 | *******************************************************************************/ |
| 3097 | #if 0 /* FIXME */ |
| 3098 | static unsigned int eth_port_set_rx_coal (ETH_PORT eth_port_num, |
| 3099 | unsigned int t_clk, |
| 3100 | unsigned int delay) |
| 3101 | { |
| 3102 | unsigned int coal; |
| 3103 | |
| 3104 | coal = ((t_clk / 1000000) * delay) / 64; |
| 3105 | /* Set RX Coalescing mechanism */ |
| 3106 | MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num), |
| 3107 | ((coal & 0x3fff) << 8) | |
| 3108 | (MV_REG_READ |
| 3109 | (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num)) |
| 3110 | & 0xffc000ff)); |
| 3111 | return coal; |
| 3112 | } |
| 3113 | |
| 3114 | #endif |
| 3115 | /******************************************************************************* |
| 3116 | * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path |
| 3117 | * |
| 3118 | * DESCRIPTION: |
| 3119 | * This routine sets the TX coalescing interrupt mechanism parameter. |
| 3120 | * This parameter is a timeout counter, that counts in 64 t_clk |
| 3121 | * chunks ; that when timeout event occurs a maskable interrupt |
| 3122 | * occurs. |
| 3123 | * The parameter is calculated using the t_cLK frequency of the |
| 3124 | * MV-643xx chip and the required delay in the interrupt in uSec |
| 3125 | * |
| 3126 | * INPUT: |
| 3127 | * ETH_PORT eth_port_num Ethernet port number |
| 3128 | * unsigned int t_clk t_clk of the MV-643xx chip in HZ units |
| 3129 | * unsigned int delay Delay in uSeconds |
| 3130 | * |
| 3131 | * OUTPUT: |
| 3132 | * Interrupt coalescing mechanism value is set in MV-643xx chip. |
| 3133 | * |
| 3134 | * RETURN: |
| 3135 | * The interrupt coalescing value set in the gigE port. |
| 3136 | * |
| 3137 | *******************************************************************************/ |
| 3138 | #if 0 /* FIXME */ |
| 3139 | static unsigned int eth_port_set_tx_coal (ETH_PORT eth_port_num, |
| 3140 | unsigned int t_clk, |
| 3141 | unsigned int delay) |
| 3142 | { |
| 3143 | unsigned int coal; |
| 3144 | |
| 3145 | coal = ((t_clk / 1000000) * delay) / 64; |
| 3146 | /* Set TX Coalescing mechanism */ |
| 3147 | MV_REG_WRITE (MV64360_ETH_TX_FIFO_URGENT_THRESHOLD_REG (eth_port_num), |
| 3148 | coal << 4); |
| 3149 | return coal; |
| 3150 | } |
| 3151 | #endif |
| 3152 | |
| 3153 | /******************************************************************************* |
| 3154 | * eth_b_copy - Copy bytes from source to destination |
| 3155 | * |
| 3156 | * DESCRIPTION: |
| 3157 | * This function supports the eight bytes limitation on Tx buffer size. |
| 3158 | * The routine will zero eight bytes starting from the destination address |
| 3159 | * followed by copying bytes from the source address to the destination. |
| 3160 | * |
| 3161 | * INPUT: |
| 3162 | * unsigned int src_addr 32 bit source address. |
| 3163 | * unsigned int dst_addr 32 bit destination address. |
| 3164 | * int byte_count Number of bytes to copy. |
| 3165 | * |
| 3166 | * OUTPUT: |
| 3167 | * See description. |
| 3168 | * |
| 3169 | * RETURN: |
| 3170 | * None. |
| 3171 | * |
| 3172 | *******************************************************************************/ |
| 3173 | static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr, |
| 3174 | int byte_count) |
| 3175 | { |
| 3176 | /* Zero the dst_addr area */ |
| 3177 | *(unsigned int *) dst_addr = 0x0; |
| 3178 | |
| 3179 | while (byte_count != 0) { |
| 3180 | *(char *) dst_addr = *(char *) src_addr; |
| 3181 | dst_addr++; |
| 3182 | src_addr++; |
| 3183 | byte_count--; |
| 3184 | } |
| 3185 | } |