Blame - arch/riscv/Kconfig - github/trini/u-boot

blob: 0de77a75d7b8f4ee222baf3b9c752d573d08ac49 [file] [log] [blame]

Bin Meng	117a433	2018-09-26 06:55:06 -0700	[diff] [blame]	1	menu "RISC-V architecture"
Rick Chen	f94c44e	2017-12-26 13:55:52 +0800	[diff] [blame]	2	depends on RISCV
				3
				4	config SYS_ARCH
				5	default "riscv"
				6
				7	choice
				8	prompt "Target select"
				9	optional
				10
Rick Chen	6f4dd62	2018-05-29 09:54:40 +0800	[diff] [blame]	11	config TARGET_AX25_AE350
				12	bool "Support ax25-ae350"
Rick Chen	f94c44e	2017-12-26 13:55:52 +0800	[diff] [blame]	13
Bin Meng	510e379	2018-09-26 06:55:21 -0700	[diff] [blame]	14	config TARGET_QEMU_VIRT
				15	bool "Support QEMU Virt Board"
				16
Rick Chen	f94c44e	2017-12-26 13:55:52 +0800	[diff] [blame]	17	endchoice
				18
Rick Chen	6f4dd62	2018-05-29 09:54:40 +0800	[diff] [blame]	19	source "board/AndesTech/ax25-ae350/Kconfig"
Bin Meng	510e379	2018-09-26 06:55:21 -0700	[diff] [blame]	20	source "board/emulation/qemu-riscv/Kconfig"
Rick Chen	f94c44e	2017-12-26 13:55:52 +0800	[diff] [blame]	21
				22	choice
Lukas Auer	862e2e7	2018-11-22 11:26:12 +0100	[diff] [blame]	23	prompt "Base ISA"
				24	default ARCH_RV32I
Rick Chen	f94c44e	2017-12-26 13:55:52 +0800	[diff] [blame]	25
Lukas Auer	862e2e7	2018-11-22 11:26:12 +0100	[diff] [blame]	26	config ARCH_RV32I
				27	bool "RV32I"
Rick Chen	f94c44e	2017-12-26 13:55:52 +0800	[diff] [blame]	28	select 32BIT
				29	help
Lukas Auer	862e2e7	2018-11-22 11:26:12 +0100	[diff] [blame]	30	Choose this option to target the RV32I base integer instruction set.
Rick Chen	f94c44e	2017-12-26 13:55:52 +0800	[diff] [blame]	31
Lukas Auer	862e2e7	2018-11-22 11:26:12 +0100	[diff] [blame]	32	config ARCH_RV64I
				33	bool "RV64I"
Rick Chen	f94c44e	2017-12-26 13:55:52 +0800	[diff] [blame]	34	select 64BIT
Lukas Auer	7115856	2018-11-22 11:26:13 +0100	[diff] [blame]	35	select PHYS_64BIT
Rick Chen	f94c44e	2017-12-26 13:55:52 +0800	[diff] [blame]	36	help
Lukas Auer	862e2e7	2018-11-22 11:26:12 +0100	[diff] [blame]	37	Choose this option to target the RV64I base integer instruction set.
Rick Chen	f94c44e	2017-12-26 13:55:52 +0800	[diff] [blame]	38
				39	endchoice
				40
Lukas Auer	d57ffa6	2018-11-22 11:26:14 +0100	[diff] [blame]	41	config RISCV_ISA_C
				42	bool "Emit compressed instructions"
				43	default y
				44	help
				45	Adds "C" to the ISA subsets that the toolchain is allowed to emit
				46	when building U-Boot, which results in compressed instructions in the
				47	U-Boot binary.
				48
				49	config RISCV_ISA_A
				50	def_bool y
				51
Rick Chen	f94c44e	2017-12-26 13:55:52 +0800	[diff] [blame]	52	config 32BIT
				53	bool
				54
				55	config 64BIT
				56	bool
				57
				58	endmenu