blob: 35518da6257581d5f742c4336d3c42586c96df25 [file] [log] [blame]
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +09001/*
2 * include/configs/alt.h
3 * This file is alt board configuration.
4 *
5 * Copyright (C) 2014 Renesas Electronics Corporation
6 *
7 * SPDX-License-Identifier: GPL-2.0
8 */
9
10#ifndef __ALT_H
11#define __ALT_H
12
13#undef DEBUG
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090014#define CONFIG_R8A7794
Nobuhiro Iwamatsu1cc95f62015-10-10 05:58:28 +090015#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Alt"
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090016
Nobuhiro Iwamatsu5ca6dfe2014-11-10 14:34:07 +090017#include "rcar-gen2-common.h"
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090018
Nobuhiro Iwamatsu1cc95f62015-10-10 05:58:28 +090019#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
Nobuhiro Iwamatsuc9b59bf72014-10-31 16:16:28 +090020#define CONFIG_SYS_TEXT_BASE 0x70000000
21#else
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090022#define CONFIG_SYS_TEXT_BASE 0xE6304000
Nobuhiro Iwamatsuc9b59bf72014-10-31 16:16:28 +090023#endif
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090024
Nobuhiro Iwamatsu1cc95f62015-10-10 05:58:28 +090025#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
Nobuhiro Iwamatsuc9b59bf72014-10-31 16:16:28 +090026#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC
27#else
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090028#define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC
Nobuhiro Iwamatsuc9b59bf72014-10-31 16:16:28 +090029#endif
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090030#define STACK_AREA_SIZE 0xC000
31#define LOW_LEVEL_MERAM_STACK \
32 (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
33
34/* MEMORY */
Nobuhiro Iwamatsu5ca6dfe2014-11-10 14:34:07 +090035#define RCAR_GEN2_SDRAM_BASE 0x40000000
36#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024)
37#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090038
39/* SCIF */
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090040
41/* FLASH */
42#define CONFIG_SPI
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090043#define CONFIG_SH_QSPI
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090044#define CONFIG_SPI_FLASH_QUAD
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090045
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090046/* SH Ether */
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090047#define CONFIG_SH_ETHER
48#define CONFIG_SH_ETHER_USE_PORT 0
49#define CONFIG_SH_ETHER_PHY_ADDR 0x1
50#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
51#define CONFIG_SH_ETHER_CACHE_WRITEBACK
52#define CONFIG_SH_ETHER_CACHE_INVALIDATE
53#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090054#define CONFIG_BITBANGMII
55#define CONFIG_BITBANGMII_MULTI
56
57/* Board Clock */
58#define RMOBILE_XTAL_CLK 20000000u
59#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
60#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
61#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2)
62#define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24)
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090063
64#define CONFIG_SYS_TMU_CLK_DIV 4
65
66/* i2c */
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090067#define CONFIG_SYS_I2C
68#define CONFIG_SYS_I2C_SH
69#define CONFIG_SYS_I2C_SLAVE 0x7F
70#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090071#define CONFIG_SYS_I2C_SH_SPEED0 400000
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090072#define CONFIG_SYS_I2C_SH_SPEED1 400000
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090073#define CONFIG_SYS_I2C_SH_SPEED2 400000
74#define CONFIG_SH_I2C_DATA_HIGH 4
75#define CONFIG_SH_I2C_DATA_LOW 5
76#define CONFIG_SH_I2C_CLOCK 10000000
77
78#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
79
Nobuhiro Iwamatsu7ffc8df2014-10-31 16:30:26 +090080/* USB */
Nobuhiro Iwamatsu7ffc8df2014-10-31 16:30:26 +090081#define CONFIG_USB_EHCI_RMOBILE
82#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
83
Nobuhiro Iwamatsu2b8c0812014-12-03 15:30:30 +090084/* MMCIF */
Nobuhiro Iwamatsu2b8c0812014-12-03 15:30:30 +090085#define CONFIG_SH_MMCIF
86#define CONFIG_SH_MMCIF_ADDR 0xee200000
87#define CONFIG_SH_MMCIF_CLK 48000000
88
Nobuhiro Iwamatsu8e2e5882014-12-02 16:52:24 +090089/* Module stop status bits */
90/* INTC-RT */
91#define CONFIG_SMSTP0_ENA 0x00400000
92/* MSIF */
93#define CONFIG_SMSTP2_ENA 0x00002000
94/* INTC-SYS, IRQC */
95#define CONFIG_SMSTP4_ENA 0x00000180
96/* SCIF2 */
97#define CONFIG_SMSTP7_ENA 0x00080000
98
Nobuhiro Iwamatsu25f96132014-11-19 14:26:33 +090099/* SDHI */
100#define CONFIG_SH_SDHI_FREQ 97500000
101
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +0900102#endif /* __ALT_H */