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Masahiro Yamada5894ca02014-10-03 19:21:06 +09001/*
Masahiro Yamadaf6e7f072015-05-29 17:30:00 +09002 * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada5894ca02014-10-03 19:21:06 +09003 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
Masahiro Yamadaf6e7f072015-05-29 17:30:00 +09007#include <linux/io.h>
Masahiro Yamadaa86ac952015-02-27 02:26:44 +09008#include <mach/bcu-regs.h>
Masahiro Yamada323d1f92015-09-22 00:27:39 +09009#include <mach/init.h>
Masahiro Yamada5894ca02014-10-03 19:21:06 +090010
11#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
12
Masahiro Yamada323d1f92015-09-22 00:27:39 +090013int ph1_ld4_bcu_init(const struct uniphier_board_data *bd)
Masahiro Yamada5894ca02014-10-03 19:21:06 +090014{
15 int shift;
16
17 writel(0x44444444, BCSCR0); /* 0x20000000-0x3fffffff: ASM bus */
18 writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */
19 writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */
20 writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */
21 writel(0x11111111, BCSCR5); /* 0xe0000000-0Xffffffff: IPPC/IPPD-bus */
22
23 /* Specify DDR channel */
Masahiro Yamada323d1f92015-09-22 00:27:39 +090024 shift = (bd->dram_ch1_base - bd->dram_ch0_base) / 0x04000000 * 4;
Masahiro Yamada5894ca02014-10-03 19:21:06 +090025 writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
26
27 shift -= 32;
28 writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */
29
30 shift -= 32;
31 writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */
Masahiro Yamada323d1f92015-09-22 00:27:39 +090032
33 return 0;
Masahiro Yamada5894ca02014-10-03 19:21:06 +090034}