Shengzhou Liu | 8d67c36 | 2014-03-05 15:04:48 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2014 Freescale Semiconductor |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | * |
| 6 | * Freescale T2080RDB board-specific CPLD controlling supports. |
| 7 | */ |
| 8 | |
| 9 | #include <common.h> |
| 10 | #include <command.h> |
| 11 | #include "cpld.h" |
| 12 | |
| 13 | u8 cpld_read(unsigned int reg) |
| 14 | { |
| 15 | void *p = (void *)CONFIG_SYS_CPLD_BASE; |
| 16 | |
| 17 | return in_8(p + reg); |
| 18 | } |
| 19 | |
| 20 | void cpld_write(unsigned int reg, u8 value) |
| 21 | { |
| 22 | void *p = (void *)CONFIG_SYS_CPLD_BASE; |
| 23 | |
| 24 | out_8(p + reg, value); |
| 25 | } |
| 26 | |
| 27 | /* Set the boot bank to the alternate bank */ |
| 28 | void cpld_set_altbank(void) |
| 29 | { |
| 30 | u8 reg = CPLD_READ(flash_csr); |
| 31 | |
| 32 | reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK; |
| 33 | CPLD_WRITE(flash_csr, reg); |
| 34 | CPLD_WRITE(reset_ctl, CPLD_LBMAP_RESET); |
| 35 | } |
| 36 | |
| 37 | /* Set the boot bank to the default bank */ |
| 38 | void cpld_set_defbank(void) |
| 39 | { |
| 40 | u8 reg = CPLD_READ(flash_csr); |
| 41 | |
| 42 | reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK; |
| 43 | CPLD_WRITE(flash_csr, reg); |
| 44 | CPLD_WRITE(reset_ctl, CPLD_LBMAP_RESET); |
| 45 | } |
| 46 | |
| 47 | int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
| 48 | { |
| 49 | int rc = 0; |
| 50 | |
| 51 | if (argc <= 1) |
| 52 | return cmd_usage(cmdtp); |
| 53 | |
| 54 | if (strcmp(argv[1], "reset") == 0) { |
| 55 | if (strcmp(argv[2], "altbank") == 0) |
| 56 | cpld_set_altbank(); |
| 57 | else |
| 58 | cpld_set_defbank(); |
| 59 | } else { |
| 60 | rc = cmd_usage(cmdtp); |
| 61 | } |
| 62 | |
| 63 | return rc; |
| 64 | } |
| 65 | |
| 66 | U_BOOT_CMD( |
| 67 | cpld, CONFIG_SYS_MAXARGS, 1, do_cpld, |
| 68 | "Reset the board or alternate bank", |
| 69 | "reset: reset to default bank\n" |
| 70 | "cpld reset altbank: reset to alternate bank\n" |
| 71 | ); |