blob: 4c637b7767354f56289cb5404e27a32f762b15fd [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Kever Yang6d1970f2017-06-23 16:11:05 +08002/*
3 * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
Kever Yang6d1970f2017-06-23 16:11:05 +08004 */
5
6#include <common.h>
7#include <dm.h>
Simon Glass67c4e9f2019-11-14 12:57:45 -07008#include <init.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -06009#include <log.h>
Kever Yang6d1970f2017-06-23 16:11:05 +080010#include <ram.h>
11#include <asm/io.h>
Kever Yang5d19ddf2019-11-15 11:04:33 +080012#include <asm/arch-rockchip/sdram.h>
Kever Yang6d1970f2017-06-23 16:11:05 +080013#include <dm/uclass-internal.h>
14
15DECLARE_GLOBAL_DATA_PTR;
Kever Yang5eb9a782019-07-22 20:02:02 +080016
17#define TRUST_PARAMETER_OFFSET (34 * 1024 * 1024)
18
19struct tos_parameter_t {
20 u32 version;
21 u32 checksum;
22 struct {
23 char name[8];
24 s64 phy_addr;
25 u32 size;
26 u32 flags;
27 } tee_mem;
28 struct {
29 char name[8];
30 s64 phy_addr;
31 u32 size;
32 u32 flags;
33 } drm_mem;
34 s64 reserve[8];
35};
36
37int dram_init_banksize(void)
38{
39 size_t top = min((unsigned long)(gd->ram_size + CONFIG_SYS_SDRAM_BASE),
40 gd->ram_top);
41
42#ifdef CONFIG_ARM64
43 /* Reserve 0x200000 for ATF bl31 */
44 gd->bd->bi_dram[0].start = 0x200000;
45 gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
46#else
47#ifdef CONFIG_SPL_OPTEE
48 struct tos_parameter_t *tos_parameter;
49
50 tos_parameter = (struct tos_parameter_t *)(CONFIG_SYS_SDRAM_BASE +
51 TRUST_PARAMETER_OFFSET);
52
53 if (tos_parameter->tee_mem.flags == 1) {
54 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
55 gd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr
56 - CONFIG_SYS_SDRAM_BASE;
57 gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr +
58 tos_parameter->tee_mem.size;
Alex Bee90f740a2020-07-15 01:03:31 +020059 gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start;
Kever Yang5eb9a782019-07-22 20:02:02 +080060 } else {
61 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
62 gd->bd->bi_dram[0].size = 0x8400000;
63 /* Reserve 32M for OPTEE with TA */
64 gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
65 + gd->bd->bi_dram[0].size + 0x2000000;
Alex Bee90f740a2020-07-15 01:03:31 +020066 gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start;
Kever Yang5eb9a782019-07-22 20:02:02 +080067 }
68#else
69 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
70 gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
71#endif
72#endif
73
74 return 0;
75}
76
Kever Yang6d1970f2017-06-23 16:11:05 +080077size_t rockchip_sdram_size(phys_addr_t reg)
78{
Kever Yang9a46f2a2019-11-15 11:04:35 +080079 u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4;
Kever Yang6d1970f2017-06-23 16:11:05 +080080 size_t chipsize_mb = 0;
81 size_t size_mb = 0;
82 u32 ch;
Kever Yang9a46f2a2019-11-15 11:04:35 +080083 u32 cs1_col = 0;
84 u32 bg = 0;
85 u32 dbw, dram_type;
Kever Yangc7becc32019-11-15 11:04:36 +080086 u32 sys_reg2 = readl(reg);
Kever Yang9a46f2a2019-11-15 11:04:35 +080087 u32 sys_reg3 = readl(reg + 4);
Kever Yangc7becc32019-11-15 11:04:36 +080088 u32 ch_num = 1 + ((sys_reg2 >> SYS_REG_NUM_CH_SHIFT)
Kever Yang6d1970f2017-06-23 16:11:05 +080089 & SYS_REG_NUM_CH_MASK);
90
Kever Yangc7becc32019-11-15 11:04:36 +080091 dram_type = (sys_reg2 >> SYS_REG_DDRTYPE_SHIFT) & SYS_REG_DDRTYPE_MASK;
92 debug("%s %x %x\n", __func__, (u32)reg, sys_reg2);
Kever Yang6d1970f2017-06-23 16:11:05 +080093 for (ch = 0; ch < ch_num; ch++) {
Kever Yangc7becc32019-11-15 11:04:36 +080094 rank = 1 + (sys_reg2 >> SYS_REG_RANK_SHIFT(ch) &
Kever Yang6d1970f2017-06-23 16:11:05 +080095 SYS_REG_RANK_MASK);
Kever Yangc7becc32019-11-15 11:04:36 +080096 cs0_col = 9 + (sys_reg2 >> SYS_REG_COL_SHIFT(ch) &
Kever Yang9a46f2a2019-11-15 11:04:35 +080097 SYS_REG_COL_MASK);
98 cs1_col = cs0_col;
Kever Yangc7becc32019-11-15 11:04:36 +080099 bk = 3 - ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
Kever Yang9a46f2a2019-11-15 11:04:35 +0800100 if ((sys_reg3 >> SYS_REG_VERSION_SHIFT &
101 SYS_REG_VERSION_MASK) == 0x2) {
102 cs1_col = 9 + (sys_reg3 >> SYS_REG_CS1_COL_SHIFT(ch) &
103 SYS_REG_CS1_COL_MASK);
104 if (((sys_reg3 >> SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) &
Kever Yangc7becc32019-11-15 11:04:36 +0800105 SYS_REG_EXTEND_CS0_ROW_MASK) << 2) + (sys_reg2 >>
Kever Yang9a46f2a2019-11-15 11:04:35 +0800106 SYS_REG_CS0_ROW_SHIFT(ch) &
107 SYS_REG_CS0_ROW_MASK) == 7)
108 cs0_row = 12;
109 else
Kever Yangc7becc32019-11-15 11:04:36 +0800110 cs0_row = 13 + (sys_reg2 >>
Kever Yang9a46f2a2019-11-15 11:04:35 +0800111 SYS_REG_CS0_ROW_SHIFT(ch) &
112 SYS_REG_CS0_ROW_MASK) +
113 ((sys_reg3 >>
114 SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) &
115 SYS_REG_EXTEND_CS0_ROW_MASK) << 2);
116 if (((sys_reg3 >> SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) &
Kever Yangc7becc32019-11-15 11:04:36 +0800117 SYS_REG_EXTEND_CS1_ROW_MASK) << 2) + (sys_reg2 >>
Kever Yang9a46f2a2019-11-15 11:04:35 +0800118 SYS_REG_CS1_ROW_SHIFT(ch) &
119 SYS_REG_CS1_ROW_MASK) == 7)
120 cs1_row = 12;
121 else
Kever Yangc7becc32019-11-15 11:04:36 +0800122 cs1_row = 13 + (sys_reg2 >>
Kever Yang9a46f2a2019-11-15 11:04:35 +0800123 SYS_REG_CS1_ROW_SHIFT(ch) &
124 SYS_REG_CS1_ROW_MASK) +
125 ((sys_reg3 >>
126 SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) &
127 SYS_REG_EXTEND_CS1_ROW_MASK) << 2);
128 } else {
Kever Yangc7becc32019-11-15 11:04:36 +0800129 cs0_row = 13 + (sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) &
Kever Yang6d1970f2017-06-23 16:11:05 +0800130 SYS_REG_CS0_ROW_MASK);
Kever Yangc7becc32019-11-15 11:04:36 +0800131 cs1_row = 13 + (sys_reg2 >> SYS_REG_CS1_ROW_SHIFT(ch) &
Kever Yang6d1970f2017-06-23 16:11:05 +0800132 SYS_REG_CS1_ROW_MASK);
Kever Yang9a46f2a2019-11-15 11:04:35 +0800133 }
Kever Yangc7becc32019-11-15 11:04:36 +0800134 bw = (2 >> ((sys_reg2 >> SYS_REG_BW_SHIFT(ch)) &
Kever Yang6d1970f2017-06-23 16:11:05 +0800135 SYS_REG_BW_MASK));
Kever Yangc7becc32019-11-15 11:04:36 +0800136 row_3_4 = sys_reg2 >> SYS_REG_ROW_3_4_SHIFT(ch) &
Kever Yang6d1970f2017-06-23 16:11:05 +0800137 SYS_REG_ROW_3_4_MASK;
Kever Yang9a46f2a2019-11-15 11:04:35 +0800138 if (dram_type == DDR4) {
Kever Yangc7becc32019-11-15 11:04:36 +0800139 dbw = (sys_reg2 >> SYS_REG_DBW_SHIFT(ch)) &
Kever Yang9a46f2a2019-11-15 11:04:35 +0800140 SYS_REG_DBW_MASK;
141 bg = (dbw == 2) ? 2 : 1;
142 }
143 chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20));
Kever Yang6d1970f2017-06-23 16:11:05 +0800144
145 if (rank > 1)
Kever Yang9a46f2a2019-11-15 11:04:35 +0800146 chipsize_mb += chipsize_mb >> ((cs0_row - cs1_row) +
147 (cs0_col - cs1_col));
Kever Yang6d1970f2017-06-23 16:11:05 +0800148 if (row_3_4)
149 chipsize_mb = chipsize_mb * 3 / 4;
150 size_mb += chipsize_mb;
Kever Yang9a46f2a2019-11-15 11:04:35 +0800151 if (rank > 1)
152 debug("rank %d cs0_col %d cs1_col %d bk %d cs0_row %d\
153 cs1_row %d bw %d row_3_4 %d\n",
154 rank, cs0_col, cs1_col, bk, cs0_row,
155 cs1_row, bw, row_3_4);
156 else
157 debug("rank %d cs0_col %d bk %d cs0_row %d\
158 bw %d row_3_4 %d\n",
159 rank, cs0_col, bk, cs0_row,
160 bw, row_3_4);
Kever Yang6d1970f2017-06-23 16:11:05 +0800161 }
162
Kever Yang3119ecc2018-12-28 09:56:48 +0800163 /*
164 * This is workaround for issue we can't get correct size for 4GB ram
165 * in 32bit system and available before we really need ram space
166 * out of 4GB, eg.enable ARM LAPE(rk3288 supports 8GB ram).
167 * The size of 4GB is '0x1 00000000', and this value will be truncated
168 * to 0 in 32bit system, and system can not get correct ram size.
169 * Rockchip SoCs reserve a blob of space for peripheral near 4GB,
170 * and we are now setting SDRAM_MAX_SIZE as max available space for
171 * ram in 4GB, so we can use this directly to workaround the issue.
172 * TODO:
173 * 1. update correct value for SDRAM_MAX_SIZE as what dram
174 * controller sees.
175 * 2. update board_get_usable_ram_top() and dram_init_banksize()
176 * to reserve memory for peripheral space after previous update.
177 */
178 if (size_mb > (SDRAM_MAX_SIZE >> 20))
179 size_mb = (SDRAM_MAX_SIZE >> 20);
180
Kever Yang6d1970f2017-06-23 16:11:05 +0800181 return (size_t)size_mb << 20;
182}
183
184int dram_init(void)
185{
186 struct ram_info ram;
187 struct udevice *dev;
188 int ret;
189
190 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
191 if (ret) {
192 debug("DRAM init failed: %d\n", ret);
193 return ret;
194 }
195 ret = ram_get_info(dev, &ram);
196 if (ret) {
197 debug("Cannot get DRAM size: %d\n", ret);
198 return ret;
199 }
200 gd->ram_size = ram.size;
201 debug("SDRAM base=%lx, size=%lx\n",
202 (unsigned long)ram.base, (unsigned long)ram.size);
203
204 return 0;
205}
206
207ulong board_get_usable_ram_top(ulong total_size)
208{
209 unsigned long top = CONFIG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE;
210
211 return (gd->ram_top > top) ? top : gd->ram_top;
212}