blob: cb982c2e74f6f9deeef3ad0fd5d32d4c72faf981 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Michal Simekdea4d2f2017-11-02 10:54:48 +01002/*
3 * (C) Copyright 2013 - 2017 Xilinx.
4 *
5 * Configuration settings for the Xilinx Zynq CSE board.
6 * See zynq-common.h for Zynq common configs
Michal Simekdea4d2f2017-11-02 10:54:48 +01007 */
8
9#ifndef __CONFIG_ZYNQ_CSE_H
10#define __CONFIG_ZYNQ_CSE_H
11
Michal Simekdea4d2f2017-11-02 10:54:48 +010012#include <configs/zynq-common.h>
13
14/* Undef unneeded configs */
15#undef CONFIG_EXTRA_ENV_SETTINGS
Michal Simekdea4d2f2017-11-02 10:54:48 +010016
Michal Simekdea4d2f2017-11-02 10:54:48 +010017#undef CONFIG_SYS_INIT_RAM_ADDR
18#undef CONFIG_SYS_INIT_RAM_SIZE
19#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFDE000
20#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
Michal Simekdea4d2f2017-11-02 10:54:48 +010021
Michal Simekdea4d2f2017-11-02 10:54:48 +010022#endif /* __CONFIG_ZYNQ_CSE_H */