Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Ian Campbell | cba69ee | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2012-2012 Henrik Nordstrom <henrik@henriknordstrom.net> |
| 4 | * |
| 5 | * (C) Copyright 2007-2011 |
| 6 | * Allwinner Technology Co., Ltd. <www.allwinnertech.com> |
| 7 | * Tom Cubie <tangliang@allwinnertech.com> |
| 8 | * |
| 9 | * Configuration settings for the Allwinner sunxi series of boards. |
Ian Campbell | cba69ee | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 10 | */ |
| 11 | |
| 12 | #ifndef _SUNXI_COMMON_CONFIG_H |
| 13 | #define _SUNXI_COMMON_CONFIG_H |
| 14 | |
Hans de Goede | daf6d39 | 2015-09-13 17:29:33 +0200 | [diff] [blame] | 15 | #include <asm/arch/cpu.h> |
Hans de Goede | e049fe2 | 2015-05-19 22:12:31 +0200 | [diff] [blame] | 16 | #include <linux/stringify.h> |
| 17 | |
Ian Campbell | cba69ee | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 18 | /* Serial & console */ |
Ian Campbell | cba69ee | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 19 | #define CONFIG_SYS_NS16550_SERIAL |
| 20 | /* ns16550 reg in the low bits of cpu reg */ |
Icenowy Zheng | 2c699fe | 2022-01-29 10:23:06 -0500 | [diff] [blame] | 21 | #ifdef CONFIG_MACH_SUNIV |
| 22 | /* suniv doesn't have apb2 and uart is connected to apb1 */ |
| 23 | #define CONFIG_SYS_NS16550_CLK 100000000 |
| 24 | #else |
Ian Campbell | cba69ee | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 25 | #define CONFIG_SYS_NS16550_CLK 24000000 |
Icenowy Zheng | 2c699fe | 2022-01-29 10:23:06 -0500 | [diff] [blame] | 26 | #endif |
Thomas Chou | 4fb6055 | 2015-11-19 21:48:13 +0800 | [diff] [blame] | 27 | #ifndef CONFIG_DM_SERIAL |
Simon Glass | 1a81cf83 | 2014-10-30 20:25:50 -0600 | [diff] [blame] | 28 | # define CONFIG_SYS_NS16550_REG_SIZE -4 |
| 29 | # define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE |
| 30 | # define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE |
| 31 | # define CONFIG_SYS_NS16550_COM3 SUNXI_UART2_BASE |
| 32 | # define CONFIG_SYS_NS16550_COM4 SUNXI_UART3_BASE |
| 33 | # define CONFIG_SYS_NS16550_COM5 SUNXI_R_UART_BASE |
| 34 | #endif |
Ian Campbell | cba69ee | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 35 | |
Paul Kocialkowski | 8a65f69 | 2015-05-16 19:52:11 +0200 | [diff] [blame] | 36 | /* CPU */ |
Paul Kocialkowski | 8a65f69 | 2015-05-16 19:52:11 +0200 | [diff] [blame] | 37 | |
Hans de Goede | e049fe2 | 2015-05-19 22:12:31 +0200 | [diff] [blame] | 38 | /* |
| 39 | * The DRAM Base differs between some models. We cannot use macros for the |
| 40 | * CONFIG_FOO defines which contain the DRAM base address since they end |
| 41 | * up unexpanded in include/autoconf.mk . |
| 42 | * |
| 43 | * So we have to have this #ifdef #else #endif block for these. |
| 44 | */ |
| 45 | #ifdef CONFIG_MACH_SUN9I |
| 46 | #define SDRAM_OFFSET(x) 0x2##x |
| 47 | #define CONFIG_SYS_SDRAM_BASE 0x20000000 |
Icenowy Zheng | 2c699fe | 2022-01-29 10:23:06 -0500 | [diff] [blame] | 48 | #elif defined(CONFIG_MACH_SUNIV) |
| 49 | #define SDRAM_OFFSET(x) 0x8##x |
| 50 | #define CONFIG_SYS_SDRAM_BASE 0x80000000 |
Hans de Goede | e049fe2 | 2015-05-19 22:12:31 +0200 | [diff] [blame] | 51 | #else |
| 52 | #define SDRAM_OFFSET(x) 0x4##x |
Ian Campbell | cba69ee | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 53 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 |
Icenowy Zheng | c199489 | 2017-04-08 15:30:12 +0800 | [diff] [blame] | 54 | /* V3s do not have enough memory to place code at 0x4a000000 */ |
Hans de Goede | e049fe2 | 2015-05-19 22:12:31 +0200 | [diff] [blame] | 55 | #endif |
| 56 | |
Hans de Goede | 77fe988 | 2015-05-20 15:27:16 +0200 | [diff] [blame] | 57 | /* |
| 58 | * The A80's A1 sram starts at 0x00010000 rather then at 0x00000000 and is |
| 59 | * slightly bigger. Note that it is possible to map the first 32 KiB of the |
| 60 | * A1 at 0x00000000 like with older SoCs by writing 0x16aa0001 to the |
| 61 | * undocumented 0x008000e0 SYS_CTRL register. Where the 16aa is a key and |
| 62 | * the 1 actually activates the mapping of the first 32 KiB to 0x00000000. |
Icenowy Zheng | cadc7c2 | 2018-07-21 16:20:20 +0800 | [diff] [blame] | 63 | * A64 and H5 also has SRAM A1 at 0x00010000, but no magic remap register |
| 64 | * is known yet. |
| 65 | * H6 has SRAM A1 at 0x00020000. |
Hans de Goede | 77fe988 | 2015-05-20 15:27:16 +0200 | [diff] [blame] | 66 | */ |
Icenowy Zheng | cadc7c2 | 2018-07-21 16:20:20 +0800 | [diff] [blame] | 67 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SUNXI_SRAM_ADDRESS |
| 68 | /* FIXME: this may be larger on some SoCs */ |
| 69 | #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */ |
Ian Campbell | cba69ee | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 70 | |
Ian Campbell | cba69ee | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 71 | #define PHYS_SDRAM_0 CONFIG_SYS_SDRAM_BASE |
| 72 | #define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */ |
| 73 | |
Hans de Goede | e526861 | 2015-08-16 14:48:22 +0200 | [diff] [blame] | 74 | #ifdef CONFIG_NAND_SUNXI |
Boris Brezillon | a0dfa88 | 2016-06-15 21:09:27 +0200 | [diff] [blame] | 75 | #define CONFIG_SYS_NAND_MAX_ECCPOS 1664 |
Boris Brezillon | 4ccae81 | 2016-06-15 21:09:23 +0200 | [diff] [blame] | 76 | #define CONFIG_SYS_MAX_NAND_DEVICE 8 |
Piotr Zierhoffer | 960caeb | 2015-07-23 14:33:03 +0200 | [diff] [blame] | 77 | #endif |
| 78 | |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 79 | /* mmc config */ |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 80 | #define CONFIG_MMC_SUNXI_SLOT 0 |
Maxime Ripard | fb1c43c | 2017-02-27 18:22:03 +0100 | [diff] [blame] | 81 | |
Emmanuel Vadot | ae042be | 2016-11-05 20:51:11 +0100 | [diff] [blame] | 82 | #define CONFIG_SYS_MMC_MAX_DEVICE 4 |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 83 | |
Ian Campbell | cba69ee | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 84 | /* |
| 85 | * Miscellaneous configurable options |
| 86 | */ |
Ian Campbell | cba69ee | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 87 | |
Ian Campbell | cba69ee | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 88 | /* standalone support */ |
Hans de Goede | e049fe2 | 2015-05-19 22:12:31 +0200 | [diff] [blame] | 89 | #define CONFIG_STANDALONE_LOAD_ADDR CONFIG_SYS_LOAD_ADDR |
Ian Campbell | cba69ee | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 90 | |
Ian Campbell | cba69ee | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 91 | /* FLASH and environment organization */ |
| 92 | |
Boris Brezillon | fa5e102 | 2015-07-27 16:21:26 +0200 | [diff] [blame] | 93 | #define CONFIG_SYS_MONITOR_LEN (768 << 10) /* 768 KiB */ |
Ian Campbell | cba69ee | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 94 | |
Icenowy Zheng | cadc7c2 | 2018-07-21 16:20:20 +0800 | [diff] [blame] | 95 | /* |
| 96 | * We cannot use expressions here, because expressions won't be evaluated in |
| 97 | * autoconf.mk. |
| 98 | */ |
| 99 | #if CONFIG_SUNXI_SRAM_ADDRESS == 0x10000 |
Andre Przywara | 54522c9 | 2017-04-26 01:32:42 +0100 | [diff] [blame] | 100 | #ifdef CONFIG_ARM64 |
| 101 | /* end of SRAM A2 for now, as SRAM A1 is pretty tight for an ARM64 build */ |
| 102 | #define LOW_LEVEL_SRAM_STACK 0x00054000 |
| 103 | #else |
Andre Przywara | bc613d8 | 2017-02-16 01:20:23 +0000 | [diff] [blame] | 104 | #define LOW_LEVEL_SRAM_STACK 0x00018000 |
Andre Przywara | 54522c9 | 2017-04-26 01:32:42 +0100 | [diff] [blame] | 105 | #endif /* !CONFIG_ARM64 */ |
Icenowy Zheng | e5715e7 | 2018-07-21 16:20:24 +0800 | [diff] [blame] | 106 | #elif CONFIG_SUNXI_SRAM_ADDRESS == 0x20000 |
Jernej Skrabec | 8ec293e | 2021-01-11 21:11:46 +0100 | [diff] [blame] | 107 | #ifdef CONFIG_MACH_SUN50I_H616 |
Jernej Skrabec | 8ec293e | 2021-01-11 21:11:46 +0100 | [diff] [blame] | 108 | #define LOW_LEVEL_SRAM_STACK 0x58000 |
| 109 | #else |
Icenowy Zheng | e5715e7 | 2018-07-21 16:20:24 +0800 | [diff] [blame] | 110 | /* end of SRAM A2 on H6 for now */ |
| 111 | #define LOW_LEVEL_SRAM_STACK 0x00118000 |
Jernej Skrabec | 8ec293e | 2021-01-11 21:11:46 +0100 | [diff] [blame] | 112 | #endif |
Siarhei Siamashka | d96ebc4 | 2016-03-29 17:29:10 +0200 | [diff] [blame] | 113 | #else |
Andre Przywara | bc613d8 | 2017-02-16 01:20:23 +0000 | [diff] [blame] | 114 | #define LOW_LEVEL_SRAM_STACK 0x00008000 /* End of sram */ |
Siarhei Siamashka | d96ebc4 | 2016-03-29 17:29:10 +0200 | [diff] [blame] | 115 | #endif |
Ian Campbell | 50827a5 | 2014-05-05 11:52:30 +0100 | [diff] [blame] | 116 | |
Hans de Goede | c26fb9d | 2014-06-09 11:37:00 +0200 | [diff] [blame] | 117 | /* Ethernet support */ |
Hans de Goede | c26fb9d | 2014-06-09 11:37:00 +0200 | [diff] [blame] | 118 | |
Andre Przywara | 671f9ad | 2016-05-04 22:15:32 +0100 | [diff] [blame] | 119 | #ifdef CONFIG_ARM64 |
| 120 | /* |
| 121 | * Boards seem to come with at least 512MB of DRAM. |
| 122 | * The kernel should go at 512K, which is the default text offset (that will |
| 123 | * be adjusted at runtime if needed). |
| 124 | * There is no compression for arm64 kernels (yet), so leave some space |
| 125 | * for really big kernels, say 256MB for now. |
| 126 | * Scripts, PXE and DTBs should go afterwards, leaving the rest for the initrd. |
Andre Przywara | 671f9ad | 2016-05-04 22:15:32 +0100 | [diff] [blame] | 127 | */ |
Jernej Skrabec | 17d6ece | 2021-03-23 21:27:31 +0100 | [diff] [blame] | 128 | #define BOOTM_SIZE __stringify(0xa000000) |
| 129 | #define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(0080000)) |
Arnaud Ferraris | 747c242 | 2021-02-20 13:14:15 +0100 | [diff] [blame] | 130 | #define KERNEL_COMP_ADDR_R __stringify(SDRAM_OFFSET(4000000)) |
| 131 | #define KERNEL_COMP_SIZE __stringify(0xb000000) |
Jernej Skrabec | 17d6ece | 2021-03-23 21:27:31 +0100 | [diff] [blame] | 132 | #define FDT_ADDR_R __stringify(SDRAM_OFFSET(FA00000)) |
| 133 | #define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(FC00000)) |
| 134 | #define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(FD00000)) |
| 135 | #define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(FE00000)) |
| 136 | #define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(FF00000)) |
Andre Przywara | 671f9ad | 2016-05-04 22:15:32 +0100 | [diff] [blame] | 137 | |
Andre Przywara | 1bf98bd | 2022-07-03 00:47:20 +0100 | [diff] [blame] | 138 | #elif (CONFIG_SUNXI_MINIMUM_DRAM_MB >= 256) |
| 139 | /* |
| 140 | * 160M RAM (256M minimum minus 64MB heap + 32MB for u-boot, stack, fb, etc. |
| 141 | * 32M uncompressed kernel, 16M compressed kernel, 1M fdt, |
| 142 | * 1M script, 1M pxe, 1M dt overlay and the ramdisk at the end. |
| 143 | */ |
| 144 | #define BOOTM_SIZE __stringify(0xa000000) |
| 145 | #define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(2000000)) |
| 146 | #define FDT_ADDR_R __stringify(SDRAM_OFFSET(3000000)) |
| 147 | #define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(3100000)) |
| 148 | #define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(3200000)) |
| 149 | #define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(3300000)) |
| 150 | #define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(3400000)) |
| 151 | |
| 152 | #elif (CONFIG_SUNXI_MINIMUM_DRAM_MB >= 64) |
Icenowy Zheng | c199489 | 2017-04-08 15:30:12 +0800 | [diff] [blame] | 153 | /* |
| 154 | * 64M RAM minus 2MB heap + 16MB for u-boot, stack, fb, etc. |
| 155 | * 16M uncompressed kernel, 8M compressed kernel, 1M fdt, |
Jernej Skrabec | 17d6ece | 2021-03-23 21:27:31 +0100 | [diff] [blame] | 156 | * 1M script, 1M pxe, 1M dt overlay and the ramdisk at the end. |
Icenowy Zheng | c199489 | 2017-04-08 15:30:12 +0800 | [diff] [blame] | 157 | */ |
Jernej Skrabec | 17d6ece | 2021-03-23 21:27:31 +0100 | [diff] [blame] | 158 | #define BOOTM_SIZE __stringify(0x2e00000) |
| 159 | #define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(1000000)) |
| 160 | #define FDT_ADDR_R __stringify(SDRAM_OFFSET(1800000)) |
| 161 | #define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(1900000)) |
| 162 | #define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(1A00000)) |
| 163 | #define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(1B00000)) |
| 164 | #define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(1C00000)) |
Icenowy Zheng | 2c699fe | 2022-01-29 10:23:06 -0500 | [diff] [blame] | 165 | |
Andre Przywara | 1bf98bd | 2022-07-03 00:47:20 +0100 | [diff] [blame] | 166 | #elif (CONFIG_SUNXI_MINIMUM_DRAM_MB >= 32) |
Icenowy Zheng | 2c699fe | 2022-01-29 10:23:06 -0500 | [diff] [blame] | 167 | /* |
Andre Przywara | c8b9ba4 | 2022-10-06 18:16:34 +0100 | [diff] [blame] | 168 | * 32M RAM minus 2.5MB for u-boot, heap, stack, etc. |
| 169 | * 16M uncompressed kernel, 7M compressed kernel, 128K fdt, 64K script, |
| 170 | * 128K DT overlay, 128K PXE and the ramdisk in the rest (max. 5MB) |
Icenowy Zheng | 2c699fe | 2022-01-29 10:23:06 -0500 | [diff] [blame] | 171 | */ |
| 172 | #define BOOTM_SIZE __stringify(0x1700000) |
Andre Przywara | c8b9ba4 | 2022-10-06 18:16:34 +0100 | [diff] [blame] | 173 | #define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(1000000)) |
| 174 | #define FDT_ADDR_R __stringify(SDRAM_OFFSET(1d50000)) |
| 175 | #define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(1d40000)) |
| 176 | #define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(1d00000)) |
| 177 | #define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(1d20000)) |
| 178 | #define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(1800000)) |
Icenowy Zheng | 2c699fe | 2022-01-29 10:23:06 -0500 | [diff] [blame] | 179 | |
| 180 | #else |
Andre Przywara | 1bf98bd | 2022-07-03 00:47:20 +0100 | [diff] [blame] | 181 | #error Need at least 32MB of DRAM. Please adjust load addresses. |
Andre Przywara | 671f9ad | 2016-05-04 22:15:32 +0100 | [diff] [blame] | 182 | #endif |
Siarhei Siamashka | 2a909c5 | 2015-10-25 06:44:46 +0200 | [diff] [blame] | 183 | |
Hans de Goede | 846e325 | 2014-08-01 09:37:58 +0200 | [diff] [blame] | 184 | #define MEM_LAYOUT_ENV_SETTINGS \ |
Icenowy Zheng | c199489 | 2017-04-08 15:30:12 +0800 | [diff] [blame] | 185 | "bootm_size=" BOOTM_SIZE "\0" \ |
Siarhei Siamashka | 2a909c5 | 2015-10-25 06:44:46 +0200 | [diff] [blame] | 186 | "kernel_addr_r=" KERNEL_ADDR_R "\0" \ |
| 187 | "fdt_addr_r=" FDT_ADDR_R "\0" \ |
| 188 | "scriptaddr=" SCRIPT_ADDR_R "\0" \ |
| 189 | "pxefile_addr_r=" PXEFILE_ADDR_R "\0" \ |
Jernej Skrabec | 17d6ece | 2021-03-23 21:27:31 +0100 | [diff] [blame] | 190 | "fdtoverlay_addr_r=" FDTOVERLAY_ADDR_R "\0" \ |
Siarhei Siamashka | 2a909c5 | 2015-10-25 06:44:46 +0200 | [diff] [blame] | 191 | "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" |
| 192 | |
Arnaud Ferraris | 747c242 | 2021-02-20 13:14:15 +0100 | [diff] [blame] | 193 | #ifdef CONFIG_ARM64 |
| 194 | |
| 195 | #define MEM_LAYOUT_ENV_EXTRA_SETTINGS \ |
| 196 | "kernel_comp_addr_r=" KERNEL_COMP_ADDR_R "\0" \ |
| 197 | "kernel_comp_size=" KERNEL_COMP_SIZE "\0" |
| 198 | |
| 199 | #else |
| 200 | |
| 201 | #define MEM_LAYOUT_ENV_EXTRA_SETTINGS "" |
| 202 | |
| 203 | #endif |
| 204 | |
Siarhei Siamashka | 2a909c5 | 2015-10-25 06:44:46 +0200 | [diff] [blame] | 205 | #define DFU_ALT_INFO_RAM \ |
| 206 | "dfu_alt_info_ram=" \ |
| 207 | "kernel ram " KERNEL_ADDR_R " 0x1000000;" \ |
| 208 | "fdt ram " FDT_ADDR_R " 0x100000;" \ |
| 209 | "ramdisk ram " RAMDISK_ADDR_R " 0x4000000\0" |
Hans de Goede | 846e325 | 2014-08-01 09:37:58 +0200 | [diff] [blame] | 210 | |
Chen-Yu Tsai | 41f8e9f | 2014-10-07 15:11:49 +0800 | [diff] [blame] | 211 | #ifdef CONFIG_MMC |
Karsten Merker | 5a37a40 | 2015-12-16 20:59:40 +0100 | [diff] [blame] | 212 | #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1 |
Maxime Ripard | de86fc3 | 2017-08-23 10:12:22 +0200 | [diff] [blame] | 213 | #define BOOTENV_DEV_MMC_AUTO(devtypeu, devtypel, instance) \ |
| 214 | BOOTENV_DEV_MMC(MMC, mmc, 0) \ |
| 215 | BOOTENV_DEV_MMC(MMC, mmc, 1) \ |
| 216 | "bootcmd_mmc_auto=" \ |
| 217 | "if test ${mmc_bootdev} -eq 1; then " \ |
| 218 | "run bootcmd_mmc1; " \ |
| 219 | "run bootcmd_mmc0; " \ |
| 220 | "elif test ${mmc_bootdev} -eq 0; then " \ |
| 221 | "run bootcmd_mmc0; " \ |
| 222 | "run bootcmd_mmc1; " \ |
| 223 | "fi\0" |
| 224 | |
| 225 | #define BOOTENV_DEV_NAME_MMC_AUTO(devtypeu, devtypel, instance) \ |
| 226 | "mmc_auto " |
| 227 | |
| 228 | #define BOOT_TARGET_DEVICES_MMC(func) func(MMC_AUTO, mmc_auto, na) |
Karsten Merker | 5a37a40 | 2015-12-16 20:59:40 +0100 | [diff] [blame] | 229 | #else |
Maxime Ripard | de86fc3 | 2017-08-23 10:12:22 +0200 | [diff] [blame] | 230 | #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) |
Karsten Merker | 5a37a40 | 2015-12-16 20:59:40 +0100 | [diff] [blame] | 231 | #endif |
Chen-Yu Tsai | 41f8e9f | 2014-10-07 15:11:49 +0800 | [diff] [blame] | 232 | #else |
| 233 | #define BOOT_TARGET_DEVICES_MMC(func) |
| 234 | #endif |
| 235 | |
Hans de Goede | 2ec3a61 | 2014-07-31 23:04:45 +0200 | [diff] [blame] | 236 | #ifdef CONFIG_AHCI |
| 237 | #define BOOT_TARGET_DEVICES_SCSI(func) func(SCSI, scsi, 0) |
| 238 | #else |
| 239 | #define BOOT_TARGET_DEVICES_SCSI(func) |
| 240 | #endif |
| 241 | |
Paul Kocialkowski | 2582ca0 | 2015-08-04 17:04:09 +0200 | [diff] [blame] | 242 | #ifdef CONFIG_USB_STORAGE |
Chen-Yu Tsai | 859b3f1 | 2014-10-03 20:16:22 +0800 | [diff] [blame] | 243 | #define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) |
| 244 | #else |
| 245 | #define BOOT_TARGET_DEVICES_USB(func) |
| 246 | #endif |
| 247 | |
Ondrej Jirman | 0eabec1 | 2019-02-13 18:50:36 +0100 | [diff] [blame] | 248 | #ifdef CONFIG_CMD_PXE |
| 249 | #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) |
| 250 | #else |
| 251 | #define BOOT_TARGET_DEVICES_PXE(func) |
| 252 | #endif |
| 253 | |
| 254 | #ifdef CONFIG_CMD_DHCP |
| 255 | #define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na) |
| 256 | #else |
| 257 | #define BOOT_TARGET_DEVICES_DHCP(func) |
| 258 | #endif |
| 259 | |
Bernhard Nortmann | f3b589c | 2015-09-17 18:52:53 +0200 | [diff] [blame] | 260 | /* FEL boot support, auto-execute boot.scr if a script address was provided */ |
| 261 | #define BOOTENV_DEV_FEL(devtypeu, devtypel, instance) \ |
| 262 | "bootcmd_fel=" \ |
| 263 | "if test -n ${fel_booted} && test -n ${fel_scriptaddr}; then " \ |
| 264 | "echo '(FEL boot)'; " \ |
| 265 | "source ${fel_scriptaddr}; " \ |
| 266 | "fi\0" |
| 267 | #define BOOTENV_DEV_NAME_FEL(devtypeu, devtypel, instance) \ |
| 268 | "fel " |
| 269 | |
Hans de Goede | 2ec3a61 | 2014-07-31 23:04:45 +0200 | [diff] [blame] | 270 | #define BOOT_TARGET_DEVICES(func) \ |
Bernhard Nortmann | f3b589c | 2015-09-17 18:52:53 +0200 | [diff] [blame] | 271 | func(FEL, fel, na) \ |
Chen-Yu Tsai | 41f8e9f | 2014-10-07 15:11:49 +0800 | [diff] [blame] | 272 | BOOT_TARGET_DEVICES_MMC(func) \ |
Hans de Goede | 2ec3a61 | 2014-07-31 23:04:45 +0200 | [diff] [blame] | 273 | BOOT_TARGET_DEVICES_SCSI(func) \ |
Chen-Yu Tsai | 859b3f1 | 2014-10-03 20:16:22 +0800 | [diff] [blame] | 274 | BOOT_TARGET_DEVICES_USB(func) \ |
Ondrej Jirman | 0eabec1 | 2019-02-13 18:50:36 +0100 | [diff] [blame] | 275 | BOOT_TARGET_DEVICES_PXE(func) \ |
| 276 | BOOT_TARGET_DEVICES_DHCP(func) |
Hans de Goede | 2ec3a61 | 2014-07-31 23:04:45 +0200 | [diff] [blame] | 277 | |
Hans de Goede | 3b82402 | 2015-10-09 17:11:15 +0100 | [diff] [blame] | 278 | #ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT |
| 279 | #define BOOTCMD_SUNXI_COMPAT \ |
| 280 | "bootcmd_sunxi_compat=" \ |
| 281 | "setenv root /dev/mmcblk0p3 rootwait; " \ |
| 282 | "if ext2load mmc 0 0x44000000 uEnv.txt; then " \ |
| 283 | "echo Loaded environment from uEnv.txt; " \ |
| 284 | "env import -t 0x44000000 ${filesize}; " \ |
| 285 | "fi; " \ |
| 286 | "setenv bootargs console=${console} root=${root} ${extraargs}; " \ |
| 287 | "ext2load mmc 0 0x43000000 script.bin && " \ |
| 288 | "ext2load mmc 0 0x48000000 uImage && " \ |
| 289 | "bootm 0x48000000\0" |
| 290 | #else |
| 291 | #define BOOTCMD_SUNXI_COMPAT |
| 292 | #endif |
| 293 | |
Hans de Goede | 2ec3a61 | 2014-07-31 23:04:45 +0200 | [diff] [blame] | 294 | #include <config_distro_bootcmd.h> |
| 295 | |
Hans de Goede | 86b4909 | 2014-09-18 21:03:34 +0200 | [diff] [blame] | 296 | #ifdef CONFIG_USB_KEYBOARD |
| 297 | #define CONSOLE_STDIN_SETTINGS \ |
Hans de Goede | 86b4909 | 2014-09-18 21:03:34 +0200 | [diff] [blame] | 298 | "stdin=serial,usbkbd\0" |
| 299 | #else |
Luc Verhaegen | 7f2c521 | 2014-08-13 07:55:06 +0200 | [diff] [blame] | 300 | #define CONSOLE_STDIN_SETTINGS \ |
| 301 | "stdin=serial\0" |
Hans de Goede | 86b4909 | 2014-09-18 21:03:34 +0200 | [diff] [blame] | 302 | #endif |
Luc Verhaegen | 7f2c521 | 2014-08-13 07:55:06 +0200 | [diff] [blame] | 303 | |
Jagan Teki | 5d23532 | 2021-02-22 00:12:34 +0000 | [diff] [blame] | 304 | #ifdef CONFIG_DM_VIDEO |
Jernej Skrabec | 5600945 | 2017-03-27 19:22:32 +0200 | [diff] [blame] | 305 | #define CONSOLE_STDOUT_SETTINGS \ |
| 306 | "stdout=serial,vidconsole\0" \ |
| 307 | "stderr=serial,vidconsole\0" |
Luc Verhaegen | 7f2c521 | 2014-08-13 07:55:06 +0200 | [diff] [blame] | 308 | #else |
| 309 | #define CONSOLE_STDOUT_SETTINGS \ |
| 310 | "stdout=serial\0" \ |
| 311 | "stderr=serial\0" |
| 312 | #endif |
| 313 | |
Maxime Ripard | c53654f | 2017-11-14 21:24:00 +0100 | [diff] [blame] | 314 | #define PARTS_DEFAULT \ |
| 315 | "name=loader1,start=8k,size=32k,uuid=${uuid_gpt_loader1};" \ |
| 316 | "name=loader2,size=984k,uuid=${uuid_gpt_loader2};" \ |
| 317 | "name=esp,size=128M,bootable,uuid=${uuid_gpt_esp};" \ |
| 318 | "name=system,size=-,uuid=${uuid_gpt_system};" |
| 319 | |
| 320 | #define UUID_GPT_ESP "c12a7328-f81f-11d2-ba4b-00a0c93ec93b" |
| 321 | |
| 322 | #ifdef CONFIG_ARM64 |
| 323 | #define UUID_GPT_SYSTEM "b921b045-1df0-41c3-af44-4c6f280d3fae" |
| 324 | #else |
| 325 | #define UUID_GPT_SYSTEM "69dad710-2ce4-4e3c-b16c-21a1d49abed3" |
| 326 | #endif |
| 327 | |
Luc Verhaegen | 7f2c521 | 2014-08-13 07:55:06 +0200 | [diff] [blame] | 328 | #define CONSOLE_ENV_SETTINGS \ |
| 329 | CONSOLE_STDIN_SETTINGS \ |
| 330 | CONSOLE_STDOUT_SETTINGS |
| 331 | |
Andreas Färber | 2eff3b7 | 2017-04-14 18:44:47 +0200 | [diff] [blame] | 332 | #ifdef CONFIG_ARM64 |
| 333 | #define FDTFILE "allwinner/" CONFIG_DEFAULT_DEVICE_TREE ".dtb" |
| 334 | #else |
| 335 | #define FDTFILE CONFIG_DEFAULT_DEVICE_TREE ".dtb" |
| 336 | #endif |
| 337 | |
Hans de Goede | 2ec3a61 | 2014-07-31 23:04:45 +0200 | [diff] [blame] | 338 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
Luc Verhaegen | 7f2c521 | 2014-08-13 07:55:06 +0200 | [diff] [blame] | 339 | CONSOLE_ENV_SETTINGS \ |
Hans de Goede | 846e325 | 2014-08-01 09:37:58 +0200 | [diff] [blame] | 340 | MEM_LAYOUT_ENV_SETTINGS \ |
Arnaud Ferraris | 747c242 | 2021-02-20 13:14:15 +0100 | [diff] [blame] | 341 | MEM_LAYOUT_ENV_EXTRA_SETTINGS \ |
Siarhei Siamashka | 2a909c5 | 2015-10-25 06:44:46 +0200 | [diff] [blame] | 342 | DFU_ALT_INFO_RAM \ |
Andreas Färber | 2eff3b7 | 2017-04-14 18:44:47 +0200 | [diff] [blame] | 343 | "fdtfile=" FDTFILE "\0" \ |
Hans de Goede | 846e325 | 2014-08-01 09:37:58 +0200 | [diff] [blame] | 344 | "console=ttyS0,115200\0" \ |
Maxime Ripard | c53654f | 2017-11-14 21:24:00 +0100 | [diff] [blame] | 345 | "uuid_gpt_esp=" UUID_GPT_ESP "\0" \ |
| 346 | "uuid_gpt_system=" UUID_GPT_SYSTEM "\0" \ |
| 347 | "partitions=" PARTS_DEFAULT "\0" \ |
Hans de Goede | 3b82402 | 2015-10-09 17:11:15 +0100 | [diff] [blame] | 348 | BOOTCMD_SUNXI_COMPAT \ |
Hans de Goede | 2ec3a61 | 2014-07-31 23:04:45 +0200 | [diff] [blame] | 349 | BOOTENV |
| 350 | |
Ian Campbell | cba69ee | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 351 | #endif /* _SUNXI_COMMON_CONFIG_H */ |