Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Prabhakar Kushwaha | 9d044fc | 2016-06-03 18:41:34 +0530 | [diff] [blame] | 2 | /* |
| 3 | * Copyright 2016 Freescale Semiconductor, Inc. |
Yangbo Lu | 34f39ce | 2021-06-03 10:51:19 +0800 | [diff] [blame] | 4 | * Copyright 2021 NXP |
Prabhakar Kushwaha | 9d044fc | 2016-06-03 18:41:34 +0530 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __LS1012AQDS_H__ |
| 8 | #define __LS1012AQDS_H__ |
| 9 | |
| 10 | #include "ls1012a_common.h" |
| 11 | |
Shengzhou Liu | b9e745b | 2016-08-26 18:30:39 +0800 | [diff] [blame] | 12 | /* DDR */ |
Prabhakar Kushwaha | 9d044fc | 2016-06-03 18:41:34 +0530 | [diff] [blame] | 13 | #define CONFIG_SYS_SDRAM_SIZE 0x40000000 |
| 14 | |
Prabhakar Kushwaha | 9d044fc | 2016-06-03 18:41:34 +0530 | [diff] [blame] | 15 | /* |
| 16 | * QIXIS Definitions |
| 17 | */ |
Prabhakar Kushwaha | 9d044fc | 2016-06-03 18:41:34 +0530 | [diff] [blame] | 18 | |
| 19 | #ifdef CONFIG_FSL_QIXIS |
Prabhakar Kushwaha | 9d044fc | 2016-06-03 18:41:34 +0530 | [diff] [blame] | 20 | #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 |
| 21 | #define QIXIS_LBMAP_BRDCFG_REG 0x04 |
| 22 | #define QIXIS_LBMAP_SWITCH 6 |
Prabhakar Kushwaha | 3b4dbd3 | 2016-07-19 14:05:47 +0530 | [diff] [blame] | 23 | #define QIXIS_LBMAP_MASK 0x08 |
Prabhakar Kushwaha | 9d044fc | 2016-06-03 18:41:34 +0530 | [diff] [blame] | 24 | #define QIXIS_LBMAP_SHIFT 0 |
| 25 | #define QIXIS_LBMAP_DFLTBANK 0x00 |
| 26 | #define QIXIS_LBMAP_ALTBANK 0x08 |
Prabhakar Kushwaha | 3b4dbd3 | 2016-07-19 14:05:47 +0530 | [diff] [blame] | 27 | #define QIXIS_RST_CTL_RESET 0x31 |
Prabhakar Kushwaha | 9d044fc | 2016-06-03 18:41:34 +0530 | [diff] [blame] | 28 | #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 |
| 29 | #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 |
| 30 | #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 |
| 31 | #endif |
| 32 | |
| 33 | /* |
| 34 | * I2C bus multiplexer |
| 35 | */ |
| 36 | #define I2C_MUX_PCA_ADDR_PRI 0x77 |
| 37 | #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ |
| 38 | #define I2C_RETIMER_ADDR 0x18 |
| 39 | #define I2C_MUX_CH_DEFAULT 0x8 |
| 40 | #define I2C_MUX_CH_CH7301 0xC |
| 41 | #define I2C_MUX_CH5 0xD |
| 42 | #define I2C_MUX_CH7 0xF |
| 43 | |
| 44 | #define I2C_MUX_CH_VOL_MONITOR 0xa |
| 45 | |
| 46 | /* |
| 47 | * RTC configuration |
| 48 | */ |
| 49 | #define RTC |
Prabhakar Kushwaha | 9d044fc | 2016-06-03 18:41:34 +0530 | [diff] [blame] | 50 | #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ |
Prabhakar Kushwaha | 9d044fc | 2016-06-03 18:41:34 +0530 | [diff] [blame] | 51 | |
Prabhakar Kushwaha | 9d044fc | 2016-06-03 18:41:34 +0530 | [diff] [blame] | 52 | |
| 53 | /* Voltage monitor on channel 2*/ |
| 54 | #define I2C_VOL_MONITOR_ADDR 0x40 |
| 55 | #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 |
| 56 | #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 |
| 57 | #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 |
| 58 | |
Biwen Li | fc9a3d1 | 2020-10-26 16:52:36 +0800 | [diff] [blame] | 59 | #undef CONFIG_EXTRA_ENV_SETTINGS |
| 60 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 61 | "verify=no\0" \ |
Biwen Li | fc9a3d1 | 2020-10-26 16:52:36 +0800 | [diff] [blame] | 62 | "kernel_addr=0x01000000\0" \ |
| 63 | "kernelheader_addr=0x600000\0" \ |
| 64 | "scriptaddr=0x80000000\0" \ |
| 65 | "scripthdraddr=0x80080000\0" \ |
| 66 | "fdtheader_addr_r=0x80100000\0" \ |
| 67 | "kernelheader_addr_r=0x80200000\0" \ |
| 68 | "kernel_addr_r=0x96000000\0" \ |
| 69 | "fdt_addr_r=0x90000000\0" \ |
| 70 | "load_addr=0xa0000000\0" \ |
| 71 | "kernel_size=0x2800000\0" \ |
| 72 | "kernelheader_size=0x40000\0" \ |
| 73 | "console=ttyS0,115200\0" \ |
| 74 | BOOTENV \ |
| 75 | "boot_scripts=ls1012aqds_boot.scr\0" \ |
| 76 | "boot_script_hdr=hdr_ls1012aqds_bs.out\0" \ |
| 77 | "scan_dev_for_boot_part=" \ |
| 78 | "part list ${devtype} ${devnum} devplist; " \ |
| 79 | "env exists devplist || setenv devplist 1; " \ |
| 80 | "for distro_bootpart in ${devplist}; do " \ |
| 81 | "if fstype ${devtype} " \ |
| 82 | "${devnum}:${distro_bootpart} " \ |
| 83 | "bootfstype; then " \ |
| 84 | "run scan_dev_for_boot; " \ |
| 85 | "fi; " \ |
| 86 | "done\0" \ |
Biwen Li | fc9a3d1 | 2020-10-26 16:52:36 +0800 | [diff] [blame] | 87 | "boot_a_script=" \ |
| 88 | "load ${devtype} ${devnum}:${distro_bootpart} " \ |
| 89 | "${scriptaddr} ${prefix}${script}; " \ |
| 90 | "env exists secureboot && load ${devtype} " \ |
| 91 | "${devnum}:${distro_bootpart} " \ |
| 92 | "${scripthdraddr} ${prefix}${boot_script_hdr}; " \ |
| 93 | "env exists secureboot " \ |
| 94 | "&& esbc_validate ${scripthdraddr};" \ |
| 95 | "source ${scriptaddr}\0" \ |
Mian Yousaf Kaukab | 864c3db | 2021-04-14 12:33:58 +0200 | [diff] [blame] | 96 | "qspi_bootcmd=echo Trying load from qspi..;" \ |
Biwen Li | fc9a3d1 | 2020-10-26 16:52:36 +0800 | [diff] [blame] | 97 | "sf probe 0:0 && sf read $load_addr " \ |
| 98 | "$kernel_addr $kernel_size; env exists secureboot " \ |
| 99 | "&& sf read $kernelheader_addr_r $kernelheader_addr " \ |
| 100 | "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ |
| 101 | "bootm $load_addr#$board\0" |
| 102 | |
Biwen Li | fc9a3d1 | 2020-10-26 16:52:36 +0800 | [diff] [blame] | 103 | #ifdef CONFIG_TFABOOT |
| 104 | #undef QSPI_NOR_BOOTCOMMAND |
Mian Yousaf Kaukab | 864c3db | 2021-04-14 12:33:58 +0200 | [diff] [blame] | 105 | #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "\ |
Biwen Li | fc9a3d1 | 2020-10-26 16:52:36 +0800 | [diff] [blame] | 106 | "env exists secureboot && esbc_halt;" |
Biwen Li | fc9a3d1 | 2020-10-26 16:52:36 +0800 | [diff] [blame] | 107 | #endif |
| 108 | |
Rajesh Bhagat | e5141cb | 2018-11-05 18:02:59 +0000 | [diff] [blame] | 109 | #include <asm/fsl_secure_boot.h> |
Prabhakar Kushwaha | 9d044fc | 2016-06-03 18:41:34 +0530 | [diff] [blame] | 110 | #endif /* __LS1012AQDS_H__ */ |