Gitiles
Code Review Sign In
gerrit.cesnet.cz / github / trini / u-boot / 506f044131515a80c7c8479a84df028be880b34e / . / include / configs / TQM8260.h
blob: 3dd671471a519a685ba9fc7cc2a1145f93da9585 [file] [log] [blame]
wdenk0f8c9762002-08-19 11:57:05 +0000[diff] [blame]1/*
2 * (C) Copyright 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * Imported from global configuration:
33 * CONFIG_L2_CACHE
34 * CONFIG_266MHz
35 * CONFIG_300MHz
36 */
37
38/*
39 * High Level Configuration Options
40 * (easy to change)
41 */
42
43#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
44
45#if 0
46#define CONFIG_TQM8260 100 /* ...on a TQM8260 module Rev.100 */
47#else
48#define CONFIG_TQM8260 200 /* ...on a TQM8260 module Rev.200 */
49#endif
50
51/* Define 60x busmode only if your TQM8260 has L2 cache! */
52#ifdef CONFIG_L2_CACHE
53# define CONFIG_BUSMODE_60x 1 /* bus mode: 60x */
54#else
55# undef CONFIG_BUSMODE_60x /* bus mode: 8260 */
56#endif
57
58/* The board with 300MHz CPU doesn't have L2 cache, but works in 60x bus mode */
59#ifdef CONFIG_300MHz
60# define CONFIG_BUSMODE_60x
61#endif
62
63#define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */
64
65#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
66
67#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
68
69#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
70
71#undef CONFIG_BOOTARGS
wdenk506f0442003-03-28 14:40:36 +0000[diff] [blame^]72
73#define CONFIG_EXTRA_ENV_SETTINGS \
74 "nfsargs=setenv bootargs root=/dev/nfs rw " \
75 "nfsroot=$(serverip):$(rootpath)\0" \
76 "ramargs=setenv bootargs root=/dev/ram rw\0" \
77 "addip=setenv bootargs $(bootargs) " \
78 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
79 ":$(hostname):$(netdev):off panic=1\0" \
80 "flash_nfs=run nfsargs addip;" \
81 "bootm $(kernel_addr)\0" \
82 "flash_self=run ramargs addip;" \
83 "bootm $(kernel_addr) $(ramdisk_addr)\0" \
84 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
85 "rootpath=/opt/eldk/ppc_82xx\0" \
86 "bootfile=/tftpboot/TQM8260/uImage\0" \
87 "kernel_addr=40040000\0" \
88 "ramdisk_addr=40100000\0" \
89 ""
90#define CONFIG_BOOTCOMMAND "run flash_self"
wdenk0f8c9762002-08-19 11:57:05 +0000[diff] [blame]91
92/* enable I2C and select the hardware/software driver */
93#undef CONFIG_HARD_I2C /* I2C with hardware support */
94#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
95#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
96#define CFG_I2C_SLAVE 0x7F
97
98/*
99 * Software (bit-bang) I2C driver configuration
100 */
101
102/* TQM8260 Rev.100 has the clock and data pins swapped (!!!) on EEPROM */
103#if (CONFIG_TQM8260 <= 100)
104
105#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
106#define I2C_ACTIVE (iop->pdir |= 0x00020000)
107#define I2C_TRISTATE (iop->pdir &= ~0x00020000)
108#define I2C_READ ((iop->pdat & 0x00020000) != 0)
109#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00020000; \
110 else iop->pdat &= ~0x00020000
111#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00010000; \
112 else iop->pdat &= ~0x00010000
113#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
114
115#else
116
117#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
118#define I2C_ACTIVE (iop->pdir |= 0x00010000)
119#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
120#define I2C_READ ((iop->pdat & 0x00010000) != 0)
121#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
122 else iop->pdat &= ~0x00010000
123#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
124 else iop->pdat &= ~0x00020000
125#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
126#endif
127
128#define CFG_I2C_EEPROM_ADDR 0x50
129#define CFG_I2C_EEPROM_ADDR_LEN 2
130#define CFG_EEPROM_PAGE_WRITE_BITS 4
131#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
132
133#define CONFIG_I2C_X
134
135/*
136 * select serial console configuration
137 *
138 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
139 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
140 * for SCC).
141 *
142 * if CONFIG_CONS_NONE is defined, then the serial console routines must
143 * defined elsewhere (for example, on the cogent platform, there are serial
144 * ports on the motherboard which are used for the serial console - see
145 * cogent/cma101/serial.[ch]).
146 */
147#define CONFIG_CONS_ON_SMC /* define if console on SMC */
148#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
149#undef CONFIG_CONS_NONE /* define if console on something else*/
150#ifdef CONFIG_82xx_CONS_SMC1
151#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
152#endif
153#ifdef CONFIG_82xx_CONS_SMC2
154#define CONFIG_CONS_INDEX 2 /* which serial channel for console */
155#endif
156
157#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
158#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */
159#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */
160
161/*
162 * select ethernet configuration
163 *
164 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
165 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
166 * for FCC)
167 *
168 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
169 * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
170 * from CONFIG_COMMANDS to remove support for networking.
171 *
172 * (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
173 * X.29 connector, and FCC2 is hardwired to the X.1 connector)
174 */
175#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
176#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
177#undef CONFIG_ETHER_NONE /* define if ether on something else */
178#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
179
180#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
181
182/*
183 * - RX clk is CLK11
184 * - TX clk is CLK12
185 */
186# define CFG_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
187
188#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
189
190/*
191 * - Rx-CLK is CLK13
192 * - Tx-CLK is CLK14
193 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
194 * - Enable Full Duplex in FSMR
195 */
196# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
197# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
198# define CFG_CPMFCR_RAMTYPE 0
199# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
200
201#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
202
203
204/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
205#ifndef CONFIG_300MHz
206#define CONFIG_8260_CLKIN 66666666 /* in Hz */
207#else
208#define CONFIG_8260_CLKIN 83333000 /* in Hz */
209#endif
210
211#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
212#define CONFIG_BAUDRATE 230400
213#else
214#define CONFIG_BAUDRATE 9600
215#endif
216
217#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
218#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
219
220#undef CONFIG_WATCHDOG /* watchdog disabled */
221
222#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
223
224#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
225 CFG_CMD_I2C | \
226 CFG_CMD_EEPROM)
227
228/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
229#include <cmd_confdefs.h>
230
231/*
232 * Miscellaneous configurable options
233 */
234#define CFG_LONGHELP /* undef to save memory */
235#define CFG_PROMPT "=> " /* Monitor Command Prompt */
236#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
237#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
238#else
239#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
240#endif
241#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
242#define CFG_MAXARGS 16 /* max number of command args */
243#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
244
245#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
246#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
247
248#define CFG_LOAD_ADDR 0x100000 /* default load address */
249
250#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
251
252#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
253
254#define CFG_RESET_ADDRESS 0xFFFFFFFC /* "bad" address */
255
256/*
257 * For booting Linux, the board info and command line data
258 * have to be in the first 8 MB of memory, since this is
259 * the maximum mapped by the Linux kernel during initialization.
260 */
261#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
262
263
264/* What should the base address of the main FLASH be and how big is
265 * it (in MBytes)? This must contain TEXT_BASE from board/tqm8260/config.mk
266 * The main FLASH is whichever is connected to *CS0.
267 */
268#define CFG_FLASH0_BASE 0x40000000
269#define CFG_FLASH1_BASE 0x60000000
270#define CFG_FLASH0_SIZE 32
271#define CFG_FLASH1_SIZE 32
272
273/* Flash bank size (for preliminary settings)
274 */
275#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
276
277/*-----------------------------------------------------------------------
278 * FLASH organization
279 */
280#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
281#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
282
283#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
284#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
285
286#if 0
287/* Start port with environment in flash; switch to EEPROM later */
288#define CFG_ENV_IS_IN_FLASH 1
289#define CFG_ENV_ADDR (CFG_FLASH_BASE+0x40000)
290#define CFG_ENV_SIZE 0x40000
291#define CFG_ENV_SECT_SIZE 0x40000
292#else
293/* Final version: environment in EEPROM */
294#define CFG_ENV_IS_IN_EEPROM 1
295#define CFG_ENV_OFFSET 0
296#define CFG_ENV_SIZE 2048
297#endif
298
299/*-----------------------------------------------------------------------
300 * Hardware Information Block
301 */
302#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
303#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
304#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
305
306/*-----------------------------------------------------------------------
307 * Hard Reset Configuration Words
308 *
309 * if you change bits in the HRCW, you must also change the CFG_*
310 * defines for the various registers affected by the HRCW e.g. changing
311 * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
312 */
313#if defined(CONFIG_266MHz)
314#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \
315 HRCW_MODCK_H0111)
316#elif defined(CONFIG_300MHz)
317#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \
318 HRCW_MODCK_H0110)
319#else
320#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
321#endif
322
323/* no slaves so just fill with zeros */
324#define CFG_HRCW_SLAVE1 0
325#define CFG_HRCW_SLAVE2 0
326#define CFG_HRCW_SLAVE3 0
327#define CFG_HRCW_SLAVE4 0
328#define CFG_HRCW_SLAVE5 0
329#define CFG_HRCW_SLAVE6 0
330#define CFG_HRCW_SLAVE7 0
331
332/*-----------------------------------------------------------------------
333 * Internal Memory Mapped Register
334 */
335#define CFG_IMMR 0xFFF00000
336
337/*-----------------------------------------------------------------------
338 * Definitions for initial stack pointer and data area (in DPRAM)
339 */
340#define CFG_INIT_RAM_ADDR CFG_IMMR
341#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
342#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
343#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
344#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
345
346/*-----------------------------------------------------------------------
347 * Start addresses for the final memory configuration
348 * (Set up by the startup code)
349 * Please note that CFG_SDRAM_BASE _must_ start at 0
350 *
351 * 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM
352 * is mapped at SDRAM_BASE2_PRELIM.
353 */
354#define CFG_SDRAM_BASE 0x00000000
355#define CFG_FLASH_BASE CFG_FLASH0_BASE
356#define CFG_MONITOR_BASE TEXT_BASE
357#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
358#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
359
360/*
361 * Internal Definitions
362 *
363 * Boot Flags
364 */
365#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
366#define BOOTFLAG_WARM 0x02 /* Software reboot */
367
368
369/*-----------------------------------------------------------------------
370 * Cache Configuration
371 */
372#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
373#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
374# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
375#endif
376
377/*-----------------------------------------------------------------------
378 * HIDx - Hardware Implementation-dependent Registers 2-11
379 *-----------------------------------------------------------------------
380 * HID0 also contains cache control - initially enable both caches and
381 * invalidate contents, then the final state leaves only the instruction
382 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
383 * but Soft reset does not.
384 *
385 * HID1 has only read-only information - nothing to set.
386 */
387#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
388 HID0_IFEM|HID0_ABE)
389#define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE)
390#define CFG_HID2 0
391
392/*-----------------------------------------------------------------------
393 * RMR - Reset Mode Register 5-5
394 *-----------------------------------------------------------------------
395 * turn on Checkstop Reset Enable
396 */
397#define CFG_RMR RMR_CSRE
398
399/*-----------------------------------------------------------------------
400 * BCR - Bus Configuration 4-25
401 *-----------------------------------------------------------------------
402 */
403#ifdef CONFIG_BUSMODE_60x
404#define CFG_BCR (BCR_EBM|BCR_L2C|BCR_LETM|\
405 BCR_NPQM0|BCR_NPQM1|BCR_NPQM2) /* 60x mode */
406#else
407#define BCR_APD01 0x10000000
408#define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */
409#endif
410
411/*-----------------------------------------------------------------------
412 * SIUMCR - SIU Module Configuration 4-31
413 *-----------------------------------------------------------------------
414 */
415#if 0
416#define CFG_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10)
417#else
418#define CFG_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10)
419#endif
420
421
422/*-----------------------------------------------------------------------
423 * SYPCR - System Protection Control 4-35
424 * SYPCR can only be written once after reset!
425 *-----------------------------------------------------------------------
426 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
427 */
428#if defined(CONFIG_WATCHDOG)
429#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
430 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
431#else
432#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
433 SYPCR_SWRI|SYPCR_SWP)
434#endif /* CONFIG_WATCHDOG */
435
436/*-----------------------------------------------------------------------
437 * TMCNTSC - Time Counter Status and Control 4-40
438 *-----------------------------------------------------------------------
439 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
440 * and enable Time Counter
441 */
442#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
443
444/*-----------------------------------------------------------------------
445 * PISCR - Periodic Interrupt Status and Control 4-42
446 *-----------------------------------------------------------------------
447 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
448 * Periodic timer
449 */
450#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
451
452/*-----------------------------------------------------------------------
453 * SCCR - System Clock Control 9-8
454 *-----------------------------------------------------------------------
455 * Ensure DFBRG is Divide by 16
456 */
457#define CFG_SCCR 0
458
459/*-----------------------------------------------------------------------
460 * RCCR - RISC Controller Configuration 13-7
461 *-----------------------------------------------------------------------
462 */
463#define CFG_RCCR 0
464
465/*
466 * Init Memory Controller:
467 *
468 * Bank Bus Machine PortSz Device
469 * ---- --- ------- ------ ------
470 * 0 60x GPCM 64 bit FLASH
471 * 1 60x SDRAM 64 bit SDRAM
472 * 2 Local SDRAM 32 bit SDRAM
473 *
474 */
475
476 /* Initialize SDRAM on local bus
477 */
478#define CFG_INIT_LOCAL_SDRAM
479
480#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
481
482/* Minimum mask to separate preliminary
483 * address ranges for CS[0:2]
484 */
485#define CFG_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */
486#define CFG_LOCAL_SDRAM_LIMIT (128<<20) /* less than 128 MB */
487
488#define CFG_MPTPR 0x4000
489
490/*-----------------------------------------------------------------------------
491 * Address for Mode Register Set (MRS) command
492 *-----------------------------------------------------------------------------
493 * In fact, the address is rather configuration data presented to the SDRAM on
494 * its address lines. Because the address lines may be mux'ed externally either
495 * for 8 column or 9 column devices, some bits appear twice in the 8260's
496 * address:
497 *
498 * | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length |
499 * | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 |
500 * 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 |
501 * 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 |
502 * Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 |
503 *-----------------------------------------------------------------------------
504 */
505#define CFG_MRS_OFFS 0x00000110
506
507
508/* Bank 0 - FLASH
509 */
510#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
511 BRx_PS_64 |\
512 BRx_MS_GPCM_P |\
513 BRx_V)
514
515#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE) |\
516 ORxG_CSNT |\
517 ORxG_ACS_DIV1 |\
518 ORxG_SCY_3_CLK |\
519 ORxG_EHTR |\
520 ORxG_TRLX)
521
522 /* SDRAM on TQM8260 can have either 8 or 9 columns.
523 * The number affects configuration values.
524 */
525
526/* Bank 1 - 60x bus SDRAM
527 */
528#define CFG_PSRT 0x20
529#define CFG_LSRT 0x20
530#ifndef CFG_RAMBOOT
531#define CFG_BR1_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
532 BRx_PS_64 |\
533 BRx_MS_SDRAM_P |\
534 BRx_V)
535
536#define CFG_OR1_PRELIM CFG_OR1_8COL
537
538
539 /* SDRAM initialization values for 8-column chips
540 */
541#define CFG_OR1_8COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
542 ORxS_BPD_4 |\
543 ORxS_ROWST_PBI1_A7 |\
544 ORxS_NUMR_12)
545
546#define CFG_PSDMR_8COL (PSDMR_PBI |\
547 PSDMR_SDAM_A15_IS_A5 |\
548 PSDMR_BSMA_A12_A14 |\
549 PSDMR_SDA10_PBI1_A8 |\
550 PSDMR_RFRC_7_CLK |\
551 PSDMR_PRETOACT_2W |\
552 PSDMR_ACTTORW_2W |\
553 PSDMR_LDOTOPRE_1C |\
554 PSDMR_WRC_2C |\
555 PSDMR_EAMUX |\
556 PSDMR_CL_2)
557
558 /* SDRAM initialization values for 9-column chips
559 */
560#define CFG_OR1_9COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
561 ORxS_BPD_4 |\
562 ORxS_ROWST_PBI1_A5 |\
563 ORxS_NUMR_13)
564
565#define CFG_PSDMR_9COL (PSDMR_PBI |\
566 PSDMR_SDAM_A16_IS_A5 |\
567 PSDMR_BSMA_A12_A14 |\
568 PSDMR_SDA10_PBI1_A7 |\
569 PSDMR_RFRC_7_CLK |\
570 PSDMR_PRETOACT_2W |\
571 PSDMR_ACTTORW_2W |\
572 PSDMR_LDOTOPRE_1C |\
573 PSDMR_WRC_2C |\
574 PSDMR_EAMUX |\
575 PSDMR_CL_2)
576
577/* Bank 2 - Local bus SDRAM
578 */
579#ifdef CFG_INIT_LOCAL_SDRAM
580#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\
581 BRx_PS_32 |\
582 BRx_MS_SDRAM_L |\
583 BRx_V)
584
585#define CFG_OR2_PRELIM CFG_OR2_8COL
586
587#define SDRAM_BASE2_PRELIM 0x80000000
588
589 /* SDRAM initialization values for 8-column chips
590 */
591#define CFG_OR2_8COL ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
592 ORxS_BPD_4 |\
593 ORxS_ROWST_PBI1_A8 |\
594 ORxS_NUMR_12)
595
596#define CFG_LSDMR_8COL (PSDMR_PBI |\
597 PSDMR_SDAM_A15_IS_A5 |\
598 PSDMR_BSMA_A13_A15 |\
599 PSDMR_SDA10_PBI1_A9 |\
600 PSDMR_RFRC_7_CLK |\
601 PSDMR_PRETOACT_2W |\
602 PSDMR_ACTTORW_2W |\
603 PSDMR_BL |\
604 PSDMR_LDOTOPRE_1C |\
605 PSDMR_WRC_2C |\
606 PSDMR_CL_2)
607
608 /* SDRAM initialization values for 9-column chips
609 */
610#define CFG_OR2_9COL ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
611 ORxS_BPD_4 |\
612 ORxS_ROWST_PBI1_A6 |\
613 ORxS_NUMR_13)
614
615#define CFG_LSDMR_9COL (PSDMR_PBI |\
616 PSDMR_SDAM_A16_IS_A5 |\
617 PSDMR_BSMA_A13_A15 |\
618 PSDMR_SDA10_PBI1_A8 |\
619 PSDMR_RFRC_7_CLK |\
620 PSDMR_PRETOACT_2W |\
621 PSDMR_ACTTORW_2W |\
622 PSDMR_BL |\
623 PSDMR_LDOTOPRE_1C |\
624 PSDMR_WRC_2C |\
625 PSDMR_CL_2)
626
627#endif /* CFG_INIT_LOCAL_SDRAM */
628
629#endif /* CFG_RAMBOOT */
630
631#endif /* __CONFIG_H */