Gitiles
Code Review Sign In
gerrit.cesnet.cz / github / trini / u-boot / 4fb25a3db3b3839094aa9ab748efd7a95924690b / . / include / asm-ppc / ppc4xx-uic.h
blob: 1573b1eab184ab61c1a673f021de123c61234cef [file] [log] [blame]
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]1/*
Stefan Roese4fb25a32008-06-25 10:59:22 +0200[diff] [blame^]2 * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]3 *
Stefan Roese4fb25a32008-06-25 10:59:22 +0200[diff] [blame^]4 * (C) Copyright 2008
5 * Stefan Roese, DENX Software Engineering, sr@denx.de.
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]6 *
Stefan Roese4fb25a32008-06-25 10:59:22 +0200[diff] [blame^]7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]24 */
25
Stefan Roese4fb25a32008-06-25 10:59:22 +0200[diff] [blame^]26#ifndef _PPC4xx_UIC_H_
27#define _PPC4xx_UIC_H_
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]28
Stefan Roese854bc8d2006-09-13 13:51:58 +0200[diff] [blame]29#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]30
31/* UIC 0 */
32#define VECNUM_U0 0 /* UART 0 */
33#define VECNUM_U1 1 /* UART 1 */
34#define VECNUM_IIC0 2 /* IIC */
35#define VECNUM_KRD 3 /* Kasumi Ready for data */
36#define VECNUM_KDA 4 /* Kasumi Data Available */
37#define VECNUM_PCRW 5 /* PCI command register write */
38#define VECNUM_PPM 6 /* PCI power management */
39#define VECNUM_IIC1 7 /* IIC */
40#define VECNUM_SPI 8 /* SPI */
41#define VECNUM_EPCISER 9 /* External PCI SERR */
42#define VECNUM_MTE 10 /* MAL TXEOB */
43#define VECNUM_MRE 11 /* MAL RXEOB */
44#define VECNUM_D0 12 /* DMA channel 0 */
45#define VECNUM_D1 13 /* DMA channel 1 */
46#define VECNUM_D2 14 /* DMA channel 2 */
47#define VECNUM_D3 15 /* DMA channel 3 */
48#define VECNUM_UD0 16 /* UDMA irq 0 */
49#define VECNUM_UD1 17 /* UDMA irq 1 */
50#define VECNUM_UD2 18 /* UDMA irq 2 */
51#define VECNUM_UD3 19 /* UDMA irq 3 */
52#define VECNUM_HSB2D 20 /* USB2.0 Device */
53#define VECNUM_USBDEV 20 /* USB 1.1/USB 2.0 Device */
54#define VECNUM_OHCI1 21 /* USB2.0 Host OHCI irq 1 */
55#define VECNUM_OHCI2 22 /* USB2.0 Host OHCI irq 2 */
56#define VECNUM_EIP94 23 /* Security EIP94 */
57#define VECNUM_ETH0 24 /* Emac 0 */
58#define VECNUM_ETH1 25 /* Emac 1 */
59#define VECNUM_EHCI 26 /* USB2.0 Host EHCI */
60#define VECNUM_EIR4 27 /* External interrupt 4 */
61#define VECNUM_UIC2NC 28 /* UIC2 non-critical interrupt */
62#define VECNUM_UIC2C 29 /* UIC2 critical interrupt */
63#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */
64#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */
65
66/* UIC 1 */
67#define VECNUM_MS (32 + 0) /* MAL SERR */
68#define VECNUM_MTDE (32 + 1) /* MAL TXDE */
69#define VECNUM_MRDE (32 + 2) /* MAL RXDE */
70#define VECNUM_U2 (32 + 3) /* UART 2 */
71#define VECNUM_U3 (32 + 4) /* UART 3 */
72#define VECNUM_EBCO (32 + 5) /* EBCO interrupt status */
73#define VECNUM_NDFC (32 + 6) /* NDFC */
74#define VECNUM_KSLE (32 + 7) /* KASUMI slave error */
75#define VECNUM_CT5 (32 + 8) /* GPT compare timer 5 */
76#define VECNUM_CT6 (32 + 9) /* GPT compare timer 6 */
77#define VECNUM_PLB34I0 (32 + 10) /* PLB3X4X MIRQ0 */
78#define VECNUM_PLB34I1 (32 + 11) /* PLB3X4X MIRQ1 */
79#define VECNUM_PLB34I2 (32 + 12) /* PLB3X4X MIRQ2 */
80#define VECNUM_PLB34I3 (32 + 13) /* PLB3X4X MIRQ3 */
81#define VECNUM_PLB34I4 (32 + 14) /* PLB3X4X MIRQ4 */
82#define VECNUM_PLB34I5 (32 + 15) /* PLB3X4X MIRQ5 */
83#define VECNUM_CT0 (32 + 16) /* GPT compare timer 0 */
84#define VECNUM_CT1 (32 + 17) /* GPT compare timer 1 */
85#define VECNUM_EIR7 (32 + 18) /* External interrupt 7 */
86#define VECNUM_EIR8 (32 + 19) /* External interrupt 8 */
87#define VECNUM_EIR9 (32 + 20) /* External interrupt 9 */
88#define VECNUM_CT2 (32 + 21) /* GPT compare timer 2 */
89#define VECNUM_CT3 (32 + 22) /* GPT compare timer 3 */
90#define VECNUM_CT4 (32 + 23) /* GPT compare timer 4 */
91#define VECNUM_SRE (32 + 24) /* Serial ROM error */
92#define VECNUM_GPTDC (32 + 25) /* GPT decrementer pulse */
93#define VECNUM_RSVD0 (32 + 26) /* Reserved */
94#define VECNUM_EPCIPER (32 + 27) /* External PCI PERR */
95#define VECNUM_EIR0 (32 + 28) /* External interrupt 0 */
96#define VECNUM_EWU0 (32 + 29) /* Ethernet 0 wakeup */
97#define VECNUM_EIR1 (32 + 30) /* External interrupt 1 */
98#define VECNUM_EWU1 (32 + 31) /* Ethernet 1 wakeup */
99
100#define VECNUM_TXDE VECNUM_MTDE
101#define VECNUM_RXDE VECNUM_MRDE
102
103/* UIC 2 */
Matthias Fuchs580d1d32008-01-08 15:39:01 +0100[diff] [blame]104#define VECNUM_EIR5 (64 + 0) /* External interrupt 5 */
105#define VECNUM_EIR6 (64 + 1) /* External interrupt 6 */
106#define VECNUM_OPB (64 + 2) /* OPB to PLB bridge int stat */
107#define VECNUM_EIR2 (64 + 3) /* External interrupt 2 */
108#define VECNUM_EIR3 (64 + 4) /* External interrupt 3 */
109#define VECNUM_DDR2 (64 + 5) /* DDR2 sdram */
110#define VECNUM_MCTX0 (64 + 6) /* MAl intp coalescence TX0 */
111#define VECNUM_MCTX1 (64 + 7) /* MAl intp coalescence TX1 */
112#define VECNUM_MCTR0 (64 + 8) /* MAl intp coalescence TR0 */
113#define VECNUM_MCTR1 (64 + 9) /* MAl intp coalescence TR1 */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]114
Stefan Roese999ecd52008-03-11 15:07:10 +0100[diff] [blame]115#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
116
117/* UIC 0 */
118#define VECNUM_U1 1 /* UART1 */
119#define VECNUM_IIC0 2 /* IIC0 */
120#define VECNUM_IIC1 3 /* IIC1 */
121#define VECNUM_PIM 4 /* PCI inbound message */
122#define VECNUM_PCRW 5 /* PCI command reg write */
123#define VECNUM_PPM 6 /* PCI power management */
124#define VECNUM_MSI0 8 /* PCI MSI level 0 */
125#define VECNUM_EIR0 9 /* External interrupt 0 */
126#define VECNUM_UIC2NC 10 /* UIC2 non-critical interrupt */
127#define VECNUM_UIC2C 11 /* UIC2 critical interrupt */
128#define VECNUM_D0 12 /* DMA channel 0 */
129#define VECNUM_D1 13 /* DMA channel 1 */
130#define VECNUM_D2 14 /* DMA channel 2 */
131#define VECNUM_D3 15 /* DMA channel 3 */
132#define VECNUM_UIC3NC 16 /* UIC3 non-critical interrupt */
133#define VECNUM_UIC3C 17 /* UIC3 critical interrupt */
134#define VECNUM_EIR1 9 /* External interrupt 1 */
135#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */
136#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */
137
138/* UIC 1 */
139#define VECNUM_EIR2 (32 + 0) /* External interrupt 0 */
140#define VECNUM_U0 (32 + 1) /* UART0 */
141#define VECNUM_EIR3 (32 + 20) /* External interrupt 3 */
142#define VECNUM_EIR4 (32 + 21) /* External interrupt 4 */
143#define VECNUM_EIR5 (32 + 26) /* External interrupt 5 */
144#define VECNUM_EIR6 (32 + 27) /* External interrupt 6 */
145#define VECNUM_U2 (32 + 28) /* UART2 */
146#define VECNUM_U3 (32 + 29) /* UART3 */
147#define VECNUM_EIR7 (32 + 30) /* External interrupt 7 */
148#define VECNUM_EIR8 (32 + 31) /* External interrupt 8 */
149
150/* UIC 2 */
151#define VECNUM_EIR9 (64 + 2) /* External interrupt 9 */
152#define VECNUM_MS (64 + 3) /* MAL SERR */
153#define VECNUM_TXDE (64 + 4) /* MAL TXDE */
154#define VECNUM_RXDE (64 + 5) /* MAL RXDE */
155#define VECNUM_MTE (64 + 6) /* MAL TXEOB */
156#define VECNUM_MRE (64 + 7) /* MAL RXEOB */
157#define VECNUM_ETH0 (64 + 16) /* Ethernet 0 */
158#define VECNUM_ETH1 (64 + 17) /* Ethernet 1 */
159#define VECNUM_ETH2 (64 + 18) /* Ethernet 2 */
160#define VECNUM_ETH3 (64 + 19) /* Ethernet 3 */
161#define VECNUM_EWU0 (64 + 20) /* Emac 0 wakeup */
162#define VECNUM_EWU1 (64 + 21) /* Emac 1 wakeup */
163#define VECNUM_EWU2 (64 + 22) /* Emac 2 wakeup */
164#define VECNUM_EWU3 (64 + 23) /* Emac 3 wakeup */
165#define VECNUM_EIR10 (64 + 24) /* External interrupt 10 */
166#define VECNUM_EIR11 (64 + 25) /* External interrupt 11 */
167
168/* UIC 3 */
169#define VECNUM_EIR12 (96 + 20) /* External interrupt 20 */
170#define VECNUM_EIR13 (96 + 21) /* External interrupt 21 */
171#define VECNUM_EIR14 (96 + 22) /* External interrupt 22 */
172#define VECNUM_EIR15 (96 + 23) /* External interrupt 23 */
173#define VECNUM_PCIEMSI0 (96 + 24) /* PCI Express MSI level 0 */
174#define VECNUM_PCIEMSI1 (96 + 25) /* PCI Express MSI level 1 */
175#define VECNUM_PCIEMSI2 (96 + 26) /* PCI Express MSI level 2 */
176#define VECNUM_PCIEMSI3 (96 + 27) /* PCI Express MSI level 3 */
177#define VECNUM_PCIEMSI4 (96 + 28) /* PCI Express MSI level 4 */
178#define VECNUM_PCIEMSI5 (96 + 29) /* PCI Express MSI level 5 */
179#define VECNUM_PCIEMSI6 (96 + 30) /* PCI Express MSI level 6 */
180#define VECNUM_PCIEMSI7 (96 + 31) /* PCI Express MSI level 7 */
181
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]182#elif defined(CONFIG_440SPE)
183
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200[diff] [blame]184/* UIC 0 */
185#define VECNUM_U0 0 /* UART0 */
186#define VECNUM_U1 1 /* UART1 */
187#define VECNUM_IIC0 2 /* IIC0 */
188#define VECNUM_IIC1 3 /* IIC1 */
189#define VECNUM_PIM 4 /* PCI inbound message */
190#define VECNUM_PCRW 5 /* PCI command reg write */
191#define VECNUM_PPM 6 /* PCI power management */
192#define VECNUM_MSI0 7 /* PCI MSI level 0 */
193#define VECNUM_MSI1 8 /* PCI MSI level 0 */
194#define VECNUM_MSI2 9 /* PCI MSI level 0 */
Stefan Roese999ecd52008-03-11 15:07:10 +0100[diff] [blame]195#define VECNUM_UIC2NC 10 /* UIC2 non-critical interrupt */
196#define VECNUM_UIC2C 11 /* UIC2 critical interrupt */
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200[diff] [blame]197#define VECNUM_D0 12 /* DMA channel 0 */
198#define VECNUM_D1 13 /* DMA channel 1 */
199#define VECNUM_D2 14 /* DMA channel 2 */
200#define VECNUM_D3 15 /* DMA channel 3 */
Stefan Roese999ecd52008-03-11 15:07:10 +0100[diff] [blame]201#define VECNUM_UIC3NC 16 /* UIC3 non-critical interrupt */
202#define VECNUM_UIC3C 17 /* UIC3 critical interrupt */
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200[diff] [blame]203#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */
204#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */
205
206/* UIC 1 */
207#define VECNUM_MS (32 + 1 ) /* MAL SERR */
208#define VECNUM_TXDE (32 + 2 ) /* MAL TXDE */
209#define VECNUM_RXDE (32 + 3 ) /* MAL RXDE */
210#define VECNUM_MTE (32 + 6 ) /* MAL Tx EOB */
211#define VECNUM_MRE (32 + 7 ) /* MAL Rx EOB */
212#define VECNUM_CT0 (32 + 12 ) /* GPT compare timer 0 */
213#define VECNUM_CT1 (32 + 13 ) /* GPT compare timer 1 */
214#define VECNUM_CT2 (32 + 14 ) /* GPT compare timer 2 */
215#define VECNUM_CT3 (32 + 15 ) /* GPT compare timer 3 */
216#define VECNUM_CT4 (32 + 16 ) /* GPT compare timer 4 */
217#define VECNUM_ETH0 (32 + 28) /* Ethernet interrupt status */
218#define VECNUM_EWU0 (32 + 29) /* Emac wakeup */
219
220/* UIC 2 */
Matthias Fuchs580d1d32008-01-08 15:39:01 +0100[diff] [blame]221#define VECNUM_EIR5 (64 + 24) /* External interrupt 5 */
222#define VECNUM_EIR4 (64 + 25) /* External interrupt 4 */
223#define VECNUM_EIR3 (64 + 26) /* External interrupt 3 */
224#define VECNUM_EIR2 (64 + 27) /* External interrupt 2 */
225#define VECNUM_EIR1 (64 + 28) /* External interrupt 1 */
226#define VECNUM_EIR0 (64 + 29) /* External interrupt 0 */
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200[diff] [blame]227
228#elif defined(CONFIG_440SP)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100[diff] [blame]229
230/* UIC 0 */
231#define VECNUM_U0 0 /* UART0 */
232#define VECNUM_U1 1 /* UART1 */
233#define VECNUM_IIC0 2 /* IIC0 */
234#define VECNUM_IIC1 3 /* IIC1 */
235#define VECNUM_PIM 4 /* PCI inbound message */
236#define VECNUM_PCRW 5 /* PCI command reg write */
237#define VECNUM_PPM 6 /* PCI power management */
238#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */
239#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */
240
241/* UIC 1 */
242#define VECNUM_EIR0 (32 + 0) /* External interrupt 0 */
243#define VECNUM_MS (32 + 1) /* MAL SERR */
244#define VECNUM_TXDE (32 + 2) /* MAL TXDE */
245#define VECNUM_RXDE (32 + 3) /* MAL RXDE */
246#define VECNUM_MTE (32 + 6) /* MAL Tx EOB */
247#define VECNUM_MRE (32 + 7) /* MAL Rx EOB */
248#define VECNUM_CT0 (32 + 12) /* GPT compare timer 0 */
249#define VECNUM_CT1 (32 + 13) /* GPT compare timer 1 */
250#define VECNUM_CT2 (32 + 14) /* GPT compare timer 2 */
251#define VECNUM_CT3 (32 + 15) /* GPT compare timer 3 */
252#define VECNUM_CT4 (32 + 16) /* GPT compare timer 4 */
253#define VECNUM_ETH0 (32 + 28) /* Ethernet interrupt status */
254#define VECNUM_EWU0 (32 + 29) /* Emac wakeup */
255
256#elif defined(CONFIG_440)
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]257
258/* UIC 0 */
259#define VECNUM_U0 0 /* UART0 */
260#define VECNUM_U1 1 /* UART1 */
261#define VECNUM_IIC0 2 /* IIC0 */
262#define VECNUM_IIC1 3 /* IIC1 */
263#define VECNUM_PIM 4 /* PCI inbound message */
264#define VECNUM_PCRW 5 /* PCI command reg write */
265#define VECNUM_PPM 6 /* PCI power management */
266#define VECNUM_MSI0 7 /* PCI MSI level 0 */
267#define VECNUM_MSI1 8 /* PCI MSI level 0 */
268#define VECNUM_MSI2 9 /* PCI MSI level 0 */
269#define VECNUM_MTE 10 /* MAL TXEOB */
270#define VECNUM_MRE 11 /* MAL RXEOB */
271#define VECNUM_D0 12 /* DMA channel 0 */
272#define VECNUM_D1 13 /* DMA channel 1 */
273#define VECNUM_D2 14 /* DMA channel 2 */
274#define VECNUM_D3 15 /* DMA channel 3 */
275#define VECNUM_CT0 18 /* GPT compare timer 0 */
276#define VECNUM_CT1 19 /* GPT compare timer 1 */
277#define VECNUM_CT2 20 /* GPT compare timer 2 */
278#define VECNUM_CT3 21 /* GPT compare timer 3 */
279#define VECNUM_CT4 22 /* GPT compare timer 4 */
280#define VECNUM_EIR0 23 /* External interrupt 0 */
281#define VECNUM_EIR1 24 /* External interrupt 1 */
282#define VECNUM_EIR2 25 /* External interrupt 2 */
283#define VECNUM_EIR3 26 /* External interrupt 3 */
284#define VECNUM_EIR4 27 /* External interrupt 4 */
285#define VECNUM_EIR5 28 /* External interrupt 5 */
286#define VECNUM_EIR6 29 /* External interrupt 6 */
287#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */
288#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */
289
290/* UIC 1 */
291#define VECNUM_MS (32 + 0 ) /* MAL SERR */
292#define VECNUM_TXDE (32 + 1 ) /* MAL TXDE */
293#define VECNUM_RXDE (32 + 2 ) /* MAL RXDE */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200[diff] [blame]294#define VECNUM_USBDEV (32 + 23) /* USB 1.1/USB 2.0 Device */
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]295#define VECNUM_ETH0 (32 + 28) /* Ethernet 0 interrupt status */
296#define VECNUM_EWU0 (32 + 29) /* Ethernet 0 wakeup */
297
298#else /* !defined(CONFIG_440) */
299
Stefan Roesee01bd212007-03-21 13:38:59 +0100[diff] [blame]300#if defined(CONFIG_405EZ)
301#define VECNUM_D0 0 /* DMA channel 0 */
302#define VECNUM_D1 1 /* DMA channel 1 */
303#define VECNUM_D2 2 /* DMA channel 2 */
304#define VECNUM_D3 3 /* DMA channel 3 */
305#define VECNUM_1588 4 /* IEEE 1588 network synchronization */
306#define VECNUM_U0 5 /* UART0 */
307#define VECNUM_U1 6 /* UART1 */
308#define VECNUM_CAN0 7 /* CAN 0 */
309#define VECNUM_CAN1 8 /* CAN 1 */
310#define VECNUM_SPI 9 /* SPI */
311#define VECNUM_IIC0 10 /* I2C */
312#define VECNUM_CHT0 11 /* Chameleon timer high pri interrupt */
313#define VECNUM_CHT1 12 /* Chameleon timer high pri interrupt */
314#define VECNUM_USBH1 13 /* USB Host 1 */
315#define VECNUM_USBH2 14 /* USB Host 2 */
316#define VECNUM_USBDEV 15 /* USB Device */
317#define VECNUM_ETH0 16 /* 10/100 Ethernet interrupt status */
318#define VECNUM_EWU0 17 /* Ethernet wakeup sequence detected */
319
320#define VECNUM_MADMAL 18 /* Logical OR of following MadMAL int */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200[diff] [blame]321#define VECNUM_MS 18 /* MAL_SERR_INT */
322#define VECNUM_TXDE 18 /* MAL_TXDE_INT */
323#define VECNUM_RXDE 18 /* MAL_RXDE_INT */
Stefan Roesee01bd212007-03-21 13:38:59 +0100[diff] [blame]324
325#define VECNUM_MTE 19 /* MAL TXEOB */
326#define VECNUM_MTE1 20 /* MAL TXEOB1 */
327#define VECNUM_MRE 21 /* MAL RXEOB */
328#define VECNUM_NAND 22 /* NAND Flash controller */
329#define VECNUM_ADC 23 /* ADC */
330#define VECNUM_DAC 24 /* DAC */
331#define VECNUM_OPB2PLB 25 /* OPB to PLB bridge interrupt */
332#define VECNUM_RESERVED0 26 /* Reserved */
333#define VECNUM_EIR0 27 /* External interrupt 0 */
334#define VECNUM_EIR1 28 /* External interrupt 1 */
335#define VECNUM_EIR2 29 /* External interrupt 2 */
336#define VECNUM_EIR3 30 /* External interrupt 3 */
337#define VECNUM_EIR4 31 /* External interrupt 4 */
338
Stefan Roesedbbd1252007-10-05 17:10:59 +0200[diff] [blame]339#elif defined(CONFIG_405EX)
340
341/* UIC 0 */
342#define VECNUM_U0 00
343#define VECNUM_U1 01
344#define VECNUM_IIC0 02
345#define VECNUM_PKA 03
346#define VECNUM_TRNG 04
347#define VECNUM_EBM 05
348#define VECNUM_BGI 06
349#define VECNUM_IIC1 07
350#define VECNUM_SPI 08
351#define VECNUM_EIR0 09
352#define VECNUM_MTE 10 /* MAL Tx EOB */
353#define VECNUM_MRE 11 /* MAL Rx EOB */
354#define VECNUM_DMA0 12
355#define VECNUM_DMA1 13
356#define VECNUM_DMA2 14
357#define VECNUM_DMA3 15
358#define VECNUM_PCIE0AL 16
359#define VECNUM_PCIE0VPD 17
360#define VECNUM_RPCIE0HRST 18
361#define VECNUM_FPCIE0HRST 19
362#define VECNUM_PCIE0TCR 20
363#define VECNUM_PCIEMSI0 21
364#define VECNUM_PCIEMSI1 22
365#define VECNUM_SECURITY 23
366#define VECNUM_ETH0 24
367#define VECNUM_ETH1 25
368#define VECNUM_PCIEMSI2 26
369#define VECNUM_EIR4 27
370#define VECNUM_UIC2NC 28
371#define VECNUM_UIC2C 29
372#define VECNUM_UIC1NC 30
373#define VECNUM_UIC1C 31
374
375/* UIC 1 */
376#define VECNUM_MS (32 + 00) /* MAL SERR */
377#define VECNUM_TXDE (32 + 01) /* MAL TXDE */
378#define VECNUM_RXDE (32 + 02) /* MAL RXDE */
379#define VECNUM_PCIE0BMVC0 (32 + 03)
380#define VECNUM_PCIE0DCRERR (32 + 04)
381#define VECNUM_EBC (32 + 05)
382#define VECNUM_NDFC (32 + 06)
383#define VECNUM_PCEI1DCRERR (32 + 07)
384#define VECNUM_CT8 (32 + 08)
385#define VECNUM_CT9 (32 + 09)
386#define VECNUM_PCIE1AL (32 + 10)
387#define VECNUM_PCIE1VPD (32 + 11)
388#define VECNUM_RPCE1HRST (32 + 12)
389#define VECNUM_FPCE1HRST (32 + 13)
390#define VECNUM_PCIE1TCR (32 + 14)
391#define VECNUM_PCIE1VC0 (32 + 15)
392#define VECNUM_CT3 (32 + 16)
393#define VECNUM_CT4 (32 + 17)
394#define VECNUM_EIR7 (32 + 18)
395#define VECNUM_EIR8 (32 + 19)
396#define VECNUM_EIR9 (32 + 20)
397#define VECNUM_CT5 (32 + 21)
398#define VECNUM_CT6 (32 + 22)
399#define VECNUM_CT7 (32 + 23)
400#define VECNUM_SROM (32 + 24) /* SERIAL ROM */
401#define VECNUM_GPTDECPULS (32 + 25) /* GPT Decrement pulse */
402#define VECNUM_EIR2 (32 + 26)
403#define VECNUM_EIR5 (32 + 27)
404#define VECNUM_EIR6 (32 + 28)
405#define VECNUM_EMAC0WAKE (32 + 29)
406#define VECNUM_EIR1 (32 + 30)
407#define VECNUM_EMAC1WAKE (32 + 31)
408
409/* UIC 2 */
410#define VECNUM_PCIE0INTA (64 + 00) /* PCIE0 INTA */
411#define VECNUM_PCIE0INTB (64 + 01) /* PCIE0 INTB */
412#define VECNUM_PCIE0INTC (64 + 02) /* PCIE0 INTC */
413#define VECNUM_PCIE0INTD (64 + 03) /* PCIE0 INTD */
414#define VECNUM_EIR3 (64 + 04) /* External IRQ 3 */
415#define VECNUM_DDRMCUE (64 + 05)
416#define VECNUM_DDRMCCE (64 + 06)
417#define VECNUM_MALINTCOATX0 (64 + 07) /* Interrupt coalecence TX0 */
418#define VECNUM_MALINTCOATX1 (64 + 08) /* Interrupt coalecence TX1 */
419#define VECNUM_MALINTCOARX0 (64 + 09) /* Interrupt coalecence RX0 */
420#define VECNUM_MALINTCOARX1 (64 + 10) /* Interrupt coalecence RX1 */
421#define VECNUM_PCIE1INTA (64 + 11) /* PCIE0 INTA */
422#define VECNUM_PCIE1INTB (64 + 12) /* PCIE0 INTB */
423#define VECNUM_PCIE1INTC (64 + 13) /* PCIE0 INTC */
424#define VECNUM_PCIE1INTD (64 + 14) /* PCIE0 INTD */
425#define VECNUM_RPCIEMSI2 (64 + 15) /* MSI level 2 */
426#define VECNUM_PCIEMSI3 (64 + 16) /* MSI level 2 */
427#define VECNUM_PCIEMSI4 (64 + 17) /* MSI level 2 */
428#define VECNUM_PCIEMSI5 (64 + 18) /* MSI level 2 */
429#define VECNUM_PCIEMSI6 (64 + 19) /* MSI level 2 */
430#define VECNUM_PCIEMSI7 (64 + 20) /* MSI level 2 */
431#define VECNUM_PCIEMSI8 (64 + 21) /* MSI level 2 */
432#define VECNUM_PCIEMSI9 (64 + 22) /* MSI level 2 */
433#define VECNUM_PCIEMSI10 (64 + 23) /* MSI level 2 */
434#define VECNUM_PCIEMSI11 (64 + 24) /* MSI level 2 */
435#define VECNUM_PCIEMSI12 (64 + 25) /* MSI level 2 */
436#define VECNUM_PCIEMSI13 (64 + 26) /* MSI level 2 */
437#define VECNUM_PCIEMSI14 (64 + 27) /* MSI level 2 */
438#define VECNUM_PCIEMSI15 (64 + 28) /* MSI level 2 */
439#define VECNUM_PLB4XAHB (64 + 29) /* PLBxAHB bridge */
440#define VECNUM_USBWAKE (64 + 30) /* USB wakup */
441#define VECNUM_USBOTG (64 + 31) /* USB OTG */
442
Stefan Roesee01bd212007-03-21 13:38:59 +0100[diff] [blame]443#else /* !CONFIG_405EZ */
444
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]445#define VECNUM_U0 0 /* UART0 */
446#define VECNUM_U1 1 /* UART1 */
447#define VECNUM_D0 5 /* DMA channel 0 */
448#define VECNUM_D1 6 /* DMA channel 1 */
449#define VECNUM_D2 7 /* DMA channel 2 */
450#define VECNUM_D3 8 /* DMA channel 3 */
451#define VECNUM_EWU0 9 /* Ethernet wakeup */
452#define VECNUM_MS 10 /* MAL SERR */
453#define VECNUM_MTE 11 /* MAL TXEOB */
454#define VECNUM_MRE 12 /* MAL RXEOB */
455#define VECNUM_TXDE 13 /* MAL TXDE */
456#define VECNUM_RXDE 14 /* MAL RXDE */
457#define VECNUM_ETH0 15 /* Ethernet interrupt status */
458#define VECNUM_EIR0 25 /* External interrupt 0 */
459#define VECNUM_EIR1 26 /* External interrupt 1 */
460#define VECNUM_EIR2 27 /* External interrupt 2 */
461#define VECNUM_EIR3 28 /* External interrupt 3 */
462#define VECNUM_EIR4 29 /* External interrupt 4 */
463#define VECNUM_EIR5 30 /* External interrupt 5 */
464#define VECNUM_EIR6 31 /* External interrupt 6 */
Stefan Roesee01bd212007-03-21 13:38:59 +0100[diff] [blame]465#endif /* defined(CONFIG_405EZ) */
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]466
467#endif /* defined(CONFIG_440) */
468
Stefan Roese4fb25a32008-06-25 10:59:22 +0200[diff] [blame^]469#endif /* _PPC4xx_UIC_H_ */