| Michael Walle | 4ceb5c6 | 2020-10-15 23:08:57 +0200 | [diff] [blame^] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | |
| 3 | #include <common.h> |
| 4 | #include <asm/io.h> |
| 5 | #include <fsl_ddr_sdram.h> |
| 6 | |
| 7 | DECLARE_GLOBAL_DATA_PTR; |
| 8 | |
| 9 | #define DCFG_GPPORCR1 0x20 |
| 10 | |
| 11 | #define GPPORCR1_MEM_MASK (0x7 << 5) |
| 12 | #define GPPORCR1_MEM_512MB_CS0 (0x0 << 5) |
| 13 | #define GPPORCR1_MEM_1GB_CS0 (0x1 << 5) |
| 14 | #define GPPORCR1_MEM_2GB_CS0 (0x2 << 5) |
| 15 | #define GPPORCR1_MEM_4GB_CS0_1 (0x3 << 5) |
| 16 | #define GPPORCR1_MEM_4GB_CS0_2 (0x4 << 5) |
| 17 | #define GPPORCR1_MEM_8GB_CS0_1_2_3 (0x5 << 5) |
| 18 | #define GPPORCR1_MEM_8GB_CS0_1 (0x6 << 5) |
| 19 | |
| 20 | static fsl_ddr_cfg_regs_t __maybe_unused ddr_cfg_regs = { |
| 21 | .cs[0].bnds = 0x0000007f, |
| 22 | .cs[0].config = 0x80044402, |
| 23 | .cs[1].bnds = 0x008000ff, |
| 24 | .cs[1].config = 0x80004402, |
| 25 | |
| 26 | .timing_cfg_0 = 0x9011010c, |
| 27 | .timing_cfg_3 = 0x010c1000, |
| 28 | .timing_cfg_1 = 0xbcb48c66, |
| 29 | .timing_cfg_2 = 0x0fc0d118, |
| 30 | .ddr_sdram_cfg = 0xe70c000c, |
| 31 | .ddr_sdram_cfg_2 = 0x24401111, |
| 32 | .ddr_sdram_mode = 0x00441c70, |
| 33 | .ddr_sdram_mode_3 = 0x00001c70, |
| 34 | .ddr_sdram_mode_5 = 0x00001c70, |
| 35 | .ddr_sdram_mode_7 = 0x00001c70, |
| 36 | .ddr_sdram_mode_2 = 0x00180000, |
| 37 | .ddr_sdram_mode_4 = 0x00180000, |
| 38 | .ddr_sdram_mode_6 = 0x00180000, |
| 39 | .ddr_sdram_mode_8 = 0x00180000, |
| 40 | |
| 41 | .ddr_sdram_interval = 0x0c30030c, |
| 42 | .ddr_data_init = 0xdeadbeef, |
| 43 | |
| 44 | .ddr_sdram_clk_cntl = 0x02400000, |
| 45 | |
| 46 | .timing_cfg_4 = 0x00000001, |
| 47 | .timing_cfg_5 = 0x04401400, |
| 48 | |
| 49 | .ddr_zq_cntl = 0x89080600, |
| 50 | .ddr_wrlvl_cntl = 0x8675f606, |
| 51 | .ddr_wrlvl_cntl_2 = 0x04080700, |
| 52 | .ddr_wrlvl_cntl_3 = 0x00000009, |
| 53 | |
| 54 | .ddr_cdr1 = 0x80040000, |
| 55 | .ddr_cdr2 = 0x0000bc01, |
| 56 | }; |
| 57 | |
| 58 | int fsl_initdram(void) |
| 59 | { |
| 60 | u32 gpporcr1 = in_le32(DCFG_BASE + DCFG_GPPORCR1); |
| 61 | phys_size_t dram_size; |
| 62 | |
| 63 | switch (gpporcr1 & GPPORCR1_MEM_MASK) { |
| 64 | case GPPORCR1_MEM_2GB_CS0: |
| 65 | dram_size = 0x80000000; |
| 66 | ddr_cfg_regs.cs[1].bnds = 0; |
| 67 | ddr_cfg_regs.cs[1].config = 0; |
| 68 | ddr_cfg_regs.cs[1].config_2 = 0; |
| 69 | break; |
| 70 | case GPPORCR1_MEM_4GB_CS0_1: |
| 71 | dram_size = 0x100000000ULL; |
| 72 | break; |
| 73 | case GPPORCR1_MEM_512MB_CS0: |
| 74 | dram_size = 0x20000000; |
| 75 | fallthrough; /* for now */ |
| 76 | case GPPORCR1_MEM_1GB_CS0: |
| 77 | dram_size = 0x40000000; |
| 78 | fallthrough; /* for now */ |
| 79 | case GPPORCR1_MEM_4GB_CS0_2: |
| 80 | dram_size = 0x100000000ULL; |
| 81 | fallthrough; /* for now */ |
| 82 | case GPPORCR1_MEM_8GB_CS0_1: |
| 83 | case GPPORCR1_MEM_8GB_CS0_1_2_3: |
| 84 | dram_size = 0x200000000ULL; |
| 85 | fallthrough; /* for now */ |
| 86 | default: |
| 87 | panic("Unsupported memory configuration (%08x)\n", |
| 88 | gpporcr1 & GPPORCR1_MEM_MASK); |
| 89 | break; |
| 90 | } |
| 91 | |
| 92 | if (!IS_ENABLED(CONFIG_SPL) || IS_ENABLED(CONFIG_SPL_BUILD)) |
| 93 | fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); |
| 94 | |
| 95 | gd->ram_size = dram_size; |
| 96 | |
| 97 | return 0; |
| 98 | } |