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Wang Huan550e3dc2014-09-05 13:52:44 +08001/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
Wang Huan550e3dc2014-09-05 13:52:44 +080010#define CONFIG_LS102XA
11
Wang Dongsheng340848b2015-06-04 12:01:09 +080012#define CONFIG_ARMV7_PSCI
13
Gong Qianyu18fb0e32015-10-26 19:47:42 +080014#define CONFIG_SYS_FSL_CLK
Wang Huan550e3dc2014-09-05 13:52:44 +080015
16#define CONFIG_DISPLAY_CPUINFO
17#define CONFIG_DISPLAY_BOARDINFO
18
19#define CONFIG_SKIP_LOWLEVEL_INIT
20#define CONFIG_BOARD_EARLY_INIT_F
21
tang yuantian41ba57d2014-12-17 12:58:05 +080022#define CONFIG_DEEP_SLEEP
23#if defined(CONFIG_DEEP_SLEEP)
24#define CONFIG_SILENT_CONSOLE
25#endif
26
Wang Huan550e3dc2014-09-05 13:52:44 +080027/*
28 * Size of malloc() pool
29 */
30#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
31
32#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
33#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
34
35/*
36 * Generic Timer Definitions
37 */
38#define GENERIC_TIMER_CLK 12500000
39
40#ifndef __ASSEMBLY__
41unsigned long get_board_sys_clk(void);
42unsigned long get_board_ddr_clk(void);
43#endif
44
Alison Wangd612f0a2014-12-09 17:38:02 +080045#ifdef CONFIG_QSPI_BOOT
46#define CONFIG_SYS_CLK_FREQ 100000000
47#define CONFIG_DDR_CLK_FREQ 100000000
48#define CONFIG_QIXIS_I2C_ACCESS
49#else
Wang Huan550e3dc2014-09-05 13:52:44 +080050#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
51#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
Alison Wangd612f0a2014-12-09 17:38:02 +080052#endif
Wang Huan550e3dc2014-09-05 13:52:44 +080053
Alison Wang86949c22014-12-03 15:00:47 +080054#ifdef CONFIG_RAMBOOT_PBL
55#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg
56#endif
57
58#ifdef CONFIG_SD_BOOT
59#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg
60#define CONFIG_SPL_FRAMEWORK
61#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
62#define CONFIG_SPL_LIBCOMMON_SUPPORT
63#define CONFIG_SPL_LIBGENERIC_SUPPORT
64#define CONFIG_SPL_ENV_SUPPORT
65#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
66#define CONFIG_SPL_I2C_SUPPORT
67#define CONFIG_SPL_WATCHDOG_SUPPORT
68#define CONFIG_SPL_SERIAL_SUPPORT
69#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
70#define CONFIG_SPL_MMC_SUPPORT
71#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
Alison Wang7ee52af2015-10-30 22:45:38 +080072#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x600
Alison Wang86949c22014-12-03 15:00:47 +080073
74#define CONFIG_SPL_TEXT_BASE 0x10000000
75#define CONFIG_SPL_MAX_SIZE 0x1a000
76#define CONFIG_SPL_STACK 0x1001d000
77#define CONFIG_SPL_PAD_TO 0x1c000
78#define CONFIG_SYS_TEXT_BASE 0x82000000
79
tang yuantian41ba57d2014-12-17 12:58:05 +080080#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
81 CONFIG_SYS_MONITOR_LEN)
Alison Wang86949c22014-12-03 15:00:47 +080082#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
83#define CONFIG_SPL_BSS_START_ADDR 0x80100000
84#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
Alison Wang7ee52af2015-10-30 22:45:38 +080085#define CONFIG_SYS_MONITOR_LEN 0xc0000
Alison Wang86949c22014-12-03 15:00:47 +080086#endif
87
Alison Wangd612f0a2014-12-09 17:38:02 +080088#ifdef CONFIG_QSPI_BOOT
89#define CONFIG_SYS_TEXT_BASE 0x40010000
90#define CONFIG_SYS_NO_FLASH
91#endif
92
Alison Wang8ab967b2014-12-09 17:38:14 +080093#ifdef CONFIG_NAND_BOOT
94#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
95#define CONFIG_SPL_FRAMEWORK
96#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
97#define CONFIG_SPL_LIBCOMMON_SUPPORT
98#define CONFIG_SPL_LIBGENERIC_SUPPORT
99#define CONFIG_SPL_ENV_SUPPORT
100#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
101#define CONFIG_SPL_I2C_SUPPORT
102#define CONFIG_SPL_WATCHDOG_SUPPORT
103#define CONFIG_SPL_SERIAL_SUPPORT
104#define CONFIG_SPL_NAND_SUPPORT
105#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
106
107#define CONFIG_SPL_TEXT_BASE 0x10000000
108#define CONFIG_SPL_MAX_SIZE 0x1a000
109#define CONFIG_SPL_STACK 0x1001d000
110#define CONFIG_SPL_PAD_TO 0x1c000
111#define CONFIG_SYS_TEXT_BASE 0x82000000
112
113#define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10)
114#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
115#define CONFIG_SYS_NAND_PAGE_SIZE 2048
116#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
117#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
118
119#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
120#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
121#define CONFIG_SPL_BSS_START_ADDR 0x80100000
122#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
123#define CONFIG_SYS_MONITOR_LEN 0x80000
124#endif
125
Wang Huan550e3dc2014-09-05 13:52:44 +0800126#ifndef CONFIG_SYS_TEXT_BASE
Alison Wang1c69a512015-04-21 16:04:38 +0800127#define CONFIG_SYS_TEXT_BASE 0x60100000
Wang Huan550e3dc2014-09-05 13:52:44 +0800128#endif
129
130#define CONFIG_NR_DRAM_BANKS 1
131
132#define CONFIG_DDR_SPD
133#define SPD_EEPROM_ADDRESS 0x51
134#define CONFIG_SYS_SPD_BUS_NUM 0
Wang Huan550e3dc2014-09-05 13:52:44 +0800135
136#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
York Sunc7eae7f2014-09-11 13:32:07 -0700137#ifndef CONFIG_SYS_FSL_DDR4
Wang Huan550e3dc2014-09-05 13:52:44 +0800138#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
York Sunc7eae7f2014-09-11 13:32:07 -0700139#define CONFIG_SYS_DDR_RAW_TIMING
140#endif
Wang Huan550e3dc2014-09-05 13:52:44 +0800141#define CONFIG_DIMM_SLOTS_PER_CTLR 1
142#define CONFIG_CHIP_SELECTS_PER_CTRL 4
143
144#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
145#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
146
147#define CONFIG_DDR_ECC
148#ifdef CONFIG_DDR_ECC
149#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
150#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
151#endif
152
153#define CONFIG_SYS_HAS_SERDES
154
Ruchika Gupta4ba4a092014-10-15 11:39:06 +0530155#define CONFIG_FSL_CAAM /* Enable CAAM */
Zhao Qiang63e75fd2014-09-26 16:25:32 +0800156
Alison Wang4c59ab92014-12-09 17:37:49 +0800157#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
158 !defined(CONFIG_QSPI_BOOT)
Zhao Qiang63e75fd2014-09-26 16:25:32 +0800159#define CONFIG_U_QE
160#endif
161
Wang Huan550e3dc2014-09-05 13:52:44 +0800162/*
163 * IFC Definitions
164 */
Alison Wangd612f0a2014-12-09 17:38:02 +0800165#ifndef CONFIG_QSPI_BOOT
Wang Huan550e3dc2014-09-05 13:52:44 +0800166#define CONFIG_FSL_IFC
167#define CONFIG_SYS_FLASH_BASE 0x60000000
168#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
169
170#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
171#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
172 CSPR_PORT_SIZE_16 | \
173 CSPR_MSEL_NOR | \
174 CSPR_V)
175#define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
176#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
177 + 0x8000000) | \
178 CSPR_PORT_SIZE_16 | \
179 CSPR_MSEL_NOR | \
180 CSPR_V)
181#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
182
183#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
184 CSOR_NOR_TRHZ_80)
185#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
186 FTIM0_NOR_TEADC(0x5) | \
187 FTIM0_NOR_TEAHC(0x5))
188#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
189 FTIM1_NOR_TRAD_NOR(0x1a) | \
190 FTIM1_NOR_TSEQRAD_NOR(0x13))
191#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
192 FTIM2_NOR_TCH(0x4) | \
193 FTIM2_NOR_TWPH(0xe) | \
194 FTIM2_NOR_TWP(0x1c))
195#define CONFIG_SYS_NOR_FTIM3 0
196
197#define CONFIG_FLASH_CFI_DRIVER
198#define CONFIG_SYS_FLASH_CFI
199#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
200#define CONFIG_SYS_FLASH_QUIET_TEST
201#define CONFIG_FLASH_SHOW_PROGRESS 45
202#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
Yuan Yao272c5262014-10-17 15:26:34 +0800203#define CONFIG_SYS_WRITE_SWAPPED_DATA
Wang Huan550e3dc2014-09-05 13:52:44 +0800204
205#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
206#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
207#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
208#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
209
210#define CONFIG_SYS_FLASH_EMPTY_INFO
211#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
212 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
213
214/*
215 * NAND Flash Definitions
216 */
217#define CONFIG_NAND_FSL_IFC
218
219#define CONFIG_SYS_NAND_BASE 0x7e800000
220#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
221
222#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
223
224#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
225 | CSPR_PORT_SIZE_8 \
226 | CSPR_MSEL_NAND \
227 | CSPR_V)
228#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
229#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
230 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
231 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
232 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
233 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
234 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
235 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
236
237#define CONFIG_SYS_NAND_ONFI_DETECTION
238
239#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
240 FTIM0_NAND_TWP(0x18) | \
241 FTIM0_NAND_TWCHT(0x7) | \
242 FTIM0_NAND_TWH(0xa))
243#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
244 FTIM1_NAND_TWBE(0x39) | \
245 FTIM1_NAND_TRR(0xe) | \
246 FTIM1_NAND_TRP(0x18))
247#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
248 FTIM2_NAND_TREH(0xa) | \
249 FTIM2_NAND_TWHRE(0x1e))
250#define CONFIG_SYS_NAND_FTIM3 0x0
251
252#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
253#define CONFIG_SYS_MAX_NAND_DEVICE 1
Wang Huan550e3dc2014-09-05 13:52:44 +0800254#define CONFIG_CMD_NAND
255
256#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
Alison Wangd612f0a2014-12-09 17:38:02 +0800257#endif
Wang Huan550e3dc2014-09-05 13:52:44 +0800258
259/*
260 * QIXIS Definitions
261 */
262#define CONFIG_FSL_QIXIS
263
264#ifdef CONFIG_FSL_QIXIS
265#define QIXIS_BASE 0x7fb00000
266#define QIXIS_BASE_PHYS QIXIS_BASE
267#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
268#define QIXIS_LBMAP_SWITCH 6
269#define QIXIS_LBMAP_MASK 0x0f
270#define QIXIS_LBMAP_SHIFT 0
271#define QIXIS_LBMAP_DFLTBANK 0x00
272#define QIXIS_LBMAP_ALTBANK 0x04
273#define QIXIS_RST_CTL_RESET 0x44
274#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
275#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
276#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
277
278#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
279#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
280 CSPR_PORT_SIZE_8 | \
281 CSPR_MSEL_GPCM | \
282 CSPR_V)
283#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
284#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
285 CSOR_NOR_NOR_MODE_AVD_NOR | \
286 CSOR_NOR_TRHZ_80)
287
288/*
289 * QIXIS Timing parameters for IFC GPCM
290 */
291#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \
292 FTIM0_GPCM_TEADC(0xe) | \
293 FTIM0_GPCM_TEAHC(0xe))
294#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \
295 FTIM1_GPCM_TRAD(0x1f))
296#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \
297 FTIM2_GPCM_TCH(0xe) | \
298 FTIM2_GPCM_TWP(0xf0))
299#define CONFIG_SYS_FPGA_FTIM3 0x0
300#endif
301
Alison Wang8ab967b2014-12-09 17:38:14 +0800302#if defined(CONFIG_NAND_BOOT)
303#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
304#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
305#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
306#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
307#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
308#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
309#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
310#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
311#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
312#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
313#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
314#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
315#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
316#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
317#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
318#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
319#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
320#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
321#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
322#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
323#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
324#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
325#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
326#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
327#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
328#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
329#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
330#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
331#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
332#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
333#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
334#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
335#else
Wang Huan550e3dc2014-09-05 13:52:44 +0800336#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
337#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
338#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
339#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
340#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
341#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
342#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
343#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
344#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
345#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
346#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
347#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
348#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
349#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
350#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
351#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
352#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
353#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
354#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
355#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
356#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
357#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
358#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
359#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
360#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
361#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
362#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
363#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
364#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
365#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
366#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
367#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
Alison Wang8ab967b2014-12-09 17:38:14 +0800368#endif
Wang Huan550e3dc2014-09-05 13:52:44 +0800369
370/*
371 * Serial Port
372 */
Alison Wang8fc21212015-01-04 15:30:58 +0800373#ifdef CONFIG_LPUART
374#define CONFIG_FSL_LPUART
375#define CONFIG_LPUART_32B_REG
376#else
Wang Huan550e3dc2014-09-05 13:52:44 +0800377#define CONFIG_CONS_INDEX 1
Wang Huan550e3dc2014-09-05 13:52:44 +0800378#define CONFIG_SYS_NS16550_SERIAL
379#define CONFIG_SYS_NS16550_REG_SIZE 1
380#define CONFIG_SYS_NS16550_CLK get_serial_clock()
Alison Wang8fc21212015-01-04 15:30:58 +0800381#endif
Wang Huan550e3dc2014-09-05 13:52:44 +0800382
383#define CONFIG_BAUDRATE 115200
384
385/*
386 * I2C
387 */
388#define CONFIG_CMD_I2C
389#define CONFIG_SYS_I2C
390#define CONFIG_SYS_I2C_MXC
Albert ARIBAUD \\(3ADEV\\)03544c62015-09-21 22:43:38 +0200391#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
392#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
York Sunf8cb1012015-03-20 10:20:40 -0700393#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
Wang Huan550e3dc2014-09-05 13:52:44 +0800394
395/*
396 * I2C bus multiplexer
397 */
398#define I2C_MUX_PCA_ADDR_PRI 0x77
399#define I2C_MUX_CH_DEFAULT 0x8
Xiubo Lidd048322014-12-16 14:50:33 +0800400#define I2C_MUX_CH_CH7301 0xC
Wang Huan550e3dc2014-09-05 13:52:44 +0800401
402/*
403 * MMC
404 */
405#define CONFIG_MMC
406#define CONFIG_CMD_MMC
407#define CONFIG_FSL_ESDHC
408#define CONFIG_GENERIC_MMC
409
Alison Wang8251ed22014-12-09 17:37:34 +0800410#define CONFIG_CMD_FAT
411#define CONFIG_DOS_PARTITION
412
Haikun Wange5493d42015-06-29 13:08:46 +0530413/* SPI */
Alison Wangd612f0a2014-12-09 17:38:02 +0800414#ifdef CONFIG_QSPI_BOOT
Haikun Wange5493d42015-06-29 13:08:46 +0530415/* QSPI */
Alison Wangd612f0a2014-12-09 17:38:02 +0800416#define QSPI0_AMBA_BASE 0x40000000
417#define FSL_QSPI_FLASH_SIZE (1 << 24)
418#define FSL_QSPI_FLASH_NUM 2
Haikun Wange5493d42015-06-29 13:08:46 +0530419
420/* DSPI */
Haikun Wange5493d42015-06-29 13:08:46 +0530421
422/* DM SPI */
423#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
424#define CONFIG_CMD_SF
425#define CONFIG_DM_SPI_FLASH
Jagan Teki68124842015-06-27 22:04:55 +0530426#define CONFIG_SPI_FLASH_DATAFLASH
Haikun Wange5493d42015-06-29 13:08:46 +0530427#endif
Alison Wangd612f0a2014-12-09 17:38:02 +0800428#endif
429
Wang Huan550e3dc2014-09-05 13:52:44 +0800430/*
Nikhil Badola8776cb22014-10-17 11:37:25 +0530431 * USB
432 */
Ramneek Mehresh081a1b72015-05-29 14:47:22 +0530433/* EHCI Support - disbaled by default */
434/*#define CONFIG_HAS_FSL_DR_USB*/
Nikhil Badola8776cb22014-10-17 11:37:25 +0530435
436#ifdef CONFIG_HAS_FSL_DR_USB
437#define CONFIG_USB_EHCI
Nikhil Badola8776cb22014-10-17 11:37:25 +0530438#define CONFIG_USB_EHCI_FSL
439#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
Nikhil Badola8776cb22014-10-17 11:37:25 +0530440#endif
Ramneek Mehresh081a1b72015-05-29 14:47:22 +0530441
442/*XHCI Support - enabled by default*/
443#define CONFIG_HAS_FSL_XHCI_USB
444
445#ifdef CONFIG_HAS_FSL_XHCI_USB
446#define CONFIG_USB_XHCI_FSL
447#define CONFIG_USB_XHCI_DWC3
448#define CONFIG_USB_XHCI
449#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
450#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
451#endif
452
453#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB)
454#define CONFIG_CMD_USB
455#define CONFIG_USB_STORAGE
456#define CONFIG_CMD_EXT2
Nikhil Badola8776cb22014-10-17 11:37:25 +0530457#endif
458
459/*
Xiubo Lidd048322014-12-16 14:50:33 +0800460 * Video
461 */
462#define CONFIG_FSL_DCU_FB
463
464#ifdef CONFIG_FSL_DCU_FB
465#define CONFIG_VIDEO
466#define CONFIG_CMD_BMP
467#define CONFIG_CFB_CONSOLE
468#define CONFIG_VGA_AS_SINGLE_DEVICE
469#define CONFIG_VIDEO_LOGO
470#define CONFIG_VIDEO_BMP_LOGO
471
472#define CONFIG_FSL_DIU_CH7301
473#define CONFIG_SYS_I2C_DVI_BUS_NUM 0
474#define CONFIG_SYS_I2C_QIXIS_ADDR 0x66
475#define CONFIG_SYS_I2C_DVI_ADDR 0x75
476#endif
477
478/*
Wang Huan550e3dc2014-09-05 13:52:44 +0800479 * eTSEC
480 */
481#define CONFIG_TSEC_ENET
482
483#ifdef CONFIG_TSEC_ENET
484#define CONFIG_MII
485#define CONFIG_MII_DEFAULT_TSEC 3
486#define CONFIG_TSEC1 1
487#define CONFIG_TSEC1_NAME "eTSEC1"
488#define CONFIG_TSEC2 1
489#define CONFIG_TSEC2_NAME "eTSEC2"
490#define CONFIG_TSEC3 1
491#define CONFIG_TSEC3_NAME "eTSEC3"
492
493#define TSEC1_PHY_ADDR 1
494#define TSEC2_PHY_ADDR 2
495#define TSEC3_PHY_ADDR 3
496
497#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
498#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
499#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
500
501#define TSEC1_PHYIDX 0
502#define TSEC2_PHYIDX 0
503#define TSEC3_PHYIDX 0
504
505#define CONFIG_ETHPRIME "eTSEC1"
506
507#define CONFIG_PHY_GIGE
508#define CONFIG_PHYLIB
509#define CONFIG_PHY_REALTEK
510
511#define CONFIG_HAS_ETH0
512#define CONFIG_HAS_ETH1
513#define CONFIG_HAS_ETH2
514
515#define CONFIG_FSL_SGMII_RISER 1
516#define SGMII_RISER_PHY_OFFSET 0x1b
517
518#ifdef CONFIG_FSL_SGMII_RISER
519#define CONFIG_SYS_TBIPA_VALUE 8
520#endif
521
522#endif
Minghuan Lianda419022014-10-31 13:43:44 +0800523
524/* PCIe */
525#define CONFIG_PCI /* Enable PCI/PCIE */
526#define CONFIG_PCIE1 /* PCIE controler 1 */
527#define CONFIG_PCIE2 /* PCIE controler 2 */
528#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
529#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
530
Minghuan Lian180b8682015-01-21 17:29:19 +0800531#define CONFIG_SYS_PCI_64BIT
532
533#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
534#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
535#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
536#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
537
538#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
539#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
540#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
541
542#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
543#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
544#define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */
545
546#ifdef CONFIG_PCI
Minghuan Lian180b8682015-01-21 17:29:19 +0800547#define CONFIG_PCI_PNP
Minghuan Lian180b8682015-01-21 17:29:19 +0800548#define CONFIG_PCI_SCAN_SHOW
549#define CONFIG_CMD_PCI
Minghuan Lian180b8682015-01-21 17:29:19 +0800550#endif
551
Wang Huan550e3dc2014-09-05 13:52:44 +0800552#define CONFIG_CMD_PING
553#define CONFIG_CMD_DHCP
554#define CONFIG_CMD_MII
Wang Huan550e3dc2014-09-05 13:52:44 +0800555
556#define CONFIG_CMDLINE_TAG
557#define CONFIG_CMDLINE_EDITING
Alison Wang86949c22014-12-03 15:00:47 +0800558
Xiubo Li1a2826f2014-11-21 17:40:57 +0800559#define CONFIG_ARMV7_NONSEC
560#define CONFIG_ARMV7_VIRT
561#define CONFIG_PEN_ADDR_BIG_ENDIAN
Mingkai Hu435acd82015-10-26 19:47:41 +0800562#define CONFIG_LAYERSCAPE_NS_ACCESS
Xiubo Li1a2826f2014-11-21 17:40:57 +0800563#define CONFIG_SMP_PEN_ADDR 0x01ee0200
564#define CONFIG_TIMER_CLK_FREQ 12500000
Xiubo Li1a2826f2014-11-21 17:40:57 +0800565
Wang Huan550e3dc2014-09-05 13:52:44 +0800566#define CONFIG_HWCONFIG
Zhuoyu Zhang03c22442015-08-17 18:55:12 +0800567#define HWCONFIG_BUFFER_SIZE 256
568
569#define CONFIG_FSL_DEVICE_DISABLE
Wang Huan550e3dc2014-09-05 13:52:44 +0800570
571#define CONFIG_BOOTDELAY 3
572
Zhao Qiang713bf942015-09-16 16:20:42 +0800573#define CONFIG_SYS_QE_FW_ADDR 0x600c0000
Zhao Qiang63e75fd2014-09-26 16:25:32 +0800574
Alison Wang8fc21212015-01-04 15:30:58 +0800575#ifdef CONFIG_LPUART
576#define CONFIG_EXTRA_ENV_SETTINGS \
577 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
Alison Wang99fe4542015-11-05 11:16:26 +0800578 "fdt_high=0xffffffff\0" \
579 "initrd_high=0xffffffff\0" \
Alison Wang8fc21212015-01-04 15:30:58 +0800580 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
581#else
Wang Huan550e3dc2014-09-05 13:52:44 +0800582#define CONFIG_EXTRA_ENV_SETTINGS \
583 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
Alison Wang99fe4542015-11-05 11:16:26 +0800584 "fdt_high=0xffffffff\0" \
585 "initrd_high=0xffffffff\0" \
Wang Huan550e3dc2014-09-05 13:52:44 +0800586 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
Alison Wang8fc21212015-01-04 15:30:58 +0800587#endif
Wang Huan550e3dc2014-09-05 13:52:44 +0800588
589/*
590 * Miscellaneous configurable options
591 */
592#define CONFIG_SYS_LONGHELP /* undef to save memory */
593#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
594#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Wang Huan550e3dc2014-09-05 13:52:44 +0800595#define CONFIG_AUTO_COMPLETE
596#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
597#define CONFIG_SYS_PBSIZE \
598 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
599#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
600#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
601
Wang Huan550e3dc2014-09-05 13:52:44 +0800602#define CONFIG_CMD_GREPENV
603#define CONFIG_CMD_MEMINFO
604#define CONFIG_CMD_MEMTEST
605#define CONFIG_SYS_MEMTEST_START 0x80000000
606#define CONFIG_SYS_MEMTEST_END 0x9fffffff
607
608#define CONFIG_SYS_LOAD_ADDR 0x82000000
Wang Huan550e3dc2014-09-05 13:52:44 +0800609
Xiubo Li660673a2014-11-21 17:40:59 +0800610#define CONFIG_LS102XA_STREAM_ID
611
Wang Huan550e3dc2014-09-05 13:52:44 +0800612/*
613 * Stack sizes
614 * The stack sizes are set up in start.S using the settings below
615 */
616#define CONFIG_STACKSIZE (30 * 1024)
617
618#define CONFIG_SYS_INIT_SP_OFFSET \
619 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
620#define CONFIG_SYS_INIT_SP_ADDR \
621 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
622
Alison Wang86949c22014-12-03 15:00:47 +0800623#ifdef CONFIG_SPL_BUILD
624#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
625#else
Wang Huan550e3dc2014-09-05 13:52:44 +0800626#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Alison Wang86949c22014-12-03 15:00:47 +0800627#endif
Wang Huan550e3dc2014-09-05 13:52:44 +0800628
629/*
630 * Environment
631 */
632#define CONFIG_ENV_OVERWRITE
633
Alison Wang86949c22014-12-03 15:00:47 +0800634#if defined(CONFIG_SD_BOOT)
635#define CONFIG_ENV_OFFSET 0x100000
636#define CONFIG_ENV_IS_IN_MMC
637#define CONFIG_SYS_MMC_ENV_DEV 0
638#define CONFIG_ENV_SIZE 0x2000
Alison Wangd612f0a2014-12-09 17:38:02 +0800639#elif defined(CONFIG_QSPI_BOOT)
640#define CONFIG_ENV_IS_IN_SPI_FLASH
641#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
642#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
643#define CONFIG_ENV_SECT_SIZE 0x10000
Alison Wang8ab967b2014-12-09 17:38:14 +0800644#elif defined(CONFIG_NAND_BOOT)
645#define CONFIG_ENV_IS_IN_NAND
646#define CONFIG_ENV_SIZE 0x2000
647#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
Alison Wang86949c22014-12-03 15:00:47 +0800648#else
Wang Huan550e3dc2014-09-05 13:52:44 +0800649#define CONFIG_ENV_IS_IN_FLASH
650#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
651#define CONFIG_ENV_SIZE 0x2000
652#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
Alison Wang86949c22014-12-03 15:00:47 +0800653#endif
Wang Huan550e3dc2014-09-05 13:52:44 +0800654
655#define CONFIG_OF_LIBFDT
656#define CONFIG_OF_BOARD_SETUP
Scott Wood6b6db0d2015-08-31 21:05:49 -0500657#define CONFIG_OF_STDOUT_VIA_ALIAS
Wang Huan550e3dc2014-09-05 13:52:44 +0800658#define CONFIG_CMD_BOOTZ
659
Ruchika Gupta4ba4a092014-10-15 11:39:06 +0530660#define CONFIG_MISC_INIT_R
661
662/* Hash command with SHA acceleration supported in hardware */
663#define CONFIG_CMD_HASH
664#define CONFIG_SHA_HW_ACCEL
665
Ruchika Guptaba474022014-10-07 15:48:47 +0530666#ifdef CONFIG_SECURE_BOOT
667#define CONFIG_CMD_BLOB
gaurav rana98cb0ef2015-03-10 14:08:50 +0530668#include <asm/fsl_secure_boot.h>
Ruchika Guptaba474022014-10-07 15:48:47 +0530669#endif
670
Wang Huan550e3dc2014-09-05 13:52:44 +0800671#endif