blob: 2ec01a5ce795656efd3ef3001682e2bb2e6e3f9f [file] [log] [blame]
Rick Chenbae2d722018-11-13 16:33:29 +08001/dts-v1/;
2
3/ {
4 #address-cells = <1>;
5 #size-cells = <1>;
6 compatible = "andestech,a25";
7 model = "andestech,a25";
8
9 aliases {
10 uart0 = &serial0;
11 spi0 = &spi;
12 };
13
14 chosen {
15 bootargs = "console=ttyS0,38400n8 debug loglevel=7";
16 stdout-path = "uart0:38400n8";
17 };
18
19 cpus {
20 #address-cells = <1>;
21 #size-cells = <0>;
22 timebase-frequency = <60000000>;
23 CPU0: cpu@0 {
24 device_type = "cpu";
25 reg = <0>;
26 status = "okay";
27 compatible = "riscv";
28 riscv,isa = "rv32imafdc";
Rick Chena1ce5312019-04-02 15:56:43 +080029 riscv,priv-major = <1>;
30 riscv,priv-minor = <10>;
Rick Chenbae2d722018-11-13 16:33:29 +080031 mmu-type = "riscv,sv32";
32 clock-frequency = <60000000>;
Rick Chena1ce5312019-04-02 15:56:43 +080033 i-cache-size = <0x8000>;
34 i-cache-line-size = <32>;
Rick Chenbae2d722018-11-13 16:33:29 +080035 d-cache-size = <0x8000>;
36 d-cache-line-size = <32>;
Rick Chena1ce5312019-04-02 15:56:43 +080037 next-level-cache = <&L2>;
Rick Chenbae2d722018-11-13 16:33:29 +080038 CPU0_intc: interrupt-controller {
39 #interrupt-cells = <1>;
40 interrupt-controller;
41 compatible = "riscv,cpu-intc";
42 };
43 };
Rick Chena1ce5312019-04-02 15:56:43 +080044 CPU1: cpu@1 {
45 device_type = "cpu";
46 reg = <1>;
47 status = "okay";
48 compatible = "riscv";
49 riscv,isa = "rv32imafdc";
50 riscv,priv-major = <1>;
51 riscv,priv-minor = <10>;
52 mmu-type = "riscv,sv32";
53 clock-frequency = <60000000>;
54 i-cache-size = <0x8000>;
55 i-cache-line-size = <32>;
56 d-cache-size = <0x8000>;
57 d-cache-line-size = <32>;
58 next-level-cache = <&L2>;
59 CPU1_intc: interrupt-controller {
60 #interrupt-cells = <1>;
61 interrupt-controller;
62 compatible = "riscv,cpu-intc";
63 };
64 };
65
66 L2: l2-cache@e0500000 {
67 compatible = "cache";
68 cache-level = <2>;
69 cache-size = <0x40000>;
70 reg = <0x0 0xe0500000 0x0 0x40000>;
71 };
Rick Chenbae2d722018-11-13 16:33:29 +080072 };
73
74 memory@0 {
75 device_type = "memory";
76 reg = <0x00000000 0x40000000>;
77 };
78
79 soc {
80 #address-cells = <1>;
81 #size-cells = <1>;
Rick Chena1ce5312019-04-02 15:56:43 +080082 compatible = "simple-bus";
Rick Chenbae2d722018-11-13 16:33:29 +080083 ranges;
84
Rick Chena1ce5312019-04-02 15:56:43 +080085 plic0: interrupt-controller@e4000000 {
86 compatible = "riscv,plic0";
87 #address-cells = <1>;
88 #interrupt-cells = <1>;
89 interrupt-controller;
90 reg = <0xe4000000 0x2000000>;
91 riscv,ndev=<71>;
92 interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 &CPU1_intc 11 &CPU1_intc 9>;
93 };
Rick Chenbae2d722018-11-13 16:33:29 +080094
Rick Chena1ce5312019-04-02 15:56:43 +080095 plic1: interrupt-controller@e6400000 {
96 compatible = "riscv,plic1";
97 #address-cells = <1>;
98 #interrupt-cells = <1>;
99 interrupt-controller;
100 reg = <0xe6400000 0x400000>;
101 riscv,ndev=<2>;
102 interrupts-extended = <&CPU0_intc 3 &CPU1_intc 3>;
103 };
Rick Chenbae2d722018-11-13 16:33:29 +0800104
Rick Chena1ce5312019-04-02 15:56:43 +0800105 plmt0@e6000000 {
106 compatible = "riscv,plmt0";
107 interrupts-extended = <&CPU0_intc 7 &CPU1_intc 7>;
Rick Chenbae2d722018-11-13 16:33:29 +0800108 reg = <0xe6000000 0x100000>;
109 };
110 };
111
112 spiclk: virt_100mhz {
113 #clock-cells = <0>;
114 compatible = "fixed-clock";
115 clock-frequency = <100000000>;
116 };
117
118 timer0: timer@f0400000 {
119 compatible = "andestech,atcpit100";
120 reg = <0xf0400000 0x1000>;
121 clock-frequency = <60000000>;
122 interrupts = <3 4>;
123 interrupt-parent = <&plic0>;
124 };
125
126 serial0: serial@f0300000 {
127 compatible = "andestech,uart16550", "ns16550a";
128 reg = <0xf0300000 0x1000>;
129 interrupts = <9 4>;
130 clock-frequency = <19660800>;
131 reg-shift = <2>;
132 reg-offset = <32>;
133 no-loopback-test = <1>;
134 interrupt-parent = <&plic0>;
135 };
136
137 mac0: mac@e0100000 {
138 compatible = "andestech,atmac100";
139 reg = <0xe0100000 0x1000>;
140 interrupts = <19 4>;
141 interrupt-parent = <&plic0>;
142 };
143
144 mmc0: mmc@f0e00000 {
145 compatible = "andestech,atfsdc010";
146 max-frequency = <100000000>;
147 clock-freq-min-max = <400000 100000000>;
148 fifo-depth = <0x10>;
149 reg = <0xf0e00000 0x1000>;
150 interrupts = <18 4>;
151 cap-sd-highspeed;
152 interrupt-parent = <&plic0>;
153 };
154
155 dma0: dma@f0c00000 {
156 compatible = "andestech,atcdmac300";
157 reg = <0xf0c00000 0x1000>;
158 interrupts = <10 4 64 4 65 4 66 4 67 4 68 4 69 4 70 4 71 4>;
159 dma-channels = <8>;
160 interrupt-parent = <&plic0>;
161 };
162
163 lcd0: lcd@e0200000 {
164 compatible = "andestech,atflcdc100";
165 reg = <0xe0200000 0x1000>;
166 interrupts = <20 4>;
167 interrupt-parent = <&plic0>;
168 };
169
170 smc0: smc@e0400000 {
171 compatible = "andestech,atfsmc020";
172 reg = <0xe0400000 0x1000>;
173 };
174
175 snd0: snd@f0d00000 {
176 compatible = "andestech,atfac97";
177 reg = <0xf0d00000 0x1000>;
178 interrupts = <17 4>;
179 interrupt-parent = <&plic0>;
180 };
181
Rick Chena1ce5312019-04-02 15:56:43 +0800182 pmu {
183 compatible = "riscv,base-pmu";
184 };
185
Rick Chenbae2d722018-11-13 16:33:29 +0800186 virtio_mmio@fe007000 {
187 interrupts = <0x17 0x4>;
188 interrupt-parent = <0x2>;
189 reg = <0xfe007000 0x1000>;
190 compatible = "virtio,mmio";
191 };
192
193 virtio_mmio@fe006000 {
194 interrupts = <0x16 0x4>;
195 interrupt-parent = <0x2>;
196 reg = <0xfe006000 0x1000>;
197 compatible = "virtio,mmio";
198 };
199
200 virtio_mmio@fe005000 {
201 interrupts = <0x15 0x4>;
202 interrupt-parent = <0x2>;
203 reg = <0xfe005000 0x1000>;
204 compatible = "virtio,mmio";
205 };
206
207 virtio_mmio@fe004000 {
208 interrupts = <0x14 0x4>;
209 interrupt-parent = <0x2>;
210 reg = <0xfe004000 0x1000>;
211 compatible = "virtio,mmio";
212 };
213
214 virtio_mmio@fe003000 {
215 interrupts = <0x13 0x4>;
216 interrupt-parent = <0x2>;
217 reg = <0xfe003000 0x1000>;
218 compatible = "virtio,mmio";
219 };
220
221 virtio_mmio@fe002000 {
222 interrupts = <0x12 0x4>;
223 interrupt-parent = <0x2>;
224 reg = <0xfe002000 0x1000>;
225 compatible = "virtio,mmio";
226 };
227
228 virtio_mmio@fe001000 {
229 interrupts = <0x11 0x4>;
230 interrupt-parent = <0x2>;
231 reg = <0xfe001000 0x1000>;
232 compatible = "virtio,mmio";
233 };
234
235 virtio_mmio@fe000000 {
236 interrupts = <0x10 0x4>;
237 interrupt-parent = <0x2>;
238 reg = <0xfe000000 0x1000>;
239 compatible = "virtio,mmio";
240 };
241
242 nor@0,0 {
243 compatible = "cfi-flash";
244 reg = <0x88000000 0x1000>;
245 bank-width = <2>;
246 device-width = <1>;
247 };
248
249 spi: spi@f0b00000 {
250 compatible = "andestech,atcspi200";
251 reg = <0xf0b00000 0x1000>;
252 #address-cells = <1>;
253 #size-cells = <0>;
254 num-cs = <1>;
255 clocks = <&spiclk>;
256 interrupts = <4 4>;
257 interrupt-parent = <&plic0>;
258 flash@0 {
259 compatible = "spi-flash";
260 spi-max-frequency = <50000000>;
261 reg = <0>;
262 spi-cpol;
263 spi-cpha;
264 };
265 };
266};