blob: ce9e28f11cc007bfb01f5da28c2e862b7aa6d46b [file] [log] [blame]
Stelian Popfa506a92008-01-31 21:15:53 +00001/*
2 * (C) Copyright 2007
Stelian Popc9e798d2011-11-01 00:00:39 +01003 * Stelian Pop <stelian@popies.net>
Stelian Popfa506a92008-01-31 21:15:53 +00004 * Lead Tech Design <www.leadtechdesign.com>
Jean-Christophe PLAGNIOL-VILLARDdc39ae92009-04-16 21:30:44 +02005 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Stelian Popfa506a92008-01-31 21:15:53 +00006 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Stelian Popfa506a92008-01-31 21:15:53 +00008 */
9#ifndef __ASM_ARM_ARCH_CLK_H__
10#define __ASM_ARM_ARCH_CLK_H__
11
12#include <asm/arch/hardware.h>
Andreas Bießmannc3a383f2011-06-12 01:49:11 +000013#include <asm/global_data.h>
Stelian Popfa506a92008-01-31 21:15:53 +000014
Andreas Bießmannc3a383f2011-06-12 01:49:11 +000015static inline unsigned long get_cpu_clk_rate(void)
16{
17 DECLARE_GLOBAL_DATA_PTR;
Simon Glassf47e6ec2012-12-13 20:48:31 +000018 return gd->arch.cpu_clk_rate_hz;
Andreas Bießmannc3a383f2011-06-12 01:49:11 +000019}
20
21static inline unsigned long get_main_clk_rate(void)
22{
23 DECLARE_GLOBAL_DATA_PTR;
Simon Glassf47e6ec2012-12-13 20:48:31 +000024 return gd->arch.main_clk_rate_hz;
Andreas Bießmannc3a383f2011-06-12 01:49:11 +000025}
26
27static inline unsigned long get_mck_clk_rate(void)
28{
29 DECLARE_GLOBAL_DATA_PTR;
Simon Glassf47e6ec2012-12-13 20:48:31 +000030 return gd->arch.mck_rate_hz;
Andreas Bießmannc3a383f2011-06-12 01:49:11 +000031}
32
33static inline unsigned long get_plla_clk_rate(void)
34{
35 DECLARE_GLOBAL_DATA_PTR;
Simon Glassf47e6ec2012-12-13 20:48:31 +000036 return gd->arch.plla_rate_hz;
Andreas Bießmannc3a383f2011-06-12 01:49:11 +000037}
38
39static inline unsigned long get_pllb_clk_rate(void)
40{
41 DECLARE_GLOBAL_DATA_PTR;
Simon Glassf47e6ec2012-12-13 20:48:31 +000042 return gd->arch.pllb_rate_hz;
Andreas Bießmannc3a383f2011-06-12 01:49:11 +000043}
44
45static inline u32 get_pllb_init(void)
46{
47 DECLARE_GLOBAL_DATA_PTR;
Simon Glassf47e6ec2012-12-13 20:48:31 +000048 return gd->arch.at91_pllb_usb_init;
Andreas Bießmannc3a383f2011-06-12 01:49:11 +000049}
Jean-Christophe PLAGNIOL-VILLARDdc39ae92009-04-16 21:30:44 +020050
Stelian Popfa506a92008-01-31 21:15:53 +000051static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
52{
Jean-Christophe PLAGNIOL-VILLARDdc39ae92009-04-16 21:30:44 +020053 return get_mck_clk_rate();
Stelian Popfa506a92008-01-31 21:15:53 +000054}
55
56static inline unsigned long get_usart_clk_rate(unsigned int dev_id)
57{
Jean-Christophe PLAGNIOL-VILLARDdc39ae92009-04-16 21:30:44 +020058 return get_mck_clk_rate();
Stelian Popfa506a92008-01-31 21:15:53 +000059}
60
Stelian Pop39cf4802008-05-09 21:57:18 +020061static inline unsigned long get_lcdc_clk_rate(unsigned int dev_id)
62{
Jean-Christophe PLAGNIOL-VILLARDdc39ae92009-04-16 21:30:44 +020063 return get_mck_clk_rate();
Stelian Pop39cf4802008-05-09 21:57:18 +020064}
65
Sedji Gaouaou22ee6472009-07-09 10:16:29 +020066static inline unsigned long get_spi_clk_rate(unsigned int dev_id)
67{
68 return get_mck_clk_rate();
69}
70
Jean-Christophe PLAGNIOL-VILLARDdc39ae92009-04-16 21:30:44 +020071static inline unsigned long get_twi_clk_rate(unsigned int dev_id)
72{
73 return get_mck_clk_rate();
74}
Stelian Pop39cf4802008-05-09 21:57:18 +020075
Reinhard Meyer1592ef82010-08-13 10:31:06 +020076static inline unsigned long get_mci_clk_rate(void)
77{
78 return get_mck_clk_rate();
79}
80
Jean-Christophe PLAGNIOL-VILLARDdc39ae92009-04-16 21:30:44 +020081int at91_clock_init(unsigned long main_clock);
Bo Shen3225f342013-05-12 22:40:54 +000082void at91_periph_clk_enable(int id);
Stelian Popfa506a92008-01-31 21:15:53 +000083#endif /* __ASM_ARM_ARCH_CLK_H__ */