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Stefan Roese5bef6fd2014-11-07 13:50:31 +01001/*
2 * Designware master SPI core controller driver
3 *
4 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
5 *
Stefan Roesea72f8022014-11-16 12:47:01 +01006 * Very loosely based on the Linux driver:
7 * drivers/spi/spi-dw.c, which is:
Stefan Roese5bef6fd2014-11-07 13:50:31 +01008 * Copyright (c) 2009, Intel Corporation.
9 *
10 * SPDX-License-Identifier: GPL-2.0
11 */
12
Eugeniy Paltsevbcdcb3e2018-03-22 13:50:46 +030013#include <asm-generic/gpio.h>
Stefan Roese5bef6fd2014-11-07 13:50:31 +010014#include <common.h>
Eugeniy Paltsev58c125b2017-12-28 15:09:03 +030015#include <clk.h>
Stefan Roese5bef6fd2014-11-07 13:50:31 +010016#include <dm.h>
17#include <errno.h>
18#include <malloc.h>
19#include <spi.h>
20#include <fdtdec.h>
21#include <linux/compat.h>
Eugeniy Paltsevc6b4f032018-03-22 13:50:43 +030022#include <linux/iopoll.h>
Stefan Roese5bef6fd2014-11-07 13:50:31 +010023#include <asm/io.h>
24
25DECLARE_GLOBAL_DATA_PTR;
26
27/* Register offsets */
28#define DW_SPI_CTRL0 0x00
29#define DW_SPI_CTRL1 0x04
30#define DW_SPI_SSIENR 0x08
31#define DW_SPI_MWCR 0x0c
32#define DW_SPI_SER 0x10
33#define DW_SPI_BAUDR 0x14
34#define DW_SPI_TXFLTR 0x18
35#define DW_SPI_RXFLTR 0x1c
36#define DW_SPI_TXFLR 0x20
37#define DW_SPI_RXFLR 0x24
38#define DW_SPI_SR 0x28
39#define DW_SPI_IMR 0x2c
40#define DW_SPI_ISR 0x30
41#define DW_SPI_RISR 0x34
42#define DW_SPI_TXOICR 0x38
43#define DW_SPI_RXOICR 0x3c
44#define DW_SPI_RXUICR 0x40
45#define DW_SPI_MSTICR 0x44
46#define DW_SPI_ICR 0x48
47#define DW_SPI_DMACR 0x4c
48#define DW_SPI_DMATDLR 0x50
49#define DW_SPI_DMARDLR 0x54
50#define DW_SPI_IDR 0x58
51#define DW_SPI_VERSION 0x5c
52#define DW_SPI_DR 0x60
53
54/* Bit fields in CTRLR0 */
55#define SPI_DFS_OFFSET 0
56
57#define SPI_FRF_OFFSET 4
58#define SPI_FRF_SPI 0x0
59#define SPI_FRF_SSP 0x1
60#define SPI_FRF_MICROWIRE 0x2
61#define SPI_FRF_RESV 0x3
62
63#define SPI_MODE_OFFSET 6
64#define SPI_SCPH_OFFSET 6
65#define SPI_SCOL_OFFSET 7
66
67#define SPI_TMOD_OFFSET 8
68#define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET)
69#define SPI_TMOD_TR 0x0 /* xmit & recv */
70#define SPI_TMOD_TO 0x1 /* xmit only */
71#define SPI_TMOD_RO 0x2 /* recv only */
72#define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */
73
74#define SPI_SLVOE_OFFSET 10
75#define SPI_SRL_OFFSET 11
76#define SPI_CFS_OFFSET 12
77
78/* Bit fields in SR, 7 bits */
Jagan Teki95e77d92015-10-23 01:01:36 +053079#define SR_MASK GENMASK(6, 0) /* cover 7 bits */
Jagan Teki431a9f02015-10-23 01:36:23 +053080#define SR_BUSY BIT(0)
81#define SR_TF_NOT_FULL BIT(1)
82#define SR_TF_EMPT BIT(2)
83#define SR_RF_NOT_EMPT BIT(3)
84#define SR_RF_FULL BIT(4)
85#define SR_TX_ERR BIT(5)
86#define SR_DCOL BIT(6)
Stefan Roese5bef6fd2014-11-07 13:50:31 +010087
Stefan Roesea72f8022014-11-16 12:47:01 +010088#define RX_TIMEOUT 1000 /* timeout in ms */
Stefan Roese5bef6fd2014-11-07 13:50:31 +010089
90struct dw_spi_platdata {
91 s32 frequency; /* Default clock frequency, -1 for none */
92 void __iomem *regs;
93};
94
95struct dw_spi_priv {
96 void __iomem *regs;
97 unsigned int freq; /* Default frequency */
98 unsigned int mode;
Eugeniy Paltsev58c125b2017-12-28 15:09:03 +030099 struct clk clk;
100 unsigned long bus_clk_rate;
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100101
Eugeniy Paltsevbcdcb3e2018-03-22 13:50:46 +0300102 struct gpio_desc cs_gpio; /* External chip-select gpio */
103
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100104 int bits_per_word;
105 u8 cs; /* chip select pin */
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100106 u8 tmode; /* TR/TO/RO/EEPROM */
107 u8 type; /* SPI/SSP/MicroWire */
108 int len;
109
110 u32 fifo_len; /* depth of the FIFO buffer */
111 void *tx;
112 void *tx_end;
113 void *rx;
114 void *rx_end;
115};
116
Eugeniy Paltsev4b5f6c52018-03-22 13:50:47 +0300117static inline u32 dw_read(struct dw_spi_priv *priv, u32 offset)
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100118{
119 return __raw_readl(priv->regs + offset);
120}
121
Eugeniy Paltsev4b5f6c52018-03-22 13:50:47 +0300122static inline void dw_write(struct dw_spi_priv *priv, u32 offset, u32 val)
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100123{
124 __raw_writel(val, priv->regs + offset);
125}
126
Eugeniy Paltsevbcdcb3e2018-03-22 13:50:46 +0300127static int request_gpio_cs(struct udevice *bus)
128{
129#if defined(CONFIG_DM_GPIO) && !defined(CONFIG_SPL_BUILD)
130 struct dw_spi_priv *priv = dev_get_priv(bus);
131 int ret;
132
133 /* External chip select gpio line is optional */
134 ret = gpio_request_by_name(bus, "cs-gpio", 0, &priv->cs_gpio, 0);
135 if (ret == -ENOENT)
136 return 0;
137
138 if (ret < 0) {
139 printf("Error: %d: Can't get %s gpio!\n", ret, bus->name);
140 return ret;
141 }
142
143 if (dm_gpio_is_valid(&priv->cs_gpio)) {
144 dm_gpio_set_dir_flags(&priv->cs_gpio,
145 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
146 }
147
148 debug("%s: used external gpio for CS management\n", __func__);
149#endif
150 return 0;
151}
152
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100153static int dw_spi_ofdata_to_platdata(struct udevice *bus)
154{
155 struct dw_spi_platdata *plat = bus->platdata;
156 const void *blob = gd->fdt_blob;
Simon Glasse160f7d2017-01-17 16:52:55 -0700157 int node = dev_of_offset(bus);
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100158
Simon Glassa821c4a2017-05-17 17:18:05 -0600159 plat->regs = (struct dw_spi *)devfdt_get_addr(bus);
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100160
161 /* Use 500KHz as a suitable default */
162 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
163 500000);
164 debug("%s: regs=%p max-frequency=%d\n", __func__, plat->regs,
165 plat->frequency);
166
Eugeniy Paltsevbcdcb3e2018-03-22 13:50:46 +0300167 return request_gpio_cs(bus);
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100168}
169
170static inline void spi_enable_chip(struct dw_spi_priv *priv, int enable)
171{
Eugeniy Paltsev4b5f6c52018-03-22 13:50:47 +0300172 dw_write(priv, DW_SPI_SSIENR, (enable ? 1 : 0));
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100173}
174
175/* Restart the controller, disable all interrupts, clean rx fifo */
176static void spi_hw_init(struct dw_spi_priv *priv)
177{
178 spi_enable_chip(priv, 0);
Eugeniy Paltsev4b5f6c52018-03-22 13:50:47 +0300179 dw_write(priv, DW_SPI_IMR, 0xff);
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100180 spi_enable_chip(priv, 1);
181
182 /*
183 * Try to detect the FIFO depth if not set by interface driver,
184 * the depth could be from 2 to 256 from HW spec
185 */
186 if (!priv->fifo_len) {
187 u32 fifo;
188
Axel Lin52091ad2015-02-26 10:45:22 +0800189 for (fifo = 1; fifo < 256; fifo++) {
Eugeniy Paltsev4b5f6c52018-03-22 13:50:47 +0300190 dw_write(priv, DW_SPI_TXFLTR, fifo);
191 if (fifo != dw_read(priv, DW_SPI_TXFLTR))
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100192 break;
193 }
194
Axel Lin52091ad2015-02-26 10:45:22 +0800195 priv->fifo_len = (fifo == 1) ? 0 : fifo;
Eugeniy Paltsev4b5f6c52018-03-22 13:50:47 +0300196 dw_write(priv, DW_SPI_TXFLTR, 0);
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100197 }
198 debug("%s: fifo_len=%d\n", __func__, priv->fifo_len);
199}
200
Eugeniy Paltsev58c125b2017-12-28 15:09:03 +0300201/*
202 * We define dw_spi_get_clk function as 'weak' as some targets
203 * (like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) don't use standard clock API
204 * and implement dw_spi_get_clk their own way in their clock manager.
205 */
206__weak int dw_spi_get_clk(struct udevice *bus, ulong *rate)
207{
208 struct dw_spi_priv *priv = dev_get_priv(bus);
209 int ret;
210
211 ret = clk_get_by_index(bus, 0, &priv->clk);
212 if (ret)
213 return ret;
214
215 ret = clk_enable(&priv->clk);
216 if (ret && ret != -ENOSYS && ret != -ENOTSUPP)
217 return ret;
218
219 *rate = clk_get_rate(&priv->clk);
220 if (!*rate)
221 goto err_rate;
222
223 debug("%s: get spi controller clk via device tree: %lu Hz\n",
224 __func__, *rate);
225
226 return 0;
227
228err_rate:
229 clk_disable(&priv->clk);
230 clk_free(&priv->clk);
231
232 return -EINVAL;
233}
234
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100235static int dw_spi_probe(struct udevice *bus)
236{
237 struct dw_spi_platdata *plat = dev_get_platdata(bus);
238 struct dw_spi_priv *priv = dev_get_priv(bus);
Eugeniy Paltsev58c125b2017-12-28 15:09:03 +0300239 int ret;
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100240
241 priv->regs = plat->regs;
242 priv->freq = plat->frequency;
243
Eugeniy Paltsev58c125b2017-12-28 15:09:03 +0300244 ret = dw_spi_get_clk(bus, &priv->bus_clk_rate);
245 if (ret)
246 return ret;
247
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100248 /* Currently only bits_per_word == 8 supported */
249 priv->bits_per_word = 8;
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100250
251 priv->tmode = 0; /* Tx & Rx */
252
253 /* Basic HW init */
254 spi_hw_init(priv);
255
256 return 0;
257}
258
259/* Return the max entries we can fill into tx fifo */
260static inline u32 tx_max(struct dw_spi_priv *priv)
261{
262 u32 tx_left, tx_room, rxtx_gap;
263
Stefan Roesea72f8022014-11-16 12:47:01 +0100264 tx_left = (priv->tx_end - priv->tx) / (priv->bits_per_word >> 3);
Eugeniy Paltsev4b5f6c52018-03-22 13:50:47 +0300265 tx_room = priv->fifo_len - dw_read(priv, DW_SPI_TXFLR);
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100266
267 /*
268 * Another concern is about the tx/rx mismatch, we
Stefan Roesea72f8022014-11-16 12:47:01 +0100269 * thought about using (priv->fifo_len - rxflr - txflr) as
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100270 * one maximum value for tx, but it doesn't cover the
271 * data which is out of tx/rx fifo and inside the
272 * shift registers. So a control from sw point of
273 * view is taken.
274 */
275 rxtx_gap = ((priv->rx_end - priv->rx) - (priv->tx_end - priv->tx)) /
Stefan Roesea72f8022014-11-16 12:47:01 +0100276 (priv->bits_per_word >> 3);
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100277
278 return min3(tx_left, tx_room, (u32)(priv->fifo_len - rxtx_gap));
279}
280
281/* Return the max entries we should read out of rx fifo */
282static inline u32 rx_max(struct dw_spi_priv *priv)
283{
Stefan Roesea72f8022014-11-16 12:47:01 +0100284 u32 rx_left = (priv->rx_end - priv->rx) / (priv->bits_per_word >> 3);
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100285
Eugeniy Paltsev4b5f6c52018-03-22 13:50:47 +0300286 return min_t(u32, rx_left, dw_read(priv, DW_SPI_RXFLR));
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100287}
288
289static void dw_writer(struct dw_spi_priv *priv)
290{
291 u32 max = tx_max(priv);
292 u16 txw = 0;
293
294 while (max--) {
295 /* Set the tx word if the transfer's original "tx" is not null */
296 if (priv->tx_end - priv->len) {
Stefan Roesea72f8022014-11-16 12:47:01 +0100297 if (priv->bits_per_word == 8)
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100298 txw = *(u8 *)(priv->tx);
299 else
300 txw = *(u16 *)(priv->tx);
301 }
Eugeniy Paltsev4b5f6c52018-03-22 13:50:47 +0300302 dw_write(priv, DW_SPI_DR, txw);
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100303 debug("%s: tx=0x%02x\n", __func__, txw);
Stefan Roesea72f8022014-11-16 12:47:01 +0100304 priv->tx += priv->bits_per_word >> 3;
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100305 }
306}
307
Eugeniy Paltsevd3d8aae2018-03-22 13:50:45 +0300308static void dw_reader(struct dw_spi_priv *priv)
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100309{
Eugeniy Paltsevd3d8aae2018-03-22 13:50:45 +0300310 u32 max = rx_max(priv);
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100311 u16 rxw;
312
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100313 while (max--) {
Eugeniy Paltsev4b5f6c52018-03-22 13:50:47 +0300314 rxw = dw_read(priv, DW_SPI_DR);
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100315 debug("%s: rx=0x%02x\n", __func__, rxw);
Stefan Roesea72f8022014-11-16 12:47:01 +0100316
Eugeniy Paltsevd3d8aae2018-03-22 13:50:45 +0300317 /* Care about rx if the transfer's original "rx" is not null */
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100318 if (priv->rx_end - priv->len) {
Stefan Roesea72f8022014-11-16 12:47:01 +0100319 if (priv->bits_per_word == 8)
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100320 *(u8 *)(priv->rx) = rxw;
321 else
322 *(u16 *)(priv->rx) = rxw;
323 }
Stefan Roesea72f8022014-11-16 12:47:01 +0100324 priv->rx += priv->bits_per_word >> 3;
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100325 }
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100326}
327
328static int poll_transfer(struct dw_spi_priv *priv)
329{
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100330 do {
331 dw_writer(priv);
Eugeniy Paltsevd3d8aae2018-03-22 13:50:45 +0300332 dw_reader(priv);
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100333 } while (priv->rx_end > priv->rx);
334
335 return 0;
336}
337
Eugeniy Paltsevbcdcb3e2018-03-22 13:50:46 +0300338static void external_cs_manage(struct udevice *dev, bool on)
339{
340#if defined(CONFIG_DM_GPIO) && !defined(CONFIG_SPL_BUILD)
341 struct dw_spi_priv *priv = dev_get_priv(dev->parent);
342
343 if (!dm_gpio_is_valid(&priv->cs_gpio))
344 return;
345
346 dm_gpio_set_value(&priv->cs_gpio, on ? 1 : 0);
347#endif
348}
349
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100350static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
351 const void *dout, void *din, unsigned long flags)
352{
353 struct udevice *bus = dev->parent;
354 struct dw_spi_priv *priv = dev_get_priv(bus);
355 const u8 *tx = dout;
356 u8 *rx = din;
357 int ret = 0;
358 u32 cr0 = 0;
Eugeniy Paltsevc6b4f032018-03-22 13:50:43 +0300359 u32 val;
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100360 u32 cs;
361
362 /* spi core configured to do 8 bit transfers */
363 if (bitlen % 8) {
364 debug("Non byte aligned SPI transfer.\n");
365 return -1;
366 }
367
Eugeniy Paltsevbcdcb3e2018-03-22 13:50:46 +0300368 /* Start the transaction if necessary. */
369 if (flags & SPI_XFER_BEGIN)
370 external_cs_manage(dev, false);
371
Stefan Roesea72f8022014-11-16 12:47:01 +0100372 cr0 = (priv->bits_per_word - 1) | (priv->type << SPI_FRF_OFFSET) |
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100373 (priv->mode << SPI_MODE_OFFSET) |
374 (priv->tmode << SPI_TMOD_OFFSET);
375
376 if (rx && tx)
377 priv->tmode = SPI_TMOD_TR;
378 else if (rx)
379 priv->tmode = SPI_TMOD_RO;
380 else
Eugeniy Paltsevfc282c72018-03-22 13:50:44 +0300381 /*
382 * In transmit only mode (SPI_TMOD_TO) input FIFO never gets
383 * any data which breaks our logic in poll_transfer() above.
384 */
385 priv->tmode = SPI_TMOD_TR;
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100386
387 cr0 &= ~SPI_TMOD_MASK;
388 cr0 |= (priv->tmode << SPI_TMOD_OFFSET);
389
Stefan Roesea72f8022014-11-16 12:47:01 +0100390 priv->len = bitlen >> 3;
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100391 debug("%s: rx=%p tx=%p len=%d [bytes]\n", __func__, rx, tx, priv->len);
392
393 priv->tx = (void *)tx;
394 priv->tx_end = priv->tx + priv->len;
395 priv->rx = rx;
396 priv->rx_end = priv->rx + priv->len;
397
398 /* Disable controller before writing control registers */
399 spi_enable_chip(priv, 0);
400
401 debug("%s: cr0=%08x\n", __func__, cr0);
402 /* Reprogram cr0 only if changed */
Eugeniy Paltsev4b5f6c52018-03-22 13:50:47 +0300403 if (dw_read(priv, DW_SPI_CTRL0) != cr0)
404 dw_write(priv, DW_SPI_CTRL0, cr0);
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100405
406 /*
407 * Configure the desired SS (slave select 0...3) in the controller
408 * The DW SPI controller will activate and deactivate this CS
409 * automatically. So no cs_activate() etc is needed in this driver.
410 */
411 cs = spi_chip_select(dev);
Eugeniy Paltsev4b5f6c52018-03-22 13:50:47 +0300412 dw_write(priv, DW_SPI_SER, 1 << cs);
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100413
414 /* Enable controller after writing control registers */
415 spi_enable_chip(priv, 1);
416
417 /* Start transfer in a polling loop */
418 ret = poll_transfer(priv);
419
Eugeniy Paltsevc6b4f032018-03-22 13:50:43 +0300420 /*
421 * Wait for current transmit operation to complete.
422 * Otherwise if some data still exists in Tx FIFO it can be
423 * silently flushed, i.e. dropped on disabling of the controller,
424 * which happens when writing 0 to DW_SPI_SSIENR which happens
425 * in the beginning of new transfer.
426 */
427 if (readl_poll_timeout(priv->regs + DW_SPI_SR, val,
428 !(val & SR_TF_EMPT) || (val & SR_BUSY),
429 RX_TIMEOUT * 1000)) {
430 ret = -ETIMEDOUT;
431 }
432
Eugeniy Paltsevbcdcb3e2018-03-22 13:50:46 +0300433 /* Stop the transaction if necessary */
434 if (flags & SPI_XFER_END)
435 external_cs_manage(dev, true);
436
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100437 return ret;
438}
439
440static int dw_spi_set_speed(struct udevice *bus, uint speed)
441{
442 struct dw_spi_platdata *plat = bus->platdata;
443 struct dw_spi_priv *priv = dev_get_priv(bus);
444 u16 clk_div;
445
446 if (speed > plat->frequency)
447 speed = plat->frequency;
448
449 /* Disable controller before writing control registers */
450 spi_enable_chip(priv, 0);
451
452 /* clk_div doesn't support odd number */
Eugeniy Paltsev58c125b2017-12-28 15:09:03 +0300453 clk_div = priv->bus_clk_rate / speed;
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100454 clk_div = (clk_div + 1) & 0xfffe;
Eugeniy Paltsev4b5f6c52018-03-22 13:50:47 +0300455 dw_write(priv, DW_SPI_BAUDR, clk_div);
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100456
457 /* Enable controller after writing control registers */
458 spi_enable_chip(priv, 1);
459
460 priv->freq = speed;
461 debug("%s: regs=%p speed=%d clk_div=%d\n", __func__, priv->regs,
462 priv->freq, clk_div);
463
464 return 0;
465}
466
467static int dw_spi_set_mode(struct udevice *bus, uint mode)
468{
469 struct dw_spi_priv *priv = dev_get_priv(bus);
470
471 /*
472 * Can't set mode yet. Since this depends on if rx, tx, or
473 * rx & tx is requested. So we have to defer this to the
474 * real transfer function.
475 */
476 priv->mode = mode;
477 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
478
479 return 0;
480}
481
482static const struct dm_spi_ops dw_spi_ops = {
483 .xfer = dw_spi_xfer,
484 .set_speed = dw_spi_set_speed,
485 .set_mode = dw_spi_set_mode,
486 /*
487 * cs_info is not needed, since we require all chip selects to be
488 * in the device tree explicitly
489 */
490};
491
492static const struct udevice_id dw_spi_ids[] = {
Marek Vasut74114862014-12-31 20:14:55 +0100493 { .compatible = "snps,dw-apb-ssi" },
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100494 { }
495};
496
497U_BOOT_DRIVER(dw_spi) = {
498 .name = "dw_spi",
499 .id = UCLASS_SPI,
500 .of_match = dw_spi_ids,
501 .ops = &dw_spi_ops,
502 .ofdata_to_platdata = dw_spi_ofdata_to_platdata,
503 .platdata_auto_alloc_size = sizeof(struct dw_spi_platdata),
504 .priv_auto_alloc_size = sizeof(struct dw_spi_priv),
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100505 .probe = dw_spi_probe,
506};