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Kumar Gala418ec852009-03-19 02:32:23 -05001/*
Dipen Dudhatd789b5f2011-01-20 16:29:35 +05302 * Copyright 2008-2011 Freescale Semiconductor, Inc.
Kumar Gala418ec852009-03-19 02:32:23 -05003 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
7 */
8
Kumar Gala83d40df2008-01-16 01:13:58 -06009#ifndef _FSL_LAW_H_
10#define _FSL_LAW_H_
11
12#include <asm/io.h>
13
Kumar Gala418ec852009-03-19 02:32:23 -050014#define LAW_EN 0x80000000
15
Kumar Gala83d40df2008-01-16 01:13:58 -060016#define SET_LAW_ENTRY(idx, a, sz, trgt) \
17 { .index = idx, .addr = a, .size = sz, .trgt_id = trgt }
18
Kumar Galaf0600542008-06-11 00:44:10 -050019#define SET_LAW(a, sz, trgt) \
20 { .index = -1, .addr = a, .size = sz, .trgt_id = trgt }
21
Kumar Gala83d40df2008-01-16 01:13:58 -060022enum law_size {
23 LAW_SIZE_4K = 0xb,
24 LAW_SIZE_8K,
25 LAW_SIZE_16K,
26 LAW_SIZE_32K,
27 LAW_SIZE_64K,
28 LAW_SIZE_128K,
29 LAW_SIZE_256K,
30 LAW_SIZE_512K,
31 LAW_SIZE_1M,
32 LAW_SIZE_2M,
33 LAW_SIZE_4M,
34 LAW_SIZE_8M,
35 LAW_SIZE_16M,
36 LAW_SIZE_32M,
37 LAW_SIZE_64M,
38 LAW_SIZE_128M,
39 LAW_SIZE_256M,
40 LAW_SIZE_512M,
41 LAW_SIZE_1G,
42 LAW_SIZE_2G,
43 LAW_SIZE_4G,
44 LAW_SIZE_8G,
45 LAW_SIZE_16G,
46 LAW_SIZE_32G,
47};
48
Li Yangde3cbd72009-12-09 14:26:08 +080049#define law_size_bits(sz) (__ilog2_u64(sz) - 1)
Becky Brucee71755f2010-06-17 11:37:23 -050050#define lawar_size(x) (1ULL << ((x & 0x3f) + 1))
Li Yangde3cbd72009-12-09 14:26:08 +080051
Kumar Gala418ec852009-03-19 02:32:23 -050052#ifdef CONFIG_FSL_CORENET
53enum law_trgt_if {
54 LAW_TRGT_IF_PCIE_1 = 0x00,
55 LAW_TRGT_IF_PCIE_2 = 0x01,
56 LAW_TRGT_IF_PCIE_3 = 0x02,
Kumar Gala9ab87d02010-04-28 04:02:21 -050057 LAW_TRGT_IF_PCIE_4 = 0x03,
Kumar Gala418ec852009-03-19 02:32:23 -050058 LAW_TRGT_IF_RIO_1 = 0x08,
59 LAW_TRGT_IF_RIO_2 = 0x09,
60
61 LAW_TRGT_IF_DDR_1 = 0x10,
62 LAW_TRGT_IF_DDR_2 = 0x11, /* 2nd controller */
York Suna4c66502012-08-17 08:22:39 +000063 LAW_TRGT_IF_DDR_3 = 0x12,
64 LAW_TRGT_IF_DDR_4 = 0x13,
Kumar Gala418ec852009-03-19 02:32:23 -050065 LAW_TRGT_IF_DDR_INTRLV = 0x14,
York Suna4c66502012-08-17 08:22:39 +000066 LAW_TRGT_IF_DDR_INTLV_34 = 0x15,
67 LAW_TRGT_IF_DDR_INTLV_123 = 0x17,
68 LAW_TRGT_IF_DDR_INTLV_1234 = 0x16,
Kumar Gala418ec852009-03-19 02:32:23 -050069 LAW_TRGT_IF_BMAN = 0x18,
70 LAW_TRGT_IF_DCSR = 0x1d,
71 LAW_TRGT_IF_LBC = 0x1f,
72 LAW_TRGT_IF_QMAN = 0x3c,
Shaveta Leekha6eaeba22013-03-25 07:40:24 +000073
74 LAW_TRGT_IF_MAPLE = 0x50,
Kumar Gala418ec852009-03-19 02:32:23 -050075};
76#define LAW_TRGT_IF_DDR LAW_TRGT_IF_DDR_1
Prabhakar Kushwaha38541732012-08-15 06:24:15 +000077#define LAW_TRGT_IF_IFC LAW_TRGT_IF_LBC
Kumar Gala418ec852009-03-19 02:32:23 -050078#else
Kumar Gala83d40df2008-01-16 01:13:58 -060079enum law_trgt_if {
80 LAW_TRGT_IF_PCI = 0x00,
81 LAW_TRGT_IF_PCI_2 = 0x01,
82#ifndef CONFIG_MPC8641
83 LAW_TRGT_IF_PCIE_1 = 0x02,
84#endif
Priyanka Jain765b0bd2013-04-04 09:31:54 +053085#if defined(CONFIG_BSC9131)
86 LAW_TRGT_IF_OCN_DSP = 0x03,
87#else
Srikanth Srinivasan8d949af2009-01-21 17:17:33 -060088#if !defined(CONFIG_MPC8572) && !defined(CONFIG_P2020)
Kumar Gala83d40df2008-01-16 01:13:58 -060089 LAW_TRGT_IF_PCIE_3 = 0x03,
90#endif
Priyanka Jain765b0bd2013-04-04 09:31:54 +053091#endif
Kumar Gala83d40df2008-01-16 01:13:58 -060092 LAW_TRGT_IF_LBC = 0x04,
93 LAW_TRGT_IF_CCSR = 0x08,
Priyanka Jain765b0bd2013-04-04 09:31:54 +053094 LAW_TRGT_IF_DSP_CCSR = 0x09,
Kumar Gala83d40df2008-01-16 01:13:58 -060095 LAW_TRGT_IF_DDR_INTRLV = 0x0b,
96 LAW_TRGT_IF_RIO = 0x0c,
Li Yangde3cbd72009-12-09 14:26:08 +080097 LAW_TRGT_IF_RIO_2 = 0x0d,
Roy Zang67a719d2011-02-03 22:14:19 -060098 LAW_TRGT_IF_DPAA_SWP_SRAM = 0x0e,
Kumar Gala83d40df2008-01-16 01:13:58 -060099 LAW_TRGT_IF_DDR = 0x0f,
100 LAW_TRGT_IF_DDR_2 = 0x16, /* 2nd controller */
York Suna4c66502012-08-17 08:22:39 +0000101 /* place holder for 3-way and 4-way interleaving */
102 LAW_TRGT_IF_DDR_3,
103 LAW_TRGT_IF_DDR_4,
104 LAW_TRGT_IF_DDR_INTLV_34,
105 LAW_TRGT_IF_DDR_INTLV_123,
106 LAW_TRGT_IF_DDR_INTLV_1234,
Kumar Gala83d40df2008-01-16 01:13:58 -0600107};
108#define LAW_TRGT_IF_DDR_1 LAW_TRGT_IF_DDR
109#define LAW_TRGT_IF_PCI_1 LAW_TRGT_IF_PCI
110#define LAW_TRGT_IF_PCIX LAW_TRGT_IF_PCI
111#define LAW_TRGT_IF_PCIE_2 LAW_TRGT_IF_PCI_2
Kumar Galaa09b9b62010-12-30 12:09:53 -0600112#define LAW_TRGT_IF_RIO_1 LAW_TRGT_IF_RIO
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530113#define LAW_TRGT_IF_IFC LAW_TRGT_IF_LBC
Kumar Gala83d40df2008-01-16 01:13:58 -0600114
115#ifdef CONFIG_MPC8641
116#define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI
117#endif
118
Srikanth Srinivasan8d949af2009-01-21 17:17:33 -0600119#if defined(CONFIG_MPC8572) || defined(CONFIG_P2020)
Kumar Gala83d40df2008-01-16 01:13:58 -0600120#define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI
121#endif
Kumar Gala418ec852009-03-19 02:32:23 -0500122#endif /* CONFIG_FSL_CORENET */
Kumar Gala83d40df2008-01-16 01:13:58 -0600123
124struct law_entry {
125 int index;
126 phys_addr_t addr;
127 enum law_size size;
128 enum law_trgt_if trgt_id;
129};
130
131extern void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id);
Kumar Galaf0600542008-06-11 00:44:10 -0500132extern int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id);
Kumar Galaba04f702008-06-10 16:16:02 -0500133extern int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id);
Kumar Galaf784e322008-08-26 15:01:28 -0500134extern int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id);
Kumar Gala418ec852009-03-19 02:32:23 -0500135extern struct law_entry find_law(phys_addr_t addr);
Kumar Gala83d40df2008-01-16 01:13:58 -0600136extern void disable_law(u8 idx);
137extern void init_laws(void);
Becky Bruceddcebcb2008-01-23 16:31:05 -0600138extern void print_laws(void);
Kumar Gala83d40df2008-01-16 01:13:58 -0600139
140/* define in board code */
141extern struct law_entry law_table[];
142extern int num_law_entries;
143#endif