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wdenkefee1702002-07-20 20:14:13 +00001/*
2 * Copyright (C) 2000 Murray Jensen <Murray.Jensen@cmst.csiro.au>
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
wdenkefee1702002-07-20 20:14:13 +00005 */
6
7#include <config.h>
8#include <command.h>
9#include <mpc8260.h>
10#include <version.h>
11
wdenkefee1702002-07-20 20:14:13 +000012#include <ppc_asm.tmpl>
13#include <ppc_defs.h>
14
15#include <asm/cache.h>
16#include <asm/mmu.h>
17
Jon Loeliger44312832007-07-09 19:06:00 -050018#if defined(CONFIG_CMD_KGDB)
wdenkefee1702002-07-20 20:14:13 +000019
20 /*
21 * cache flushing routines for kgdb
22 */
23
24 .globl kgdb_flush_cache_all
25kgdb_flush_cache_all:
26 mfspr r3, HID0
27 ori r3, r3, HID0_ICFI|HID0_DCI /* Invalidate All */
28 SYNC
29 mtspr HID0, r3
30 blr
31
32 .globl kgdb_flush_cache_range
33kgdb_flush_cache_range:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020034 li r5,CONFIG_SYS_CACHELINE_SIZE-1
wdenkefee1702002-07-20 20:14:13 +000035 andc r3,r3,r5
36 subf r4,r3,r4
37 add r4,r4,r5
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020038 srwi. r4,r4,CONFIG_SYS_CACHELINE_SHIFT
wdenkefee1702002-07-20 20:14:13 +000039 beqlr
40 mtctr r4
41 mr r6,r3
421: dcbst 0,r3
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020043 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
wdenkefee1702002-07-20 20:14:13 +000044 bdnz 1b
45 sync /* wait for dcbst's to get to ram */
46 mtctr r4
472: icbi 0,r6
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020048 addi r6,r6,CONFIG_SYS_CACHELINE_SIZE
wdenkefee1702002-07-20 20:14:13 +000049 bdnz 2b
50 SYNC
51 blr
52
Jon Loeliger068b60a2007-07-10 10:27:39 -050053#endif