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wdenk8ed96042005-01-09 23:16:25 +00001/*
2 * Basic I2C functions
3 *
4 * Copyright (c) 2004 Texas Instruments
5 *
6 * This package is free software; you can redistribute it and/or
7 * modify it under the terms of the license found in the file
8 * named COPYING that should have accompanied this file.
9 *
10 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
11 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
12 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
13 *
14 * Author: Jian Zhang jzhang@ti.com, Texas Instruments
15 *
16 * Copyright (c) 2003 Wolfgang Denk, wd@denx.de
17 * Rewritten to fit into the current U-Boot framework
18 *
19 * Adapted for OMAP2420 I2C, r-woodruff2@ti.com
20 *
21 */
22
23#include <common.h>
wdenk289f9322005-01-12 00:15:14 +000024
wdenk8ed96042005-01-09 23:16:25 +000025#include <asm/arch/i2c.h>
26#include <asm/io.h>
27
Steve Sakoman938717c2010-06-12 06:42:57 -070028#include "omap24xx_i2c.h"
29
John Rigby29565322010-12-20 18:27:51 -070030DECLARE_GLOBAL_DATA_PTR;
31
Steve Sakoman73e87472010-10-20 06:07:44 -070032#define I2C_TIMEOUT 1000
Steve Sakomand7083952010-07-19 20:31:55 -070033
Michael Jones89677b22011-07-27 14:01:55 -040034static void wait_for_bb(void);
35static u16 wait_for_pin(void);
Wolfgang Denk49a75812005-09-25 18:41:04 +020036static void flush_fifo(void);
wdenk8ed96042005-01-09 23:16:25 +000037
Dirk Behme1d2e96d2009-11-02 20:36:26 +010038static struct i2c *i2c_base = (struct i2c *)I2C_DEFAULT_BASE;
39
40static unsigned int bus_initialized[I2C_BUS_MAX];
41static unsigned int current_bus;
42
Michael Jones89677b22011-07-27 14:01:55 -040043void i2c_init(int speed, int slaveadd)
wdenk8ed96042005-01-09 23:16:25 +000044{
Tom Rix7f79dfb2009-06-28 12:52:27 -050045 int psc, fsscll, fssclh;
46 int hsscll = 0, hssclh = 0;
47 u32 scll, sclh;
Steve Sakomand7083952010-07-19 20:31:55 -070048 int timeout = I2C_TIMEOUT;
Tom Rix7f79dfb2009-06-28 12:52:27 -050049
50 /* Only handle standard, fast and high speeds */
51 if ((speed != OMAP_I2C_STANDARD) &&
52 (speed != OMAP_I2C_FAST_MODE) &&
53 (speed != OMAP_I2C_HIGH_SPEED)) {
54 printf("Error : I2C unsupported speed %d\n", speed);
55 return;
56 }
57
58 psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
59 psc -= 1;
60 if (psc < I2C_PSC_MIN) {
61 printf("Error : I2C unsupported prescalar %d\n", psc);
62 return;
63 }
64
65 if (speed == OMAP_I2C_HIGH_SPEED) {
66 /* High speed */
67
68 /* For first phase of HS mode */
69 fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK /
70 (2 * OMAP_I2C_FAST_MODE);
71
72 fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
73 fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
74 if (((fsscll < 0) || (fssclh < 0)) ||
75 ((fsscll > 255) || (fssclh > 255))) {
Andreas Müller49e9b4b2012-01-04 15:26:19 +000076 puts("Error : I2C initializing first phase clock\n");
Tom Rix7f79dfb2009-06-28 12:52:27 -050077 return;
78 }
79
80 /* For second phase of HS mode */
81 hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
82
83 hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM;
84 hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM;
85 if (((fsscll < 0) || (fssclh < 0)) ||
86 ((fsscll > 255) || (fssclh > 255))) {
Andreas Müller49e9b4b2012-01-04 15:26:19 +000087 puts("Error : I2C initializing second phase clock\n");
Tom Rix7f79dfb2009-06-28 12:52:27 -050088 return;
89 }
90
91 scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll;
92 sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh;
93
94 } else {
95 /* Standard and fast speed */
96 fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
97
98 fsscll -= I2C_FASTSPEED_SCLL_TRIM;
99 fssclh -= I2C_FASTSPEED_SCLH_TRIM;
100 if (((fsscll < 0) || (fssclh < 0)) ||
101 ((fsscll > 255) || (fssclh > 255))) {
Andreas Müller49e9b4b2012-01-04 15:26:19 +0000102 puts("Error : I2C initializing clock\n");
Tom Rix7f79dfb2009-06-28 12:52:27 -0500103 return;
104 }
105
106 scll = (unsigned int)fsscll;
107 sclh = (unsigned int)fssclh;
108 }
wdenk8ed96042005-01-09 23:16:25 +0000109
Michael Jones89677b22011-07-27 14:01:55 -0400110 if (readw(&i2c_base->con) & I2C_CON_EN) {
111 writew(0, &i2c_base->con);
112 udelay(50000);
wdenk8ed96042005-01-09 23:16:25 +0000113 }
114
Steve Sakomand7083952010-07-19 20:31:55 -0700115 writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */
116 udelay(1000);
117
118 writew(I2C_CON_EN, &i2c_base->con);
119 while (!(readw(&i2c_base->syss) & I2C_SYSS_RDONE) && timeout--) {
120 if (timeout <= 0) {
Andreas Müller49e9b4b2012-01-04 15:26:19 +0000121 puts("ERROR: Timeout in soft-reset\n");
Steve Sakomand7083952010-07-19 20:31:55 -0700122 return;
123 }
124 udelay(1000);
125 }
126
127 writew(0, &i2c_base->con);
Dirk Behme1d2e96d2009-11-02 20:36:26 +0100128 writew(psc, &i2c_base->psc);
129 writew(scll, &i2c_base->scll);
130 writew(sclh, &i2c_base->sclh);
Tom Rix7f79dfb2009-06-28 12:52:27 -0500131
wdenk8ed96042005-01-09 23:16:25 +0000132 /* own address */
Michael Jones89677b22011-07-27 14:01:55 -0400133 writew(slaveadd, &i2c_base->oa);
134 writew(I2C_CON_EN, &i2c_base->con);
Wolfgang Denk49a75812005-09-25 18:41:04 +0200135
wdenk8ed96042005-01-09 23:16:25 +0000136 /* have to enable intrrupts or OMAP i2c module doesn't work */
Michael Jones89677b22011-07-27 14:01:55 -0400137 writew(I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
Dirk Behme1d2e96d2009-11-02 20:36:26 +0100138 I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie);
Michael Jones89677b22011-07-27 14:01:55 -0400139 udelay(1000);
Wolfgang Denk49a75812005-09-25 18:41:04 +0200140 flush_fifo();
Michael Jones89677b22011-07-27 14:01:55 -0400141 writew(0xFFFF, &i2c_base->stat);
142 writew(0, &i2c_base->cnt);
Dirk Behme1d2e96d2009-11-02 20:36:26 +0100143
Heiko Schocher1724fe92010-09-17 13:10:37 +0200144 if (gd->flags & GD_FLG_RELOC)
145 bus_initialized[current_bus] = 1;
wdenk8ed96042005-01-09 23:16:25 +0000146}
147
Michael Jones89677b22011-07-27 14:01:55 -0400148static int i2c_read_byte(u8 devaddr, u8 regoffset, u8 *value)
wdenk8ed96042005-01-09 23:16:25 +0000149{
150 int i2c_error = 0;
151 u16 status;
152
153 /* wait until bus not busy */
Michael Jones89677b22011-07-27 14:01:55 -0400154 wait_for_bb();
wdenk8ed96042005-01-09 23:16:25 +0000155
156 /* one byte only */
Michael Jones89677b22011-07-27 14:01:55 -0400157 writew(1, &i2c_base->cnt);
wdenk8ed96042005-01-09 23:16:25 +0000158 /* set slave address */
Michael Jones89677b22011-07-27 14:01:55 -0400159 writew(devaddr, &i2c_base->sa);
wdenk8ed96042005-01-09 23:16:25 +0000160 /* no stop bit needed here */
Michael Jones89677b22011-07-27 14:01:55 -0400161 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
162 I2C_CON_TRX, &i2c_base->con);
wdenk8ed96042005-01-09 23:16:25 +0000163
Steve Sakomanda0cc662010-10-20 06:07:45 -0700164 /* send register offset */
165 while (1) {
166 status = wait_for_pin();
167 if (status == 0 || status & I2C_STAT_NACK) {
wdenk8ed96042005-01-09 23:16:25 +0000168 i2c_error = 1;
Steve Sakomanda0cc662010-10-20 06:07:45 -0700169 goto read_exit;
wdenk8ed96042005-01-09 23:16:25 +0000170 }
Steve Sakomanda0cc662010-10-20 06:07:45 -0700171 if (status & I2C_STAT_XRDY) {
172 /* Important: have to use byte access */
173 writeb(regoffset, &i2c_base->data);
174 writew(I2C_STAT_XRDY, &i2c_base->stat);
175 }
176 if (status & I2C_STAT_ARDY) {
177 writew(I2C_STAT_ARDY, &i2c_base->stat);
178 break;
179 }
wdenk8ed96042005-01-09 23:16:25 +0000180 }
181
Steve Sakomanda0cc662010-10-20 06:07:45 -0700182 /* set slave address */
183 writew(devaddr, &i2c_base->sa);
184 /* read one byte from slave */
185 writew(1, &i2c_base->cnt);
186 /* need stop bit here */
187 writew(I2C_CON_EN | I2C_CON_MST |
188 I2C_CON_STT | I2C_CON_STP,
189 &i2c_base->con);
190
191 /* receive data */
192 while (1) {
193 status = wait_for_pin();
194 if (status == 0 || status & I2C_STAT_NACK) {
195 i2c_error = 1;
196 goto read_exit;
wdenk8ed96042005-01-09 23:16:25 +0000197 }
wdenk8ed96042005-01-09 23:16:25 +0000198 if (status & I2C_STAT_RRDY) {
Steve Sakoman938717c2010-06-12 06:42:57 -0700199#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
Michael Jones89677b22011-07-27 14:01:55 -0400200 defined(CONFIG_OMAP44XX)
Steve Sakomanda0cc662010-10-20 06:07:45 -0700201 *value = readb(&i2c_base->data);
Dirk Behme7d264c12008-12-14 09:47:18 +0100202#else
Steve Sakomanda0cc662010-10-20 06:07:45 -0700203 *value = readw(&i2c_base->data);
Dirk Behme7d264c12008-12-14 09:47:18 +0100204#endif
Steve Sakomanda0cc662010-10-20 06:07:45 -0700205 writew(I2C_STAT_RRDY, &i2c_base->stat);
wdenk8ed96042005-01-09 23:16:25 +0000206 }
Steve Sakomanda0cc662010-10-20 06:07:45 -0700207 if (status & I2C_STAT_ARDY) {
208 writew(I2C_STAT_ARDY, &i2c_base->stat);
209 break;
wdenk8ed96042005-01-09 23:16:25 +0000210 }
211 }
Steve Sakomanda0cc662010-10-20 06:07:45 -0700212
213read_exit:
wdenk8ed96042005-01-09 23:16:25 +0000214 flush_fifo();
Michael Jones89677b22011-07-27 14:01:55 -0400215 writew(0xFFFF, &i2c_base->stat);
216 writew(0, &i2c_base->cnt);
wdenk8ed96042005-01-09 23:16:25 +0000217 return i2c_error;
218}
219
Wolfgang Denk49a75812005-09-25 18:41:04 +0200220static void flush_fifo(void)
wdenk8ed96042005-01-09 23:16:25 +0000221{ u16 stat;
wdenk082acfd2005-01-10 00:01:04 +0000222
223 /* note: if you try and read data when its not there or ready
224 * you get a bus error
225 */
Michael Jones89677b22011-07-27 14:01:55 -0400226 while (1) {
Dirk Behme1d2e96d2009-11-02 20:36:26 +0100227 stat = readw(&i2c_base->stat);
Michael Jones89677b22011-07-27 14:01:55 -0400228 if (stat == I2C_STAT_RRDY) {
Steve Sakoman938717c2010-06-12 06:42:57 -0700229#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
Michael Jones89677b22011-07-27 14:01:55 -0400230 defined(CONFIG_OMAP44XX)
Dirk Behme1d2e96d2009-11-02 20:36:26 +0100231 readb(&i2c_base->data);
Dirk Behme7d264c12008-12-14 09:47:18 +0100232#else
Dirk Behme1d2e96d2009-11-02 20:36:26 +0100233 readw(&i2c_base->data);
Dirk Behme7d264c12008-12-14 09:47:18 +0100234#endif
Michael Jones89677b22011-07-27 14:01:55 -0400235 writew(I2C_STAT_RRDY, &i2c_base->stat);
wdenk8ed96042005-01-09 23:16:25 +0000236 udelay(1000);
Michael Jones89677b22011-07-27 14:01:55 -0400237 } else
wdenk8ed96042005-01-09 23:16:25 +0000238 break;
239 }
240}
241
Michael Jones89677b22011-07-27 14:01:55 -0400242int i2c_probe(uchar chip)
wdenk8ed96042005-01-09 23:16:25 +0000243{
Steve Sakomanfbad3552010-10-20 06:07:47 -0700244 u16 status;
wdenk8ed96042005-01-09 23:16:25 +0000245 int res = 1; /* default = fail */
246
Michael Jones89677b22011-07-27 14:01:55 -0400247 if (chip == readw(&i2c_base->oa))
wdenk8ed96042005-01-09 23:16:25 +0000248 return res;
wdenk8ed96042005-01-09 23:16:25 +0000249
250 /* wait until bus not busy */
Michael Jones89677b22011-07-27 14:01:55 -0400251 wait_for_bb();
wdenk8ed96042005-01-09 23:16:25 +0000252
Nick Thompson0e579682011-04-11 22:37:41 +0000253 /* try to write one byte */
Michael Jones89677b22011-07-27 14:01:55 -0400254 writew(1, &i2c_base->cnt);
wdenk8ed96042005-01-09 23:16:25 +0000255 /* set slave address */
Michael Jones89677b22011-07-27 14:01:55 -0400256 writew(chip, &i2c_base->sa);
wdenk8ed96042005-01-09 23:16:25 +0000257 /* stop bit needed here */
Nick Thompson0e579682011-04-11 22:37:41 +0000258 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
259 I2C_CON_STP, &i2c_base->con);
wdenk8ed96042005-01-09 23:16:25 +0000260
Nick Thompson0e579682011-04-11 22:37:41 +0000261 status = wait_for_pin();
Steve Sakomanfbad3552010-10-20 06:07:47 -0700262
Nick Thompson0e579682011-04-11 22:37:41 +0000263 /* check for ACK (!NAK) */
264 if (!(status & I2C_STAT_NACK))
265 res = 0;
266
267 /* abort transfer (force idle state) */
268 writew(0, &i2c_base->con);
269
wdenk8ed96042005-01-09 23:16:25 +0000270 flush_fifo();
Michael Jones89677b22011-07-27 14:01:55 -0400271 /* don't allow any more data in... we don't want it. */
272 writew(0, &i2c_base->cnt);
Dirk Behme1d2e96d2009-11-02 20:36:26 +0100273 writew(0xFFFF, &i2c_base->stat);
wdenk8ed96042005-01-09 23:16:25 +0000274 return res;
275}
276
Michael Jones89677b22011-07-27 14:01:55 -0400277int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
wdenk8ed96042005-01-09 23:16:25 +0000278{
279 int i;
280
281 if (alen > 1) {
Michael Jones89677b22011-07-27 14:01:55 -0400282 printf("I2C read: addr len %d not supported\n", alen);
wdenk8ed96042005-01-09 23:16:25 +0000283 return 1;
284 }
285
286 if (addr + len > 256) {
Andreas Müller49e9b4b2012-01-04 15:26:19 +0000287 puts("I2C read: address out of range\n");
wdenk8ed96042005-01-09 23:16:25 +0000288 return 1;
289 }
290
291 for (i = 0; i < len; i++) {
Michael Jones89677b22011-07-27 14:01:55 -0400292 if (i2c_read_byte(chip, addr + i, &buffer[i])) {
Andreas Müller49e9b4b2012-01-04 15:26:19 +0000293 puts("I2C read: I/O error\n");
Michael Jones89677b22011-07-27 14:01:55 -0400294 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
wdenk8ed96042005-01-09 23:16:25 +0000295 return 1;
296 }
297 }
298
299 return 0;
300}
301
Michael Jones89677b22011-07-27 14:01:55 -0400302int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
wdenk8ed96042005-01-09 23:16:25 +0000303{
304 int i;
Michael Jones0607e2b2011-09-04 14:01:55 -0400305 u16 status;
306 int i2c_error = 0;
wdenk8ed96042005-01-09 23:16:25 +0000307
308 if (alen > 1) {
Michael Jones0607e2b2011-09-04 14:01:55 -0400309 printf("I2C write: addr len %d not supported\n", alen);
wdenk8ed96042005-01-09 23:16:25 +0000310 return 1;
311 }
312
313 if (addr + len > 256) {
Michael Jones0607e2b2011-09-04 14:01:55 -0400314 printf("I2C write: address 0x%x + 0x%x out of range\n",
315 addr, len);
wdenk8ed96042005-01-09 23:16:25 +0000316 return 1;
317 }
318
Michael Jones0607e2b2011-09-04 14:01:55 -0400319 /* wait until bus not busy */
320 wait_for_bb();
321
322 /* start address phase - will write regoffset + len bytes data */
323 /* TODO consider case when !CONFIG_OMAP243X/34XX/44XX */
324 writew(alen + len, &i2c_base->cnt);
325 /* set slave address */
326 writew(chip, &i2c_base->sa);
327 /* stop bit needed here */
328 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
329 I2C_CON_STP, &i2c_base->con);
330
331 /* Send address byte */
332 status = wait_for_pin();
333
334 if (status == 0 || status & I2C_STAT_NACK) {
335 i2c_error = 1;
336 printf("error waiting for i2c address ACK (status=0x%x)\n",
337 status);
338 goto write_exit;
339 }
340
341 if (status & I2C_STAT_XRDY) {
342 writeb(addr & 0xFF, &i2c_base->data);
343 writew(I2C_STAT_XRDY, &i2c_base->stat);
344 } else {
345 i2c_error = 1;
346 printf("i2c bus not ready for transmit (status=0x%x)\n",
347 status);
348 goto write_exit;
349 }
350
351 /* address phase is over, now write data */
wdenk8ed96042005-01-09 23:16:25 +0000352 for (i = 0; i < len; i++) {
Michael Jones0607e2b2011-09-04 14:01:55 -0400353 status = wait_for_pin();
354
355 if (status == 0 || status & I2C_STAT_NACK) {
356 i2c_error = 1;
357 printf("i2c error waiting for data ACK (status=0x%x)\n",
358 status);
359 goto write_exit;
360 }
361
362 if (status & I2C_STAT_XRDY) {
363 writeb(buffer[i], &i2c_base->data);
364 writew(I2C_STAT_XRDY, &i2c_base->stat);
365 } else {
366 i2c_error = 1;
367 printf("i2c bus not ready for Tx (i=%d)\n", i);
368 goto write_exit;
wdenk8ed96042005-01-09 23:16:25 +0000369 }
370 }
371
Michael Jones0607e2b2011-09-04 14:01:55 -0400372write_exit:
373 flush_fifo();
374 writew(0xFFFF, &i2c_base->stat);
375 return i2c_error;
wdenk8ed96042005-01-09 23:16:25 +0000376}
377
Michael Jones89677b22011-07-27 14:01:55 -0400378static void wait_for_bb(void)
wdenk8ed96042005-01-09 23:16:25 +0000379{
Steve Sakoman73e87472010-10-20 06:07:44 -0700380 int timeout = I2C_TIMEOUT;
wdenk8ed96042005-01-09 23:16:25 +0000381 u16 stat;
382
Michael Jonesf9a78b82011-07-14 22:09:28 +0000383 writew(0xFFFF, &i2c_base->stat); /* clear current interrupts...*/
Michael Jones89677b22011-07-27 14:01:55 -0400384 while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
385 writew(stat, &i2c_base->stat);
Steve Sakoman73e87472010-10-20 06:07:44 -0700386 udelay(1000);
wdenk8ed96042005-01-09 23:16:25 +0000387 }
388
389 if (timeout <= 0) {
Michael Jones89677b22011-07-27 14:01:55 -0400390 printf("timed out in wait_for_bb: I2C_STAT=%x\n",
391 readw(&i2c_base->stat));
wdenk8ed96042005-01-09 23:16:25 +0000392 }
Dirk Behme1d2e96d2009-11-02 20:36:26 +0100393 writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/
wdenk8ed96042005-01-09 23:16:25 +0000394}
395
Michael Jones89677b22011-07-27 14:01:55 -0400396static u16 wait_for_pin(void)
wdenk8ed96042005-01-09 23:16:25 +0000397{
398 u16 status;
Steve Sakoman73e87472010-10-20 06:07:44 -0700399 int timeout = I2C_TIMEOUT;
wdenk8ed96042005-01-09 23:16:25 +0000400
401 do {
Michael Jones89677b22011-07-27 14:01:55 -0400402 udelay(1000);
403 status = readw(&i2c_base->stat);
404 } while (!(status &
wdenk8ed96042005-01-09 23:16:25 +0000405 (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
406 I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
407 I2C_STAT_AL)) && timeout--);
408
409 if (timeout <= 0) {
Michael Jones89677b22011-07-27 14:01:55 -0400410 printf("timed out in wait_for_pin: I2C_STAT=%x\n",
411 readw(&i2c_base->stat));
Steve Sakoman73e87472010-10-20 06:07:44 -0700412 writew(0xFFFF, &i2c_base->stat);
413 status = 0;
414 }
415
wdenk8ed96042005-01-09 23:16:25 +0000416 return status;
417}
Dirk Behme1d2e96d2009-11-02 20:36:26 +0100418
419int i2c_set_bus_num(unsigned int bus)
420{
421 if ((bus < 0) || (bus >= I2C_BUS_MAX)) {
422 printf("Bad bus: %d\n", bus);
423 return -1;
424 }
425
Michael Jones89677b22011-07-27 14:01:55 -0400426#if I2C_BUS_MAX == 3
Dirk Behme1d2e96d2009-11-02 20:36:26 +0100427 if (bus == 2)
428 i2c_base = (struct i2c *)I2C_BASE3;
429 else
430#endif
431 if (bus == 1)
432 i2c_base = (struct i2c *)I2C_BASE2;
433 else
434 i2c_base = (struct i2c *)I2C_BASE1;
435
436 current_bus = bus;
437
Michael Jones89677b22011-07-27 14:01:55 -0400438 if (!bus_initialized[current_bus])
Dirk Behme1d2e96d2009-11-02 20:36:26 +0100439 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
440
441 return 0;
442}
Steve Sakoman938717c2010-06-12 06:42:57 -0700443
444int i2c_get_bus_num(void)
445{
446 return (int) current_bus;
447}