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wdenk0f8c9762002-08-19 11:57:05 +00001/*
2 * (C) Copyright 2001
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenkc837dcb2004-01-20 23:12:12 +000015 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenk0f8c9762002-08-19 11:57:05 +000016 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_IOP480 1 /* This is a IOP480 CPU */
wdenkc837dcb2004-01-20 23:12:12 +000037#define CONFIG_ADCIOP 1 /* ...on a ADCIOP board */
wdenk0f8c9762002-08-19 11:57:05 +000038
wdenkc837dcb2004-01-20 23:12:12 +000039#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
wdenk0f8c9762002-08-19 11:57:05 +000040
wdenkc837dcb2004-01-20 23:12:12 +000041#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
wdenk0f8c9762002-08-19 11:57:05 +000042
wdenkc837dcb2004-01-20 23:12:12 +000043#define CONFIG_CPUCLOCK 66
44#define CONFIG_BUSCLOCK (CONFIG_CPUCLOCK)
wdenk0f8c9762002-08-19 11:57:05 +000045
wdenkc837dcb2004-01-20 23:12:12 +000046#define CONFIG_BAUDRATE 9600
wdenk0f8c9762002-08-19 11:57:05 +000047#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
48#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */
49
wdenkc837dcb2004-01-20 23:12:12 +000050#undef CONFIG_BOOTARGS
wdenk0f8c9762002-08-19 11:57:05 +000051
52#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
53#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
54
55#undef CONFIG_WATCHDOG /* watchdog disabled */
56
wdenkc837dcb2004-01-20 23:12:12 +000057#define CONFIG_PHY_ADDR 0 /* PHY address */
wdenk0f8c9762002-08-19 11:57:05 +000058
59#define CONFIG_IPADDR 10.0.18.222
60#define CONFIG_SERVERIP 10.0.18.190
61
Jon Loeliger498ff9a2007-07-05 19:13:52 -050062/*
63 * Command line configuration.
64 */
65#include <config_cmd_default.h>
wdenk0f8c9762002-08-19 11:57:05 +000066
Jon Loeliger498ff9a2007-07-05 19:13:52 -050067#define CONFIG_CMD_DHCP
68#define CONFIG_CMD_IRQ
69#define CONFIG_CMD_ELF
70#define CONFIG_CMD_ASKENV
71
wdenk0f8c9762002-08-19 11:57:05 +000072
73/*
74 * Miscellaneous configurable options
75 */
76#define CFG_LONGHELP /* undef to save memory */
77#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger498ff9a2007-07-05 19:13:52 -050078#if defined(CONFIG_CMD_KGDB)
wdenkc837dcb2004-01-20 23:12:12 +000079#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk0f8c9762002-08-19 11:57:05 +000080#else
wdenkc837dcb2004-01-20 23:12:12 +000081#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
wdenk0f8c9762002-08-19 11:57:05 +000082#endif
83#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
84#define CFG_MAXARGS 16 /* max number of command args */
85#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
86
wdenkc837dcb2004-01-20 23:12:12 +000087#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
wdenk0f8c9762002-08-19 11:57:05 +000088
89#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
90#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
91
92/* The following table includes the supported baudrates */
wdenkc837dcb2004-01-20 23:12:12 +000093#define CFG_BAUDRATE_TABLE \
wdenk8bde7f72003-06-27 21:31:46 +000094 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200 }
wdenk0f8c9762002-08-19 11:57:05 +000095
wdenkc837dcb2004-01-20 23:12:12 +000096#define CFG_LOAD_ADDR 0x100000 /* default load address */
wdenk0f8c9762002-08-19 11:57:05 +000097
wdenkc837dcb2004-01-20 23:12:12 +000098#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk0f8c9762002-08-19 11:57:05 +000099
100#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
101
102/*-----------------------------------------------------------------------
103 * Definitions for initial stack pointer and data area (in DPRAM)
104 */
wdenkc837dcb2004-01-20 23:12:12 +0000105#define CFG_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */
wdenk0f8c9762002-08-19 11:57:05 +0000106#define CFG_INIT_RAM_END 0x0f00 /* End of used area in RAM */
107#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
108#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
109#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
110
111/*-----------------------------------------------------------------------
112 * Start addresses for the final memory configuration
113 * (Set up by the startup code)
114 * Please note that CFG_SDRAM_BASE _must_ start at 0
115 */
116#define CFG_SDRAM_BASE 0x00000000
117#define CFG_FLASH_BASE 0xFFFD0000
118#define CFG_MONITOR_BASE CFG_FLASH_BASE
119#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
120#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
121
122/*
123 * For booting Linux, the board info and command line data
124 * have to be in the first 8 MB of memory, since this is
125 * the maximum mapped by the Linux kernel during initialization.
126 */
wdenkc837dcb2004-01-20 23:12:12 +0000127#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk0f8c9762002-08-19 11:57:05 +0000128/*-----------------------------------------------------------------------
129 * FLASH organization
130 */
131#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
wdenkc837dcb2004-01-20 23:12:12 +0000132#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenk0f8c9762002-08-19 11:57:05 +0000133
134#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
135#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
136
wdenkc837dcb2004-01-20 23:12:12 +0000137#define CFG_FLASH_WORD_SIZE unsigned char /* flash word size (width) */
138#define CFG_FLASH_ADDR0 0x0AA9 /* 1st address for flash config cycles */
139#define CFG_FLASH_ADDR1 0x0556 /* 2nd address for flash config cycles */
wdenk0f8c9762002-08-19 11:57:05 +0000140/*
141 * The following defines are added for buggy IOP480 byte interface.
142 * All other boards should use the standard values (CPCI405 etc.)
143 */
wdenkc837dcb2004-01-20 23:12:12 +0000144#define CFG_FLASH_READ0 0x0002 /* 0 is standard */
145#define CFG_FLASH_READ1 0x0000 /* 1 is standard */
146#define CFG_FLASH_READ2 0x0004 /* 2 is standard */
wdenk0f8c9762002-08-19 11:57:05 +0000147
wdenkc837dcb2004-01-20 23:12:12 +0000148#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
wdenk0f8c9762002-08-19 11:57:05 +0000149
150#if 1 /* Use NVRAM for environment variables */
151/*-----------------------------------------------------------------------
152 * NVRAM organization
153 */
154#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
155#define CFG_NVRAM_BASE_ADDR 0x10000000 /* NVRAM base address */
156#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */
157#define CFG_ENV_SIZE 0x0400 /* Size of Environment vars */
158#define CFG_ENV_ADDR \
159 (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */
stroesea20b27a2004-12-16 18:05:42 +0000160#define CFG_VXWORKS_MAC_PTR (CFG_NVRAM_BASE_ADDR+0x7800) /* VxWorks eth-addr*/
wdenk0f8c9762002-08-19 11:57:05 +0000161
162#else /* Use FLASH for environment variables */
163
wdenkc837dcb2004-01-20 23:12:12 +0000164#define CFG_ENV_IS_IN_FLASH 1
165#define CFG_ENV_OFFSET 0x00010000 /* Offset of Environment Sector */
wdenk0f8c9762002-08-19 11:57:05 +0000166#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
167
168#define CFG_ENV_SECT_SIZE 0x8000 /* see README - env sector total size */
169
170#endif
171
172/*-----------------------------------------------------------------------
173 * PCI stuff
174 */
175#define CONFIG_PCI /* include pci support */
176#undef CONFIG_PCI_PNP
177
wdenkc837dcb2004-01-20 23:12:12 +0000178#define CONFIG_NET_MULTI /* Multi ethernet cards support */
wdenk0f8c9762002-08-19 11:57:05 +0000179
180#define CONFIG_TULIP
181
wdenkc837dcb2004-01-20 23:12:12 +0000182#define CFG_ETH_DEV_FN 0x0000
183#define CFG_ETH_IOBASE 0x0fff0000
wdenk0f8c9762002-08-19 11:57:05 +0000184
185/*-----------------------------------------------------------------------
186 * Cache Configuration
187 */
188#define CFG_DCACHE_SIZE 2048 /* For PLX IOP480 */
Wolfgang Denk0c8721a2005-09-23 11:05:55 +0200189#define CFG_CACHELINE_SIZE 16 /* For AMCC 401/403 CPUs */
Jon Loeliger498ff9a2007-07-05 19:13:52 -0500190#if defined(CONFIG_CMD_KGDB)
wdenk0f8c9762002-08-19 11:57:05 +0000191#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
192#endif
193
194/*
195 * Init Memory Controller:
196 *
197 * BR0/1 and OR0/1 (FLASH)
198 */
199
200#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
201#define FLASH_BASE1_PRELIM 0xFFE00000 /* FLASH bank #1 */
202
203
204/*
205 * Internal Definitions
206 *
207 * Boot Flags
208 */
209#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
210#define BOOTFLAG_WARM 0x02 /* Software reboot */
211
212#endif /* __CONFIG_H */