blob: 44972c5c09a8e678df44eef9a310f85daee33676 [file] [log] [blame]
Dipen Dudhat52f90da2011-03-22 09:27:39 +05301/*
2 * NAND boot for FSL Integrated Flash Controller, NAND Flash Control Machine
3 *
4 * Copyright 2011 Freescale Semiconductor, Inc.
5 * Author: Dipen Dudhat <dipen.dudhat@freescale.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#include <common.h>
24#include <asm/io.h>
25#include <asm/fsl_ifc.h>
26#include <linux/mtd/nand.h>
27
28static inline int is_blank(uchar *addr, int page_size)
29{
30 int i;
31
32 for (i = 0; i < page_size; i++) {
33 if (__raw_readb(&addr[i]) != 0xff)
34 return 0;
35 }
36
37 /*
38 * For the SPL, don't worry about uncorrectable errors
39 * where the main area is all FFs but shouldn't be.
40 */
41 return 1;
42}
43
44/* returns nonzero if entire page is blank */
45static inline int check_read_ecc(uchar *buf, u32 *eccstat,
46 unsigned int bufnum, int page_size)
47{
48 u32 reg = eccstat[bufnum / 4];
49 int errors = (reg >> ((3 - bufnum % 4) * 8)) & 15;
50
51 if (errors == 15) { /* uncorrectable */
52 /* Blank pages fail hw ECC checks */
53 if (is_blank(buf, page_size))
54 return 1;
55
56 puts("ecc error\n");
57 for (;;)
58 ;
59 }
60
61 return 0;
62}
63
64static inline void nand_wait(uchar *buf, int bufnum, int page_size)
65{
66 struct fsl_ifc *ifc = IFC_BASE_ADDR;
67 u32 status;
68 u32 eccstat[4];
69 int bufperpage = page_size / 512;
70 int bufnum_end, i;
71
72 bufnum *= bufperpage;
73 bufnum_end = bufnum + bufperpage - 1;
74
75 do {
76 status = in_be32(&ifc->ifc_nand.nand_evter_stat);
77 } while (!(status & IFC_NAND_EVTER_STAT_OPC));
78
79 if (status & IFC_NAND_EVTER_STAT_FTOER) {
80 puts("flash time out error\n");
81 for (;;)
82 ;
83 }
84
85 for (i = bufnum / 4; i <= bufnum_end / 4; i++)
86 eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]);
87
88 for (i = bufnum; i <= bufnum_end; i++) {
89 if (check_read_ecc(buf, eccstat, i, page_size))
90 break;
91 }
92
93 out_be32(&ifc->ifc_nand.nand_evter_stat, status);
94}
95
96static inline int bad_block(uchar *marker, int port_size)
97{
98 if (port_size == 8)
99 return __raw_readb(marker) != 0xff;
100 else
101 return __raw_readw((u16 *)marker) != 0xffff;
102}
103
104static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
105{
106 struct fsl_ifc *ifc = IFC_BASE_ADDR;
107 uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
108 int page_size;
109 int port_size;
110 int pages_per_blk;
111 int blk_size;
112 int bad_marker = 0;
113 int bufnum_mask, bufnum;
114
115 int csor, cspr;
116 int pos = 0;
117 int j = 0;
118
119 int sram_addr;
120 int pg_no;
121
122 /* Get NAND Flash configuration */
123 csor = CONFIG_SYS_NAND_CSOR;
124 cspr = CONFIG_SYS_NAND_CSPR;
125
126 if (!(csor & CSOR_NAND_ECC_DEC_EN)) {
127 /* soft ECC in SPL is unimplemented */
128 puts("WARNING: soft ECC not checked in SPL\n");
129 } else {
130 u32 hwcsor;
131
132 /* make sure board is configured with ECC on boot */
133 hwcsor = in_be32(&ifc->csor_cs[0].csor);
134 if (!(hwcsor & CSOR_NAND_ECC_DEC_EN))
135 puts("WARNING: ECC not checked in SPL, "
136 "check board cfg\n");
137 }
138
139 port_size = (cspr & CSPR_PORT_SIZE_16) ? 16 : 8;
140
141 if (csor & CSOR_NAND_PGS_4K) {
142 page_size = 4096;
143 bufnum_mask = 1;
144 } else if (csor & CSOR_NAND_PGS_2K) {
145 page_size = 2048;
146 bufnum_mask = 3;
147 } else {
148 page_size = 512;
149 bufnum_mask = 15;
150
151 if (port_size == 8)
152 bad_marker = 5;
153 }
154
155 pages_per_blk =
156 32 << ((csor & CSOR_NAND_PB_MASK) >> CSOR_NAND_PB_SHIFT);
157
158 blk_size = pages_per_blk * page_size;
159
160 /* Open Full SRAM mapping for spare are access */
161 out_be32(&ifc->ifc_nand.ncfgr, 0x0);
162
163 /* Clear Boot events */
164 out_be32(&ifc->ifc_nand.nand_evter_stat, 0xffffffff);
165
166 /* Program FIR/FCR for Large/Small page */
167 if (page_size > 512) {
168 out_be32(&ifc->ifc_nand.nand_fir0,
169 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
170 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
171 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
172 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
173 (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP4_SHIFT));
174 out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
175
176 out_be32(&ifc->ifc_nand.nand_fcr0,
177 (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
178 (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
179 } else {
180 out_be32(&ifc->ifc_nand.nand_fir0,
181 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
182 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
183 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
184 (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP3_SHIFT));
185 out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
186
187 out_be32(&ifc->ifc_nand.nand_fcr0,
188 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
189 }
190
191 /* Program FBCR = 0 for full page read */
192 out_be32(&ifc->ifc_nand.nand_fbcr, 0);
193
194 /* Read and copy u-boot on SDRAM from NAND device, In parallel
195 * check for Bad block if found skip it and read continue to
196 * next Block
197 */
198 while (pos < uboot_size) {
199 int i = 0;
200 do {
201 pg_no = offs / page_size;
202 bufnum = pg_no & bufnum_mask;
203 sram_addr = bufnum * page_size * 2;
204
205 out_be32(&ifc->ifc_nand.row0, pg_no);
206 out_be32(&ifc->ifc_nand.col0, 0);
207 /* start read */
208 out_be32(&ifc->ifc_nand.nandseq_strt,
209 IFC_NAND_SEQ_STRT_FIR_STRT);
210
211 /* wait for read to complete */
212 nand_wait(&buf[sram_addr], bufnum, page_size);
213
214 /*
215 * If either of the first two pages are marked bad,
216 * continue to the next block.
217 */
218 if (i++ < 2 &&
219 bad_block(&buf[sram_addr + page_size + bad_marker],
220 port_size)) {
221 puts("skipping\n");
222 offs = (offs + blk_size) & ~(blk_size - 1);
223 pos &= ~(blk_size - 1);
224 break;
225 }
226
227 for (j = 0; j < page_size; j++)
228 dst[pos + j] = __raw_readb(&buf[sram_addr + j]);
229
230 pos += page_size;
231 offs += page_size;
232 } while ((offs & (blk_size - 1)) && (pos < uboot_size));
233 }
234}
235
236/*
237 * Main entrypoint for NAND Boot. It's necessary that SDRAM is already
238 * configured and available since this code loads the main U-boot image
239 * from NAND into SDRAM and starts from there.
240 */
241void nand_boot(void)
242{
243 __attribute__((noreturn)) void (*uboot)(void);
244
245 /*
246 * Load U-Boot image from NAND into RAM
247 */
248 nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
249 (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
250
251#ifdef CONFIG_NAND_ENV_DST
252 nand_load(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
253 (uchar *)CONFIG_NAND_ENV_DST);
254
255#ifdef CONFIG_ENV_OFFSET_REDUND
256 nand_load(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
257 (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
258#endif
259#endif
260
261 /*
262 * Jump to U-Boot image
263 */
264 /*
265 * Clean d-cache and invalidate i-cache, to
266 * make sure that no stale data is executed.
267 */
268 flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
269 uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
270 uboot();
271}