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Aubrey Li26bf7de2007-03-19 01:24:52 +08001/*
2 * U-boot - Configuration file for BF537 STAMP board
3 */
4
Mike Frysingercf6f4692008-06-01 09:09:48 -04005#ifndef __CONFIG_BF537_STAMP_H__
6#define __CONFIG_BF537_STAMP_H__
Aubrey Li26bf7de2007-03-19 01:24:52 +08007
Mike Frysingerf7ce12c2008-02-18 05:26:48 -05008#include <asm/blackfin-config-pre.h>
9
Aubrey Li26bf7de2007-03-19 01:24:52 +080010
11/*
Mike Frysingercf6f4692008-06-01 09:09:48 -040012 * Processor Settings
Aubrey Li26bf7de2007-03-19 01:24:52 +080013 */
Mike Frysingercf6f4692008-06-01 09:09:48 -040014#define CONFIG_BFIN_CPU bf537-0.2
15#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
16
17
18/*
19 * Clock Settings
20 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
21 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
22 */
23/* CONFIG_CLKIN_HZ is any value in Hz */
24#define CONFIG_CLKIN_HZ 25000000
25/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
26/* 1 = CLKIN / 2 */
27#define CONFIG_CLKIN_HALF 0
28/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
29/* 1 = bypass PLL */
30#define CONFIG_PLL_BYPASS 0
31/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
32/* Values can range from 0-63 (where 0 means 64) */
33#define CONFIG_VCO_MULT 20
34/* CCLK_DIV controls the core clock divider */
35/* Values can be 1, 2, 4, or 8 ONLY */
36#define CONFIG_CCLK_DIV 1
37/* SCLK_DIV controls the system clock divider */
38/* Values can range from 1-15 */
Mike Frysingerf82caac2008-12-08 16:16:11 -050039#define CONFIG_SCLK_DIV 4
Mike Frysingercf6f4692008-06-01 09:09:48 -040040
41
42/*
43 * Memory Settings
44 */
45#define CONFIG_MEM_ADD_WDTH 10
46#define CONFIG_MEM_SIZE 64
47
48#define CONFIG_EBIU_SDRRC_VAL 0x306
49#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
50
51#define CONFIG_EBIU_AMGCTL_VAL 0xFF
52#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
53#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
54
Mike Frysinger6f5fd562009-01-21 20:47:12 -050055#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
Mike Frysingercf6f4692008-06-01 09:09:48 -040056#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
57
Aubrey Li26bf7de2007-03-19 01:24:52 +080058
59/*
60 * Network Settings
61 */
Mike Frysingercf6f4692008-06-01 09:09:48 -040062#ifndef __ADSPBF534__
63#define ADI_CMDS_NETWORK 1
64#define CONFIG_BFIN_MAC
Aubrey Li26bf7de2007-03-19 01:24:52 +080065#define CONFIG_NETCONSOLE 1
66#define CONFIG_NET_MULTI 1
Mike Frysingercf6f4692008-06-01 09:09:48 -040067#endif
68#define CONFIG_HOSTNAME bf537-stamp
69/* Uncomment next line to use fixed MAC address */
70/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
Jon Loeliger079a1362007-07-10 10:12:10 -050071
72
73/*
Mike Frysingercf6f4692008-06-01 09:09:48 -040074 * Flash Settings
Jon Loeligerba2351f2007-07-04 22:31:49 -050075 */
Mike Frysingercf6f4692008-06-01 09:09:48 -040076#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077#define CONFIG_SYS_FLASH_BASE 0x20000000
Mike Frysingercf6f4692008-06-01 09:09:48 -040078#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020079#define CONFIG_SYS_FLASH_PROTECTION
80#define CONFIG_SYS_MAX_FLASH_BANKS 1
Mike Frysingercf6f4692008-06-01 09:09:48 -040081/* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
82#define CONFIG_SYS_MAX_FLASH_SECT 71
Aubrey Li26bf7de2007-03-19 01:24:52 +080083
Aubrey Li26bf7de2007-03-19 01:24:52 +080084
Mike Frysingercf6f4692008-06-01 09:09:48 -040085/*
86 * SPI Settings
87 */
88#define CONFIG_BFIN_SPI
89#define CONFIG_ENV_SPI_MAX_HZ 30000000
90#define CONFIG_SF_DEFAULT_HZ 30000000
91#define CONFIG_SPI_FLASH
92#define CONFIG_SPI_FLASH_ATMEL
93#define CONFIG_SPI_FLASH_SPANSION
94#define CONFIG_SPI_FLASH_STMICRO
95#define CONFIG_SPI_FLASH_WINBOND
96
97
98/*
99 * Env Storage Settings
100 */
Mike Frysinger9171fc82008-03-30 15:46:13 -0400101#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
Mike Frysingercf6f4692008-06-01 09:09:48 -0400102#define CONFIG_ENV_IS_IN_SPI_FLASH
103#define CONFIG_ENV_OFFSET 0x4000
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200104#define CONFIG_ENV_SIZE 0x2000
Mike Frysingercf6f4692008-06-01 09:09:48 -0400105#define CONFIG_ENV_SECT_SIZE 0x2000
106#else
107#define CONFIG_ENV_IS_IN_FLASH
108#define CONFIG_ENV_OFFSET 0x4000
109#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
110#define CONFIG_ENV_SIZE 0x2000
111#define CONFIG_ENV_SECT_SIZE 0x2000
112#endif
113#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
Aubrey Li26bf7de2007-03-19 01:24:52 +0800114#define ENV_IS_EMBEDDED
Mike Frysingercf6f4692008-06-01 09:09:48 -0400115#else
116#define ENV_IS_EMBEDDED_CUSTOM
117#endif
Aubrey Li26bf7de2007-03-19 01:24:52 +0800118
Aubrey Li26bf7de2007-03-19 01:24:52 +0800119
120/*
Mike Frysingercf6f4692008-06-01 09:09:48 -0400121 * I2C Settings
Aubrey Li26bf7de2007-03-19 01:24:52 +0800122 */
Mike Frysingercf6f4692008-06-01 09:09:48 -0400123#define CONFIG_BFIN_TWI_I2C 1
124#define CONFIG_HARD_I2C 1
125#define CONFIG_SYS_I2C_SPEED 50000
126#define CONFIG_SYS_I2C_SLAVE 0
Aubrey Li26bf7de2007-03-19 01:24:52 +0800127
Aubrey Li26bf7de2007-03-19 01:24:52 +0800128
129/*
Mike Frysingercf6f4692008-06-01 09:09:48 -0400130 * SPI_MMC Settings
Aubrey Li26bf7de2007-03-19 01:24:52 +0800131 */
Mike Frysingercf6f4692008-06-01 09:09:48 -0400132#define CONFIG_MMC
133#define CONFIG_BFIN_SPI_MMC
134
135
136/*
137 * NAND Settings
138 */
139/* #define CONFIG_BF537_NAND */
140#ifdef CONFIG_BF537_NAND
141# define CONFIG_CMD_NAND
142#endif
Aubrey Li26bf7de2007-03-19 01:24:52 +0800143
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_NAND_ADDR 0x20212000
145#define CONFIG_SYS_NAND_BASE CONFIG_SYS_NAND_ADDR
146#define CONFIG_SYS_MAX_NAND_DEVICE 1
Aubrey Li26bf7de2007-03-19 01:24:52 +0800147#define SECTORSIZE 512
148#define ADDR_COLUMN 1
149#define ADDR_PAGE 2
150#define ADDR_COLUMN_PAGE 3
151#define NAND_ChipID_UNKNOWN 0x00
152#define NAND_MAX_FLOORS 1
Aubrey Li26bf7de2007-03-19 01:24:52 +0800153#define BFIN_NAND_READY PF3
154
Mike Frysingercf6f4692008-06-01 09:09:48 -0400155#define NAND_WAIT_READY(nand) \
156 do { \
157 int timeout = 0; \
158 while (!(*pPORTFIO & PF3)) \
159 if (timeout++ > 100000) \
160 break; \
Aubrey Li26bf7de2007-03-19 01:24:52 +0800161 } while (0)
162
Mike Frysingercf6f4692008-06-01 09:09:48 -0400163#define BFIN_NAND_CLE (1 << 2) /* A2 -> Command Enable */
164#define BFIN_NAND_ALE (1 << 1) /* A1 -> Address Enable */
165#define WRITE_NAND_COMMAND(d, adr) bfin_write8(adr | BFIN_NAND_CLE, d)
166#define WRITE_NAND_ADDRESS(d, adr) bfin_write8(adr | BFIN_NAND_ALE, d)
167#define WRITE_NAND(d, adr) bfin_write8(adr, d)
168#define READ_NAND(adr) bfin_read8(adr)
Aubrey Li26bf7de2007-03-19 01:24:52 +0800169
Aubrey Li26bf7de2007-03-19 01:24:52 +0800170
171/*
Mike Frysingercf6f4692008-06-01 09:09:48 -0400172 * CF-CARD IDE-HDD Support
Aubrey Li26bf7de2007-03-19 01:24:52 +0800173 */
Mike Frysingercf6f4692008-06-01 09:09:48 -0400174/* #define CONFIG_BFIN_TRUE_IDE */ /* Add CF flash card support */
175/* #define CONFIG_BFIN_CF_IDE */ /* Add CF flash card support */
176/* #define CONFIG_BFIN_HDD_IDE */ /* Add IDE Disk Drive (HDD) support */
Aubrey Li26bf7de2007-03-19 01:24:52 +0800177
Mike Frysingercf6f4692008-06-01 09:09:48 -0400178#if defined(CONFIG_BFIN_CF_IDE) || \
179 defined(CONFIG_BFIN_HDD_IDE) || \
180 defined(CONFIG_BFIN_TRUE_IDE)
181# define CONFIG_BFIN_IDE 1
182# define CONFIG_CMD_IDE
183#endif
Aubrey Li26bf7de2007-03-19 01:24:52 +0800184
Aubrey Li26bf7de2007-03-19 01:24:52 +0800185#if defined(CONFIG_BFIN_IDE)
186
187#define CONFIG_DOS_PARTITION 1
188/*
189 * IDE/ATA stuff
190 */
191#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
192#undef CONFIG_IDE_LED /* no led for ide supported */
193#undef CONFIG_IDE_RESET /* no reset for ide supported */
194
Mike Frysingercf6f4692008-06-01 09:09:48 -0400195#define CONFIG_SYS_IDE_MAXBUS 1
196#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS * 1)
Aubrey Li26bf7de2007-03-19 01:24:52 +0800197
Mike Frysingercf6f4692008-06-01 09:09:48 -0400198#undef CONFIG_EBIU_AMBCTL1_VAL
199#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC3FFC3
Aubrey Li26bf7de2007-03-19 01:24:52 +0800200
201#define CONFIG_CF_ATASEL_DIS 0x20311800
202#define CONFIG_CF_ATASEL_ENA 0x20311802
203
204#if defined(CONFIG_BFIN_TRUE_IDE)
205/*
206 * Note that these settings aren't for the most part used in include/ata.h
207 * when all of the ATA registers are setup
208 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_ATA_BASE_ADDR 0x2031C000
210#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
Mike Frysingercf6f4692008-06-01 09:09:48 -0400211#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */
212#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */
213#define CONFIG_SYS_ATA_ALT_OFFSET 0x001C /* alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_ATA_STRIDE 2 /* CF.A0 --> Blackfin.Ax */
Aubrey Li26bf7de2007-03-19 01:24:52 +0800215
Mike Frysingercf6f4692008-06-01 09:09:48 -0400216#elif defined(CONFIG_BFIN_CF_IDE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_ATA_BASE_ADDR 0x20211800
218#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
Mike Frysingercf6f4692008-06-01 09:09:48 -0400219#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* data I/O */
220#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* normal register accesses */
221#define CONFIG_SYS_ATA_ALT_OFFSET 0x000E /* alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_ATA_STRIDE 1 /* CF.A0 --> Blackfin.Ax */
Aubrey Li26bf7de2007-03-19 01:24:52 +0800223
Mike Frysingercf6f4692008-06-01 09:09:48 -0400224#elif defined(CONFIG_BFIN_HDD_IDE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_ATA_BASE_ADDR 0x20314000
226#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
Mike Frysingercf6f4692008-06-01 09:09:48 -0400227#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */
228#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */
229#define CONFIG_SYS_ATA_ALT_OFFSET 0x001C /* alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A1 */
Aubrey Li26bf7de2007-03-19 01:24:52 +0800231#undef CONFIG_SCLK_DIV
232#define CONFIG_SCLK_DIV 8
Mike Frysingercf6f4692008-06-01 09:09:48 -0400233#endif
Aubrey Li26bf7de2007-03-19 01:24:52 +0800234
Mike Frysingercf6f4692008-06-01 09:09:48 -0400235#endif
236
237
238/*
239 * Misc Settings
240 */
241#define CONFIG_MISC_INIT_R
242#define CONFIG_RTC_BFIN
243#define CONFIG_UART_CONSOLE 0
244
245/* #define CONFIG_BF537_STAMP_LEDCMD 1 */
246
247/* Define if want to do post memory test */
248#undef CONFIG_POST
249#ifdef CONFIG_POST
250#define FLASH_START_POST_BLOCK 11 /* Should > = 11 */
251#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */
252#endif
253
254
255/*
256 * Pull in common ADI header for remaining command/environment setup
257 */
258#include <configs/bfin_adi_common.h>
Aubrey Li26bf7de2007-03-19 01:24:52 +0800259
Mike Frysinger9171fc82008-03-30 15:46:13 -0400260#include <asm/blackfin-config-post.h>
261
Aubrey Li26bf7de2007-03-19 01:24:52 +0800262#endif