blob: c36141a0076a374434bea674e0b92a4507d1b028 [file] [log] [blame]
Rafal Jaworowski8993e542007-07-27 14:43:59 +02001/*
Wolfgang Denk3b74e7e2009-05-16 10:47:45 +02002 * (C) Copyright 2007-2009 DENX Software Engineering
Rafal Jaworowski8993e542007-07-27 14:43:59 +02003 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02004 * SPDX-License-Identifier: GPL-2.0+
Rafal Jaworowski8993e542007-07-27 14:43:59 +02005 */
6
7/*
Wolfgang Denk72601d02009-05-16 10:47:41 +02008 * MPC5121ADS board configuration file
Rafal Jaworowski8993e542007-07-27 14:43:59 +02009 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
Wolfgang Denk72601d02009-05-16 10:47:41 +020014#define CONFIG_MPC5121ADS 1
Anatolij Gustschin10e99d82014-10-21 13:46:59 +020015
Rafal Jaworowski8993e542007-07-27 14:43:59 +020016/*
Wolfgang Denk72601d02009-05-16 10:47:41 +020017 * Memory map for the MPC5121ADS board:
Rafal Jaworowski8993e542007-07-27 14:43:59 +020018 *
19 * 0x0000_0000 - 0x0FFF_FFFF DDR RAM (256 MB)
20 * 0x3000_0000 - 0x3001_FFFF SRAM (128 KB)
21 * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB)
22 * 0x8200_0000 - 0x8200_001F CPLD (32 B)
John Rigby5f91db72008-02-26 09:38:14 -070023 * 0x8400_0000 - 0x82FF_FFFF PCI I/O space (16 MB)
24 * 0xA000_0000 - 0xAFFF_FFFF PCI memory space (256 MB)
25 * 0xB000_0000 - 0xBFFF_FFFF PCI memory mapped I/O space (256 MB)
Rafal Jaworowski8993e542007-07-27 14:43:59 +020026 * 0xFC00_0000 - 0xFFFF_FFFF NOR Boot FLASH (64 MB)
27 */
28
29/*
30 * High Level Configuration Options
31 */
32#define CONFIG_E300 1 /* E300 Family */
York Sun0e1bad42008-05-05 10:20:01 -050033
Wolfgang Denk2ae18242010-10-06 09:05:45 +020034#define CONFIG_SYS_TEXT_BASE 0xFFF00000
35
York Sun0e1bad42008-05-05 10:20:01 -050036/* video */
Timur Tabi7d3053f2011-02-15 17:09:19 -060037#ifdef CONFIG_FSL_DIU_FB
38#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR + 0x2100)
Timur Tabie69e5202010-08-31 19:56:43 -050039#define CONFIG_CMD_BMP
Timur Tabie69e5202010-08-31 19:56:43 -050040#define CONFIG_VIDEO_LOGO
41#define CONFIG_VIDEO_BMP_LOGO
York Sun0e1bad42008-05-05 10:20:01 -050042#endif
Rafal Jaworowski8993e542007-07-27 14:43:59 +020043
John Rigby5f91db72008-02-26 09:38:14 -070044/* CONFIG_PCI is defined at config time */
Rafal Jaworowski8993e542007-07-27 14:43:59 +020045
Wolfgang Denk72601d02009-05-16 10:47:41 +020046#ifdef CONFIG_MPC5121ADS_REV2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020047#define CONFIG_SYS_MPC512X_CLKIN 66000000 /* in Hz */
Martha Marxf31c49d2008-05-29 14:23:25 -040048#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049#define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */
Martha Marxf31c49d2008-05-29 14:23:25 -040050#endif
Rafal Jaworowski8993e542007-07-27 14:43:59 +020051
52#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
York Sun0e1bad42008-05-05 10:20:01 -050053#define CONFIG_MISC_INIT_R
Rafal Jaworowski8993e542007-07-27 14:43:59 +020054
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020055#define CONFIG_SYS_IMMR 0x80000000
Rafal Jaworowski8993e542007-07-27 14:43:59 +020056
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
58#define CONFIG_SYS_MEMTEST_END 0x00400000
Rafal Jaworowski8993e542007-07-27 14:43:59 +020059
60/*
61 * DDR Setup - manually set all parameters as there's no SPD etc.
62 */
Wolfgang Denk72601d02009-05-16 10:47:41 +020063#ifdef CONFIG_MPC5121ADS_REV2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020064#define CONFIG_SYS_DDR_SIZE 256 /* MB */
Martha Marxf31c49d2008-05-29 14:23:25 -040065#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066#define CONFIG_SYS_DDR_SIZE 512 /* MB */
Martha Marxf31c49d2008-05-29 14:23:25 -040067#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020068#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
69#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
Anatolij Gustschinb9947bb2010-04-24 19:27:08 +020070#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000
Rafal Jaworowski8993e542007-07-27 14:43:59 +020071
Anatolij Gustschin5d937e82010-04-24 19:27:07 +020072#define CONFIG_SYS_IOCTRL_MUX_DDR 0x00000036
73
Rafal Jaworowski8993e542007-07-27 14:43:59 +020074/* DDR Controller Configuration
Wolfgang Denkb1b54e32007-08-02 21:27:46 +020075 *
76 * SYS_CFG:
77 * [31:31] MDDRC Soft Reset: Diabled
78 * [30:30] DRAM CKE pin: Enabled
79 * [29:29] DRAM CLK: Enabled
80 * [28:28] Command Mode: Enabled (For initialization only)
81 * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
82 * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
83 * [20:19] Read Test: DON'T USE
84 * [18:18] Self Refresh: Enabled
85 * [17:17] 16bit Mode: Disabled
86 * [16:13] Ready Delay: 2
87 * [12:12] Half DQS Delay: Disabled
88 * [11:11] Quarter DQS Delay: Disabled
89 * [10:08] Write Delay: 2
90 * [07:07] Early ODT: Disabled
91 * [06:06] On DIE Termination: Disabled
92 * [05:05] FIFO Overflow Clear: DON'T USE here
93 * [04:04] FIFO Underflow Clear: DON'T USE here
94 * [03:03] FIFO Overflow Pending: DON'T USE here
95 * [02:02] FIFO Underlfow Pending: DON'T USE here
96 * [01:01] FIFO Overlfow Enabled: Enabled
97 * [00:00] FIFO Underflow Enabled: Enabled
98 * TIME_CFG0
99 * [31:16] DRAM Refresh Time: 0 CSB clocks
100 * [15:8] DRAM Command Time: 0 CSB clocks
101 * [07:00] DRAM Precharge Time: 0 CSB clocks
102 * TIME_CFG1
103 * [31:26] DRAM tRFC:
104 * [25:21] DRAM tWR1:
105 * [20:17] DRAM tWRT1:
106 * [16:11] DRAM tDRR:
107 * [10:05] DRAM tRC:
108 * [04:00] DRAM tRAS:
109 * TIME_CFG2
110 * [31:28] DRAM tRCD:
111 * [27:23] DRAM tFAW:
112 * [22:19] DRAM tRTW1:
113 * [18:15] DRAM tCCD:
114 * [14:10] DRAM tRTP:
115 * [09:05] DRAM tRP:
116 * [04:00] DRAM tRPA
117 */
Wolfgang Denk72601d02009-05-16 10:47:41 +0200118#ifdef CONFIG_MPC5121ADS_REV2
Martha M Stan054197b2009-09-21 14:07:14 -0400119#define CONFIG_SYS_MDDRC_SYS_CFG 0xE8604A00
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_MDDRC_TIME_CFG1 0x54EC1168
121#define CONFIG_SYS_MDDRC_TIME_CFG2 0x35210864
Martha Marxf31c49d2008-05-29 14:23:25 -0400122#else
Martha M Stan054197b2009-09-21 14:07:14 -0400123#define CONFIG_SYS_MDDRC_SYS_CFG 0xEA804A00
124#define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168
125#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864
Martha Marxf31c49d2008-05-29 14:23:25 -0400126#endif
Martha M Stan054197b2009-09-21 14:07:14 -0400127#define CONFIG_SYS_MDDRC_TIME_CFG0 0x06183D2E
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200128
Martha M Stana5aa3992009-09-21 14:08:00 -0400129#define CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA 0xEA802B00
130#define CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA 0x690e1189
131#define CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA 0x35310864
132
Martha M Stan054197b2009-09-21 14:07:14 -0400133#define CONFIG_SYS_DDRCMD_NOP 0x01380000
134#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400
135#define CONFIG_SYS_DDRCMD_EM2 0x01020000
136#define CONFIG_SYS_DDRCMD_EM3 0x01030000
137#define CONFIG_SYS_DDRCMD_EN_DLL 0x01010000
138#define CONFIG_SYS_DDRCMD_RFSH 0x01080000
Martha M Stana5aa3992009-09-21 14:08:00 -0400139
140#define DDRCMD_EMR_OCD(pr, ohm) ( \
141 (1 << 24) | /* MDDRC Command Request */ \
142 (1 << 16) | /* MODE Reg BA[2:0] */ \
143 (0 << 12) | /* Outputs 0=Enabled */ \
144 (0 << 11) | /* RDQS */ \
145 (1 << 10) | /* DQS# */ \
146 (pr << 7) | /* OCD prog 7=deflt,0=exit */ \
147 /* ODT Rtt[1:0] 0=0,1=75,2=150,3=50 */ \
148 ((ohm & 0x2) << 5)| /* Rtt1 */ \
149 (0 << 3) | /* additive posted CAS# */ \
150 ((ohm & 0x1) << 2)| /* Rtt0 */ \
151 (0 << 0) | /* Output Drive Strength */ \
152 (0 << 0)) /* DLL Enable 0=Normal */
153
154#define CONFIG_SYS_DDRCMD_OCD_DEFAULT DDRCMD_EMR_OCD(7, 0)
155#define CONFIG_SYS_ELPIDA_OCD_EXIT DDRCMD_EMR_OCD(0, 0)
156
157#define DDRCMD_MODE_REG(cas, wr) ( \
158 (1 << 24) | /* MDDRC Command Request */ \
159 (0 << 16) | /* MODE Reg BA[2:0] */ \
160 ((wr-1) << 9)| /* Write Recovery */ \
161 (cas << 4) | /* CAS */ \
162 (0 << 3) | /* Burst Type:0=Sequential,1=Interleaved */ \
163 (2 << 0)) /* 4 or 8 Burst Length:0x2=4 0x3=8 */
164
165#define CONFIG_SYS_MICRON_INIT_DEV_OP DDRCMD_MODE_REG(3, 3)
166#define CONFIG_SYS_ELPIDA_INIT_DEV_OP DDRCMD_MODE_REG(4, 4)
167#define CONFIG_SYS_ELPIDA_RES_DLL (DDRCMD_MODE_REG(4, 4) | (1 << 8))
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200168
169/* DDR Priority Manager Configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777
171#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000
172#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001
173#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC
174#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA
175#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666
176#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555
177#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444
178#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444
179#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555
180#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558
181#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111
182#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122
183#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa
184#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa
185#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666
186#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666
187#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111
188#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111
189#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111
190#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111
191#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111
192#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200193
194/*
195 * NOR FLASH on the Local Bus
196 */
Martha Marxf31c49d2008-05-29 14:23:25 -0400197#undef CONFIG_BKUP_FLASH
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200199#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Martha Marxf31c49d2008-05-29 14:23:25 -0400200#ifdef CONFIG_BKUP_FLASH
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */
202#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* max flash size in bytes */
Martha Marxf31c49d2008-05-29 14:23:25 -0400203#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* start of FLASH */
205#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* max flash size in bytes */
Martha Marxf31c49d2008-05-29 14:23:25 -0400206#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
208#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
209#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
210#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200211
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#undef CONFIG_SYS_FLASH_CHECKSUM
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200213
214/*
Stefan Roese229549a2009-06-09 16:57:47 +0200215 * NAND FLASH
Wolfgang Denk13946922009-06-14 20:58:50 +0200216 * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only)
Stefan Roese229549a2009-06-09 16:57:47 +0200217 */
Wolfgang Denk7d4450a2009-06-14 20:58:53 +0200218#define CONFIG_CMD_NAND /* enable NAND support */
219#define CONFIG_JFFS2_NAND /* with JFFS2 on it */
Stefan Roese229549a2009-06-09 16:57:47 +0200220#define CONFIG_NAND_MPC5121_NFC
221#define CONFIG_SYS_NAND_BASE 0x40000000
222
223#define CONFIG_SYS_MAX_NAND_DEVICE 2
Stefan Roese229549a2009-06-09 16:57:47 +0200224#define CONFIG_SYS_NAND_SELECT_DEVICE /* driver supports mutipl. chips */
225
226/*
227 * Configuration parameters for MPC5121 NAND driver
228 */
229#define CONFIG_FSL_NFC_WIDTH 1
230#define CONFIG_FSL_NFC_WRITE_SIZE 2048
231#define CONFIG_FSL_NFC_SPARE_SIZE 64
232#define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
233
234/*
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200235 * CPLD registers area is really only 32 bytes in size, but the smallest possible LP
236 * window is 64KB
237 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define CONFIG_SYS_CPLD_BASE 0x82000000
239#define CONFIG_SYS_CPLD_SIZE 0x00010000 /* 64 KB */
Anatolij Gustschin676c6692013-02-08 00:03:44 +0000240#define CONFIG_SYS_CS2_START CONFIG_SYS_CPLD_BASE
241#define CONFIG_SYS_CS2_SIZE CONFIG_SYS_CPLD_SIZE
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200242
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_SRAM_BASE 0x30000000
244#define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200245
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_CS0_CFG 0x05059310 /* ALE active low, data size 4bytes */
247#define CONFIG_SYS_CS2_CFG 0x05059010 /* ALE active low, data size 1byte */
248#define CONFIG_SYS_CS_ALETIMING 0x00000005 /* Use alternative CS timing for CS0 and CS2 */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200249
250/* Use SRAM for initial stack */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200252#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_SRAM_SIZE /* Size of used area in RAM */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200253
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200254#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200256
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200257#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of monitor */
Stefan Roese229549a2009-06-09 16:57:47 +0200258#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
York Sun0e1bad42008-05-05 10:20:01 -0500259#ifdef CONFIG_FSL_DIU_FB
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
York Sun0e1bad42008-05-05 10:20:01 -0500261#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
York Sun0e1bad42008-05-05 10:20:01 -0500263#endif
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200264
265/*
266 * Serial Port
267 */
268#define CONFIG_CONS_INDEX 1
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200269
270/*
271 * Serial console configuration
272 */
273#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */
Marek Vasutbfb31272012-09-16 16:07:24 +0200274#define CONFIG_SYS_PSC3
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200275#if CONFIG_PSC_CONSOLE != 3
276#error CONFIG_PSC_CONSOLE must be 3
277#endif
278#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_BAUDRATE_TABLE \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200280 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
281
282#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE
283#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR
284#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE
285#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR
286
287#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200288
John Rigby5f91db72008-02-26 09:38:14 -0700289/*
Anatolij Gustschine5f53862013-02-08 00:03:45 +0000290 * Clocks in use
291 */
292#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
293 CLOCK_SCCR1_DDR_EN | \
294 CLOCK_SCCR1_FEC_EN | \
295 CLOCK_SCCR1_LPC_EN | \
296 CLOCK_SCCR1_NFC_EN | \
297 CLOCK_SCCR1_PATA_EN | \
298 CLOCK_SCCR1_PCI_EN | \
299 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
300 CLOCK_SCCR1_PSCFIFO_EN | \
301 CLOCK_SCCR1_TPR_EN)
302
303#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_DIU_EN | \
304 CLOCK_SCCR2_I2C_EN | \
305 CLOCK_SCCR2_MEM_EN | \
306 CLOCK_SCCR2_SPDIF_EN | \
307 CLOCK_SCCR2_USB1_EN | \
308 CLOCK_SCCR2_USB2_EN)
309
310/*
John Rigby5f91db72008-02-26 09:38:14 -0700311 * PCI
312 */
313#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000314#define CONFIG_PCI_INDIRECT_BRIDGE
John Rigby5f91db72008-02-26 09:38:14 -0700315
316/*
317 * General PCI
318 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200319#define CONFIG_SYS_PCI_MEM_BASE 0xA0000000
320#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
321#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
322#define CONFIG_SYS_PCI_MMIO_BASE (CONFIG_SYS_PCI_MEM_BASE + CONFIG_SYS_PCI_MEM_SIZE)
323#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
324#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
325#define CONFIG_SYS_PCI_IO_BASE 0x00000000
326#define CONFIG_SYS_PCI_IO_PHYS 0x84000000
327#define CONFIG_SYS_PCI_IO_SIZE 0x01000000 /* 16M */
John Rigby5f91db72008-02-26 09:38:14 -0700328
John Rigby5f91db72008-02-26 09:38:14 -0700329#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
330
331#endif
332
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200333/* I2C */
334#define CONFIG_HARD_I2C /* I2C with hardware support */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200335#define CONFIG_I2C_MULTI_BUS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
337#define CONFIG_SYS_I2C_SLAVE 0x7F
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200338#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200340#endif
341
342/*
Martha Marxabfbd0ae2009-01-26 10:45:07 -0700343 * IIM - IC Identification Module
344 */
Benoît Thébaudeau83306922013-04-23 10:17:42 +0000345#undef CONFIG_FSL_IIM
Martha Marxabfbd0ae2009-01-26 10:45:07 -0700346
347/*
Grzegorz Bernacki80020122007-10-09 13:58:24 +0200348 * EEPROM configuration
349 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200350#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */
351#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Atmel: AT24C32A-10TQ-2.7 */
352#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */
353#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32-Byte Page Write Mode */
Grzegorz Bernacki80020122007-10-09 13:58:24 +0200354
355/*
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200356 * Ethernet configuration
357 */
358#define CONFIG_MPC512x_FEC 1
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200359#define CONFIG_PHY_ADDR 0x1
360#define CONFIG_MII 1 /* MII PHY management */
Martha Marxf31c49d2008-05-29 14:23:25 -0400361#define CONFIG_FEC_AN_TIMEOUT 1
John Rigbyef11df62008-08-05 17:38:57 -0600362#define CONFIG_HAS_ETH0
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200363
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200364/*
365 * Configure on-board RTC
366 */
Martha Marxf31c49d2008-05-29 14:23:25 -0400367#define CONFIG_RTC_M41T62 /* use M41T62 rtc via i2 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200368#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200369
370/*
Damien Dusha29c6fbe2010-10-14 15:27:06 +0200371 * USB Support
372 */
Damien Dusha29c6fbe2010-10-14 15:27:06 +0200373
374#if defined(CONFIG_CMD_USB)
375#define CONFIG_USB_EHCI /* Enable EHCI Support */
376#define CONFIG_USB_EHCI_FSL /* On a FSL platform */
377#define CONFIG_EHCI_MMIO_BIG_ENDIAN /* With big-endian regs */
378#define CONFIG_EHCI_DESC_BIG_ENDIAN
379#define CONFIG_EHCI_IS_TDI
Damien Dusha29c6fbe2010-10-14 15:27:06 +0200380#endif
381
382/*
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200383 * Environment
384 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200385#define CONFIG_ENV_IS_IN_FLASH 1
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200386/* This has to be a multiple of the Flash sector size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200387#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200388#define CONFIG_ENV_SIZE 0x2000
Martha Marxf31c49d2008-05-29 14:23:25 -0400389#ifdef CONFIG_BKUP_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200390#define CONFIG_ENV_SECT_SIZE 0x20000 /* one sector (256K) for env */
Martha Marxf31c49d2008-05-29 14:23:25 -0400391#else
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200392#define CONFIG_ENV_SECT_SIZE 0x40000 /* one sector (256K) for env */
Martha Marxf31c49d2008-05-29 14:23:25 -0400393#endif
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200394
395/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200396#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
397#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200398
399#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200400#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200401
Wolfgang Denk7d4450a2009-06-14 20:58:53 +0200402#define CONFIG_CMD_DATE
Wolfgang Denk7d4450a2009-06-14 20:58:53 +0200403#define CONFIG_CMD_EEPROM
Wolfgang Denk7d4450a2009-06-14 20:58:53 +0200404#define CONFIG_CMD_IDE
405#define CONFIG_CMD_JFFS2
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200406#define CONFIG_CMD_REGINFO
Wolfgang Denk7d4450a2009-06-14 20:58:53 +0200407
Martha Marxabfbd0ae2009-01-26 10:45:07 -0700408#undef CONFIG_CMD_FUSE
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200409
410#if defined(CONFIG_PCI)
411#define CONFIG_CMD_PCI
412#endif
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200413
Wolfgang Denk7d4450a2009-06-14 20:58:53 +0200414/*
415 * Dynamic MTD partition support
416 */
417#define CONFIG_CMD_MTDPARTS
418#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
419#define CONFIG_FLASH_CFI_MTD
420#define MTDIDS_DEFAULT "nor0=fc000000.flash,nand0=mpc5121.nand"
421
422/*
423 * NOR flash layout:
424 *
425 * FC000000 - FEABFFFF 42.75 MiB User Data
426 * FEAC0000 - FFABFFFF 16 MiB Root File System
427 * FFAC0000 - FFEBFFFF 4 MiB Linux Kernel
428 * FFEC0000 - FFEFFFFF 256 KiB Device Tree
429 * FFF00000 - FFFFFFFF 1 MiB U-Boot (up to 512 KiB) and 2 x * env
430 *
431 * NAND flash layout: one big partition
432 */
433#define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:43776k(user)," \
434 "16m(rootfs)," \
435 "4m(kernel)," \
436 "256k(dtb)," \
437 "1m(u-boot);" \
438 "mpc5121.nand:-(data)"
439
Damien Dusha29c6fbe2010-10-14 15:27:06 +0200440#if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2) || defined(CONFIG_CMD_USB)
441
Ralph Kondziella70a4da42009-01-26 12:34:36 -0700442#define CONFIG_DOS_PARTITION
443#define CONFIG_MAC_PARTITION
444#define CONFIG_ISO_PARTITION
Damien Dusha29c6fbe2010-10-14 15:27:06 +0200445
Damien Dusha29c6fbe2010-10-14 15:27:06 +0200446#define CONFIG_SUPPORT_VFAT
447
Ralph Kondziella70a4da42009-01-26 12:34:36 -0700448#endif /* defined(CONFIG_CMD_IDE) */
449
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200450/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200451 * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
452 * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200453 * to 0xFFFF, watchdog timeouts after about 64s. For details refer
454 * to chapter 36 of the MPC5121e Reference Manual.
455 */
Wolfgang Denk66ffb182008-01-15 17:22:28 +0100456/* #define CONFIG_WATCHDOG */ /* enable watchdog */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200457#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200458
459 /*
460 * Miscellaneous configurable options
461 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200462#define CONFIG_SYS_LONGHELP /* undef to save memory */
463#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200464
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200465#ifdef CONFIG_CMD_KGDB
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200466 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200467#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200468 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200469#endif
470
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200471#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
472#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
473#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200474
475/*
476 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700477 * have to be in the first 256 MB of memory, since this is
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200478 * the maximum mapped by the Linux kernel during initialization.
479 */
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700480#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200481
482/* Cache Configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200483#define CONFIG_SYS_DCACHE_SIZE 32768
484#define CONFIG_SYS_CACHELINE_SIZE 32
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200485#ifdef CONFIG_CMD_KGDB
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200486#define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200487#endif
488
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200489#define CONFIG_SYS_HID0_INIT 0x000000000
Wolfgang Denke2b66fe2009-03-26 10:00:57 +0100490#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | HID0_ICE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200491#define CONFIG_SYS_HID2 HID2_HBE
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200492
Becky Bruce31d82672008-05-08 19:02:12 -0500493#define CONFIG_HIGH_BATS 1 /* High BATs supported */
494
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200495#ifdef CONFIG_CMD_KGDB
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200496#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200497#endif
498
499/*
500 * Environment Configuration
501 */
Wolfgang Denk66ffb182008-01-15 17:22:28 +0100502#define CONFIG_TIMESTAMP
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200503
Wolfgang Denk72601d02009-05-16 10:47:41 +0200504#define CONFIG_HOSTNAME mpc5121ads
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000505#define CONFIG_BOOTFILE "mpc5121ads/uImage"
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000506#define CONFIG_ROOTPATH "/opt/eldk/ppc_6xx"
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200507
Wolfgang Denk8d103072008-01-13 23:37:50 +0100508#define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200509
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200510#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
511
512#define CONFIG_BAUDRATE 115200
513
514#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk5b0b2b62008-03-03 12:36:49 +0100515 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200516 "echo"
517
518#define CONFIG_EXTRA_ENV_SETTINGS \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100519 "u-boot_addr_r=200000\0" \
Wolfgang Denk51e46e22008-08-26 15:01:28 +0200520 "kernel_addr_r=600000\0" \
521 "fdt_addr_r=880000\0" \
522 "ramdisk_addr_r=900000\0" \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100523 "u-boot_addr=FFF00000\0" \
Wolfgang Denk7d4450a2009-06-14 20:58:53 +0200524 "kernel_addr=FFAC0000\0" \
Wolfgang Denk51e46e22008-08-26 15:01:28 +0200525 "fdt_addr=FFEC0000\0" \
Wolfgang Denk7d4450a2009-06-14 20:58:53 +0200526 "ramdisk_addr=FEAC0000\0" \
Wolfgang Denk72601d02009-05-16 10:47:41 +0200527 "ramdiskfile=mpc5121ads/uRamdisk\0" \
528 "u-boot=mpc5121ads/u-boot.bin\0" \
529 "bootfile=mpc5121ads/uImage\0" \
530 "fdtfile=mpc5121ads/mpc5121ads.dtb\0" \
Wolfgang Denk51e46e22008-08-26 15:01:28 +0200531 "rootpath=/opt/eldk/ppc_6xx\n" \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200532 "netdev=eth0\0" \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100533 "consdev=ttyPSC0\0" \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200534 "nfsargs=setenv bootargs root=/dev/nfs rw " \
535 "nfsroot=${serverip}:${rootpath}\0" \
536 "ramargs=setenv bootargs root=/dev/ram rw\0" \
537 "addip=setenv bootargs ${bootargs} " \
538 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
539 ":${hostname}:${netdev}:off panic=1\0" \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100540 "addtty=setenv bootargs ${bootargs} " \
541 "console=${consdev},${baudrate}\0" \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200542 "flash_nfs=run nfsargs addip addtty;" \
Detlev Zundela99715b2008-04-18 14:50:01 +0200543 "bootm ${kernel_addr} - ${fdt_addr}\0" \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200544 "flash_self=run ramargs addip addtty;" \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100545 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
546 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
547 "tftp ${fdt_addr_r} ${fdtfile};" \
548 "run nfsargs addip addtty;" \
549 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
550 "net_self=tftp ${kernel_addr_r} ${bootfile};" \
551 "tftp ${ramdisk_addr_r} ${ramdiskfile};" \
Detlev Zundela99715b2008-04-18 14:50:01 +0200552 "tftp ${fdt_addr_r} ${fdtfile};" \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100553 "run ramargs addip addtty;" \
Wolfgang Denk5b0b2b62008-03-03 12:36:49 +0100554 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
Detlev Zundela99715b2008-04-18 14:50:01 +0200555 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100556 "update=protect off ${u-boot_addr} +${filesize};" \
557 "era ${u-boot_addr} +${filesize};" \
558 "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \
559 "upd=run load update\0" \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200560 ""
561
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200562#define CONFIG_BOOTCOMMAND "run flash_self"
563
John Rigbyef11df62008-08-05 17:38:57 -0600564#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1
Grzegorz Bernacki281ff9a2008-01-08 17:16:15 +0100565
566#define OF_CPU "PowerPC,5121@0"
John Rigbyef11df62008-08-05 17:38:57 -0600567#define OF_SOC_COMPAT "fsl,mpc5121-immr"
Grzegorz Bernacki281ff9a2008-01-08 17:16:15 +0100568#define OF_TBCLK (bd->bi_busfreq / 4)
John Rigbyac915282008-01-30 13:36:57 -0700569#define OF_STDOUT_PATH "/soc@80000000/serial@11300"
Grzegorz Bernacki281ff9a2008-01-08 17:16:15 +0100570
Ralph Kondziella70a4da42009-01-26 12:34:36 -0700571/*-----------------------------------------------------------------------
572 * IDE/ATA stuff
573 *-----------------------------------------------------------------------
574 */
575
576#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
577#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
578#undef CONFIG_IDE_LED /* LED for IDE not supported */
579
580#define CONFIG_IDE_RESET /* reset for IDE supported */
581#define CONFIG_IDE_PREINIT
582
583#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
584#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */
585
586#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
Wolfgang Denk3b74e7e2009-05-16 10:47:45 +0200587#define CONFIG_SYS_ATA_BASE_ADDR get_pata_base()
Ralph Kondziella70a4da42009-01-26 12:34:36 -0700588
589/* Offset for data I/O RefMan MPC5121EE Table 28-10 */
590#define CONFIG_SYS_ATA_DATA_OFFSET (0x00A0)
591
592/* Offset for normal register accesses */
593#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
594
595/* Offset for alternate registers RefMan MPC5121EE Table 28-23 */
596#define CONFIG_SYS_ATA_ALT_OFFSET (0x00D8)
597
598/* Interval between registers */
599#define CONFIG_SYS_ATA_STRIDE 4
600
Wolfgang Denk3b74e7e2009-05-16 10:47:45 +0200601#define ATA_BASE_ADDR get_pata_base()
Ralph Kondziella70a4da42009-01-26 12:34:36 -0700602
603/*
604 * Control register bit definitions
605 */
606#define FSL_ATA_CTRL_FIFO_RST_B 0x80000000
607#define FSL_ATA_CTRL_ATA_RST_B 0x40000000
608#define FSL_ATA_CTRL_FIFO_TX_EN 0x20000000
609#define FSL_ATA_CTRL_FIFO_RCV_EN 0x10000000
610#define FSL_ATA_CTRL_DMA_PENDING 0x08000000
611#define FSL_ATA_CTRL_DMA_ULTRA 0x04000000
612#define FSL_ATA_CTRL_DMA_WRITE 0x02000000
613#define FSL_ATA_CTRL_IORDY_EN 0x01000000
614
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200615#endif /* __CONFIG_H */