Mingkai Hu | f3a8e2b | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2015 Freescale Semiconductor |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | #ifndef __LS1043A_COMMON_H |
| 8 | #define __LS1043A_COMMON_H |
| 9 | |
| 10 | #define CONFIG_REMAKE_ELF |
| 11 | #define CONFIG_FSL_LAYERSCAPE |
Mingkai Hu | f3a8e2b | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 12 | #define CONFIG_LS1043A |
Hou Zhiqiang | 831c068 | 2015-10-26 19:47:57 +0800 | [diff] [blame] | 13 | #define CONFIG_MP |
Mingkai Hu | f3a8e2b | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 14 | #define CONFIG_SYS_FSL_CLK |
| 15 | #define CONFIG_GICV2 |
| 16 | |
| 17 | #include <asm/arch/config.h> |
Mingkai Hu | f3a8e2b | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 18 | |
| 19 | /* Link Definitions */ |
| 20 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) |
| 21 | |
| 22 | #define CONFIG_SUPPORT_RAW_INITRD |
| 23 | |
| 24 | #define CONFIG_SKIP_LOWLEVEL_INIT |
| 25 | #define CONFIG_BOARD_EARLY_INIT_F 1 |
| 26 | |
Mingkai Hu | f3a8e2b | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 27 | #define CONFIG_VERY_BIG_RAM |
| 28 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 |
| 29 | #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 |
| 30 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
Shaohui Xie | e994ddd | 2015-11-23 15:23:48 +0800 | [diff] [blame] | 31 | #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL |
Mingkai Hu | f3a8e2b | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 32 | |
Hou Zhiqiang | 831c068 | 2015-10-26 19:47:57 +0800 | [diff] [blame] | 33 | #define CPU_RELEASE_ADDR secondary_boot_func |
| 34 | |
Mingkai Hu | f3a8e2b | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 35 | /* Generic Timer Definitions */ |
| 36 | #define COUNTER_FREQUENCY 25000000 /* 25MHz */ |
| 37 | |
| 38 | /* Size of malloc() pool */ |
| 39 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) |
| 40 | |
| 41 | /* Serial Port */ |
| 42 | #define CONFIG_CONS_INDEX 1 |
Mingkai Hu | f3a8e2b | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 43 | #define CONFIG_SYS_NS16550_SERIAL |
| 44 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| 45 | #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) |
| 46 | |
| 47 | #define CONFIG_BAUDRATE 115200 |
| 48 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
| 49 | |
Gong Qianyu | c7ca8b0 | 2015-10-26 19:47:56 +0800 | [diff] [blame] | 50 | /* SD boot SPL */ |
| 51 | #ifdef CONFIG_SD_BOOT |
| 52 | #define CONFIG_SPL_FRAMEWORK |
| 53 | #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" |
| 54 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" |
Gong Qianyu | c7ca8b0 | 2015-10-26 19:47:56 +0800 | [diff] [blame] | 55 | |
| 56 | #define CONFIG_SPL_TEXT_BASE 0x10000000 |
| 57 | #define CONFIG_SPL_MAX_SIZE 0x1d000 |
| 58 | #define CONFIG_SPL_STACK 0x1001e000 |
| 59 | #define CONFIG_SPL_PAD_TO 0x1d000 |
| 60 | |
| 61 | #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ |
| 62 | CONFIG_SYS_MONITOR_LEN) |
| 63 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 |
| 64 | #define CONFIG_SPL_BSS_START_ADDR 0x80100000 |
| 65 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 |
| 66 | #define CONFIG_SYS_MONITOR_LEN 0xa0000 |
| 67 | #endif |
| 68 | |
Gong Qianyu | 3ad4472 | 2015-10-26 19:47:53 +0800 | [diff] [blame] | 69 | /* NAND SPL */ |
| 70 | #ifdef CONFIG_NAND_BOOT |
| 71 | #define CONFIG_SPL_PBL_PAD |
| 72 | #define CONFIG_SPL_FRAMEWORK |
| 73 | #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" |
| 74 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" |
Gong Qianyu | 3ad4472 | 2015-10-26 19:47:53 +0800 | [diff] [blame] | 75 | #define CONFIG_SPL_TEXT_BASE 0x10000000 |
| 76 | #define CONFIG_SPL_MAX_SIZE 0x1a000 |
| 77 | #define CONFIG_SPL_STACK 0x1001d000 |
| 78 | #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE |
| 79 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE |
| 80 | #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 |
| 81 | #define CONFIG_SPL_BSS_START_ADDR 0x80100000 |
| 82 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 |
| 83 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 |
| 84 | #define CONFIG_SYS_MONITOR_LEN 0xa0000 |
| 85 | #endif |
| 86 | |
Mingkai Hu | f3a8e2b | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 87 | /* IFC */ |
Qianyu Gong | b0f20ca | 2016-01-25 15:16:07 +0800 | [diff] [blame] | 88 | #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) |
Mingkai Hu | f3a8e2b | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 89 | #define CONFIG_FSL_IFC |
| 90 | /* |
| 91 | * CONFIG_SYS_FLASH_BASE has the final address (core view) |
| 92 | * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) |
| 93 | * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address |
| 94 | * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting |
| 95 | */ |
| 96 | #define CONFIG_SYS_FLASH_BASE 0x60000000 |
| 97 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE |
| 98 | #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 |
| 99 | |
| 100 | #ifndef CONFIG_SYS_NO_FLASH |
| 101 | #define CONFIG_FLASH_CFI_DRIVER |
| 102 | #define CONFIG_SYS_FLASH_CFI |
| 103 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
| 104 | #define CONFIG_SYS_FLASH_QUIET_TEST |
| 105 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
| 106 | #endif |
Gong Qianyu | 166ef1e | 2016-01-25 15:16:06 +0800 | [diff] [blame] | 107 | #endif |
Mingkai Hu | f3a8e2b | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 108 | |
| 109 | /* I2C */ |
Mingkai Hu | f3a8e2b | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 110 | #define CONFIG_SYS_I2C |
| 111 | #define CONFIG_SYS_I2C_MXC |
| 112 | #define CONFIG_SYS_I2C_MXC_I2C1 |
| 113 | #define CONFIG_SYS_I2C_MXC_I2C2 |
| 114 | #define CONFIG_SYS_I2C_MXC_I2C3 |
| 115 | #define CONFIG_SYS_I2C_MXC_I2C4 |
| 116 | |
| 117 | /* PCIe */ |
Mingkai Hu | f3a8e2b | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 118 | #define CONFIG_PCIE1 /* PCIE controller 1 */ |
| 119 | #define CONFIG_PCIE2 /* PCIE controller 2 */ |
| 120 | #define CONFIG_PCIE3 /* PCIE controller 3 */ |
| 121 | #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ |
| 122 | #define FSL_PCIE_COMPAT "fsl,ls1043a-pcie" |
| 123 | |
| 124 | #define CONFIG_SYS_PCI_64BIT |
| 125 | |
| 126 | #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 |
| 127 | #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ |
| 128 | #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 |
| 129 | #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ |
| 130 | |
| 131 | #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 |
| 132 | #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 |
| 133 | #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ |
| 134 | |
| 135 | #define CONFIG_SYS_PCIE_MEM_BUS 0x40000000 |
| 136 | #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000 |
| 137 | #define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */ |
| 138 | |
| 139 | #ifdef CONFIG_PCI |
| 140 | #define CONFIG_NET_MULTI |
Mingkai Hu | f3a8e2b | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 141 | #define CONFIG_E1000 |
| 142 | #define CONFIG_PCI_SCAN_SHOW |
| 143 | #define CONFIG_CMD_PCI |
| 144 | #endif |
| 145 | |
| 146 | /* Command line configuration */ |
Mingkai Hu | f3a8e2b | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 147 | #define CONFIG_CMD_ENV |
Wenbin Song | 6ffc490 | 2016-07-15 17:17:46 +0800 | [diff] [blame] | 148 | #define CONFIG_MENU |
| 149 | #define CONFIG_CMD_PXE |
Mingkai Hu | f3a8e2b | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 150 | |
Yangbo Lu | 8ef0d5c | 2015-10-26 19:47:55 +0800 | [diff] [blame] | 151 | /* MMC */ |
| 152 | #define CONFIG_MMC |
| 153 | #ifdef CONFIG_MMC |
Yangbo Lu | 8ef0d5c | 2015-10-26 19:47:55 +0800 | [diff] [blame] | 154 | #define CONFIG_FSL_ESDHC |
| 155 | #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 |
| 156 | #define CONFIG_GENERIC_MMC |
| 157 | #define CONFIG_DOS_PARTITION |
| 158 | #endif |
| 159 | |
Gong Qianyu | e0579a5 | 2016-01-25 15:16:05 +0800 | [diff] [blame] | 160 | /* DSPI */ |
| 161 | #define CONFIG_FSL_DSPI |
| 162 | #ifdef CONFIG_FSL_DSPI |
Gong Qianyu | e0579a5 | 2016-01-25 15:16:05 +0800 | [diff] [blame] | 163 | #define CONFIG_DM_SPI_FLASH |
| 164 | #define CONFIG_SPI_FLASH_STMICRO /* cs0 */ |
| 165 | #define CONFIG_SPI_FLASH_SST /* cs1 */ |
| 166 | #define CONFIG_SPI_FLASH_EON /* cs2 */ |
Qianyu Gong | b0f20ca | 2016-01-25 15:16:07 +0800 | [diff] [blame] | 167 | #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) |
Gong Qianyu | e0579a5 | 2016-01-25 15:16:05 +0800 | [diff] [blame] | 168 | #define CONFIG_SF_DEFAULT_BUS 1 |
| 169 | #define CONFIG_SF_DEFAULT_CS 0 |
| 170 | #endif |
Gong Qianyu | 166ef1e | 2016-01-25 15:16:06 +0800 | [diff] [blame] | 171 | #endif |
Gong Qianyu | e0579a5 | 2016-01-25 15:16:05 +0800 | [diff] [blame] | 172 | |
Aneesh Bansal | ef6c55a | 2016-01-22 16:37:22 +0530 | [diff] [blame] | 173 | #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ |
| 174 | |
Shaohui Xie | e829734 | 2015-10-26 19:47:54 +0800 | [diff] [blame] | 175 | /* FMan ucode */ |
| 176 | #define CONFIG_SYS_DPAA_FMAN |
| 177 | #ifdef CONFIG_SYS_DPAA_FMAN |
| 178 | #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 |
| 179 | |
Qianyu Gong | fd1b147 | 2016-04-01 17:52:52 +0800 | [diff] [blame] | 180 | #ifdef CONFIG_NAND_BOOT |
| 181 | /* Store Fman ucode at offeset 0x160000(11 blocks). */ |
| 182 | #define CONFIG_SYS_QE_FMAN_FW_IN_NAND |
| 183 | #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) |
Qianyu Gong | 2a55583 | 2016-04-01 17:52:53 +0800 | [diff] [blame] | 184 | #elif defined(CONFIG_SD_BOOT) |
| 185 | /* |
| 186 | * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is |
| 187 | * about 1MB (2040 blocks), Env is stored after the image, and the env size is |
| 188 | * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 2080(0x820). |
| 189 | */ |
| 190 | #define CONFIG_SYS_QE_FMAN_FW_IN_MMC |
| 191 | #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) |
| 192 | #elif defined(CONFIG_QSPI_BOOT) |
Gong Qianyu | 166ef1e | 2016-01-25 15:16:06 +0800 | [diff] [blame] | 193 | #define CONFIG_SYS_QE_FW_IN_SPIFLASH |
| 194 | #define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000 |
| 195 | #define CONFIG_ENV_SPI_BUS 0 |
| 196 | #define CONFIG_ENV_SPI_CS 0 |
| 197 | #define CONFIG_ENV_SPI_MAX_HZ 1000000 |
| 198 | #define CONFIG_ENV_SPI_MODE 0x03 |
| 199 | #else |
Shaohui Xie | e829734 | 2015-10-26 19:47:54 +0800 | [diff] [blame] | 200 | #define CONFIG_SYS_QE_FMAN_FW_IN_NOR |
| 201 | /* FMan fireware Pre-load address */ |
| 202 | #define CONFIG_SYS_FMAN_FW_ADDR 0x60300000 |
Gong Qianyu | 166ef1e | 2016-01-25 15:16:06 +0800 | [diff] [blame] | 203 | #endif |
Shaohui Xie | e829734 | 2015-10-26 19:47:54 +0800 | [diff] [blame] | 204 | #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 |
| 205 | #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) |
| 206 | #endif |
| 207 | |
Mingkai Hu | f3a8e2b | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 208 | /* Miscellaneous configurable options */ |
| 209 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) |
| 210 | #define CONFIG_ARCH_EARLY_INIT_R |
| 211 | #define CONFIG_BOARD_LATE_INIT |
| 212 | |
| 213 | #define CONFIG_HWCONFIG |
| 214 | #define HWCONFIG_BUFFER_SIZE 128 |
| 215 | |
Wenbin Song | dbe18f1 | 2016-07-21 18:55:16 +0800 | [diff] [blame] | 216 | #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) |
| 217 | #define MTDPARTS_DEFAULT "mtdparts=spi0.0:1m(uboot)," \ |
| 218 | "5m(kernel),1m(dtb),9m(file_system)" |
| 219 | #else |
| 220 | #define MTDPARTS_DEFAULT "mtdparts=60000000.nor:1m(nor_bank0_rcw)," \ |
| 221 | "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \ |
| 222 | "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \ |
| 223 | "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \ |
| 224 | "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \ |
| 225 | "40m(nor_bank4_fit);7e800000.flash:" \ |
| 226 | "1m(nand_uboot),1m(nand_uboot_env)," \ |
| 227 | "20m(nand_fit);spi0.0:1m(uboot)," \ |
| 228 | "5m(kernel),1m(dtb),9m(file_system)" |
| 229 | #endif |
| 230 | |
Mingkai Hu | f3a8e2b | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 231 | /* Initial environment variables */ |
| 232 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 233 | "hwconfig=fsl_ddr:bank_intlv=auto\0" \ |
| 234 | "loadaddr=0x80100000\0" \ |
Mingkai Hu | f3a8e2b | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 235 | "fdt_high=0xffffffffffffffff\0" \ |
| 236 | "initrd_high=0xffffffffffffffff\0" \ |
Qianyu Gong | ad6767b | 2016-03-15 16:35:57 +0800 | [diff] [blame] | 237 | "kernel_start=0x61100000\0" \ |
| 238 | "kernel_load=0xa0000000\0" \ |
| 239 | "kernel_size=0x2800000\0" \ |
Wenbin Song | dbe18f1 | 2016-07-21 18:55:16 +0800 | [diff] [blame] | 240 | "console=ttyS0,115200\0" \ |
| 241 | "mtdparts=" MTDPARTS_DEFAULT "\0" |
Mingkai Hu | f3a8e2b | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 242 | |
| 243 | #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ |
Wenbin Song | dbe18f1 | 2016-07-21 18:55:16 +0800 | [diff] [blame] | 244 | "earlycon=uart8250,mmio,0x21c0500 " \ |
| 245 | MTDPARTS_DEFAULT |
| 246 | |
Qianyu Gong | 1297cdb | 2016-04-25 16:53:53 +0800 | [diff] [blame] | 247 | #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) |
| 248 | #define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \ |
| 249 | "e0000 f00000 && bootm $kernel_load" |
| 250 | #else |
Mingkai Hu | f3a8e2b | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 251 | #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ |
| 252 | "$kernel_size && bootm $kernel_load" |
Qianyu Gong | 1297cdb | 2016-04-25 16:53:53 +0800 | [diff] [blame] | 253 | #endif |
Mingkai Hu | f3a8e2b | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 254 | |
| 255 | /* Monitor Command Prompt */ |
| 256 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ |
Mingkai Hu | f3a8e2b | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 257 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
| 258 | sizeof(CONFIG_SYS_PROMPT) + 16) |
Mingkai Hu | f3a8e2b | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 259 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ |
| 260 | #define CONFIG_SYS_LONGHELP |
| 261 | #define CONFIG_CMDLINE_EDITING 1 |
| 262 | #define CONFIG_AUTO_COMPLETE |
| 263 | #define CONFIG_SYS_MAXARGS 64 /* max command args */ |
| 264 | |
| 265 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
| 266 | |
Aneesh Bansal | ef6c55a | 2016-01-22 16:37:22 +0530 | [diff] [blame] | 267 | /* Hash command with SHA acceleration supported in hardware */ |
| 268 | #ifdef CONFIG_FSL_CAAM |
| 269 | #define CONFIG_CMD_HASH |
| 270 | #define CONFIG_SHA_HW_ACCEL |
| 271 | #endif |
| 272 | |
Mingkai Hu | f3a8e2b | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 273 | #endif /* __LS1043A_COMMON_H */ |