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Chunhe Lan57072332013-06-14 16:21:48 +08001/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * Authors: Roy Zang <tie-fei.zang@freescale.com>
5 * Chunhe Lan <Chunhe.Lan@freescale.com>
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Chunhe Lan57072332013-06-14 16:21:48 +08008 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13#ifndef CONFIG_SYS_TEXT_BASE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053014#define CONFIG_SYS_TEXT_BASE 0xeff40000
Chunhe Lan57072332013-06-14 16:21:48 +080015#endif
16
17#ifndef CONFIG_SYS_MONITOR_BASE
18#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
19#endif
20
21#ifndef CONFIG_RESET_VECTOR_ADDRESS
22#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
23#endif
24
25/* High Level Configuration Options */
26#define CONFIG_BOOKE /* BOOKE */
27#define CONFIG_E500 /* BOOKE e500 family */
Chunhe Lan57072332013-06-14 16:21:48 +080028#define CONFIG_MP /* support multiple processors */
29
30#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
Chunhe Lan57072332013-06-14 16:21:48 +080031#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Robert P. J. Dayb38eaec2016-05-03 19:52:49 -040032#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
33#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
34#define CONFIG_PCIE3 /* PCIE controller 3 (slot 3) */
Chunhe Lan57072332013-06-14 16:21:48 +080035#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
36#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
37#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
38#define CONFIG_FSL_LAW /* Use common FSL init code */
39
40#ifndef __ASSEMBLY__
41extern unsigned long get_clock_freq(void);
42#endif
43
44#define CONFIG_SYS_CLK_FREQ 66666666
45#define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ
46
47/*
48 * These can be toggled for performance analysis, otherwise use default.
49 */
50#define CONFIG_L2_CACHE /* toggle L2 cache */
51#define CONFIG_BTB /* toggle branch predition */
52#define CONFIG_HWCONFIG
53
54#define CONFIG_ENABLE_36BIT_PHYS
55
56#define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
57#define CONFIG_SYS_MEMTEST_END 0x02000000
58
59#define CONFIG_PANIC_HANG /* do not reset board on panic */
60
61/* Implement conversion of addresses in the LBC */
62#define CONFIG_SYS_LBC_LBCR 0x00000000
63#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
64
65/* DDR Setup */
66#define CONFIG_VERY_BIG_RAM
67#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
68#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
69
70#define CONFIG_DIMM_SLOTS_PER_CTLR 1
71#define CONFIG_CHIP_SELECTS_PER_CTRL 1
72
73#define CONFIG_DDR_SPD
York Sun5614e712013-09-30 09:22:09 -070074#define CONFIG_SYS_FSL_DDR3
Chunhe Lan57072332013-06-14 16:21:48 +080075#define CONFIG_FSL_DDR_INTERACTIVE
76#define CONFIG_SYS_SDRAM_SIZE 512u /* DDR is 512M */
77#define CONFIG_SYS_SPD_BUS_NUM 0
78#define SPD_EEPROM_ADDRESS 0x50
79#define CONFIG_SYS_DDR_RAW_TIMING
80
81/*
82 * Memory map
83 *
84 * 0x0000_0000 0x1fff_ffff DDR 512M cacheable
85 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
86 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
87 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
88 * 0xff00_0000 0xff3f_ffff DPAA_QBMAN 4M cacheable
89 * 0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable
90 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable TLB0
91 *
92 * Localbus non-cacheable
93 *
94 * 0xec00_0000 0xefff_ffff NOR flash 64M non-cacheable
95 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
96 */
97
98/*
99 * Local Bus Definitions
100 */
101#define CONFIG_SYS_FLASH_BASE 0xec000000 /* start of FLASH 64M */
102#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
103
104#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
105 | BR_PS_16 | BR_V)
106#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
107
108#define CONFIG_FLASH_CFI_DRIVER
109#define CONFIG_SYS_FLASH_CFI
110#define CONFIG_SYS_FLASH_EMPTY_INFO
111#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
112#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
113#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
114#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
115
116#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f function */
117#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
118
119#define CONFIG_SYS_INIT_RAM_LOCK
120#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
121#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* Size of used area in RAM */
122#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
123 GENERATED_GBL_DATA_SIZE)
124#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
125
Prabhakar Kushwaha9307cba2014-03-31 15:31:48 +0530126#define CONFIG_SYS_MONITOR_LEN (768 * 1024) /* Reserve 512 kB for Mon */
Chunhe Lan57072332013-06-14 16:21:48 +0800127#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
128
129#define CONFIG_SYS_NAND_BASE 0xffa00000
130#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
131
132#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
133#define CONFIG_SYS_MAX_NAND_DEVICE 1
Chunhe Lan57072332013-06-14 16:21:48 +0800134#define CONFIG_CMD_NAND
135#define CONFIG_NAND_FSL_ELBC
136#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
137
138/* NAND flash config */
139#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
140 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
141 | BR_PS_8 /* Port Size = 8bit */ \
142 | BR_MS_FCM /* MSEL = FCM */ \
143 | BR_V) /* valid */
144#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \
145 | OR_FCM_PGS \
146 | OR_FCM_CSCT \
147 | OR_FCM_CST \
148 | OR_FCM_CHT \
149 | OR_FCM_SCY_1 \
150 | OR_FCM_TRLX \
151 | OR_FCM_EHTR)
152
153#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
154#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
155#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
156#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
157
158/* Serial Port */
159#define CONFIG_CONS_INDEX 1
160#undef CONFIG_SERIAL_SOFTWARE_FIFO
Chunhe Lan57072332013-06-14 16:21:48 +0800161#define CONFIG_SYS_NS16550_SERIAL
162#define CONFIG_SYS_NS16550_REG_SIZE 1
163#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
164
165#define CONFIG_SYS_BAUDRATE_TABLE \
166 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
167
168#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
169#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
170
Chunhe Lan57072332013-06-14 16:21:48 +0800171/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200172#define CONFIG_SYS_I2C
173#define CONFIG_SYS_I2C_FSL
174#define CONFIG_SYS_FSL_I2C_SPEED 400000
175#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
176#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
177#define CONFIG_SYS_FSL_I2C2_SPEED 400000
178#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
179#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
Chunhe Lan57072332013-06-14 16:21:48 +0800180
181/*
182 * I2C2 EEPROM
183 */
184#define CONFIG_ID_EEPROM
185#ifdef CONFIG_ID_EEPROM
186#define CONFIG_SYS_I2C_EEPROM_NXID
187#endif
188#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
189#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
190#define CONFIG_SYS_EEPROM_BUS_NUM 0
191
Chunhe Lan57072332013-06-14 16:21:48 +0800192/*
193 * General PCI
194 * Memory space is mapped 1-1, but I/O space must start from 0.
195 */
196
197/* controller 3, Slot 1, tgtid 3, Base address b000 */
198#define CONFIG_SYS_PCIE3_NAME "Slot 3"
199#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
200#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
201#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
202#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
203#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
204#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
205#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
206#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
207
208/* controller 2, direct to uli, tgtid 2, Base address 9000 */
209#define CONFIG_SYS_PCIE2_NAME "Slot 2"
210#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
211#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
212#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
213#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
214#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
215#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
216#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
217#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
218
219/* controller 1, Slot 2, tgtid 1, Base address a000 */
220#define CONFIG_SYS_PCIE1_NAME "Slot 1"
221#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
222#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
223#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
224#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
225#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
226#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
227#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
228#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
229
230#if defined(CONFIG_PCI)
Chunhe Lan57072332013-06-14 16:21:48 +0800231#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
232#endif /* CONFIG_PCI */
233
234/*
235 * Environment
236 */
237#define CONFIG_ENV_OVERWRITE
238
239#define CONFIG_ENV_IS_IN_FLASH
Chunhe Lan57072332013-06-14 16:21:48 +0800240#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Chunhe Lan57072332013-06-14 16:21:48 +0800241#define CONFIG_ENV_SIZE 0x2000
242#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
243
244#define CONFIG_LOADS_ECHO /* echo on for serial download */
245#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
246
247/*
248 * Command line configuration.
249 */
Chunhe Lan57072332013-06-14 16:21:48 +0800250#define CONFIG_CMD_IRQ
Chunhe Lan57072332013-06-14 16:21:48 +0800251#define CONFIG_CMD_REGINFO
252
253#if defined(CONFIG_PCI)
254#define CONFIG_CMD_PCI
Chunhe Lan57072332013-06-14 16:21:48 +0800255#endif
256
257/*
258 * USB
259 */
260#define CONFIG_HAS_FSL_DR_USB
261#ifdef CONFIG_HAS_FSL_DR_USB
262#define CONFIG_USB_EHCI
263
264#ifdef CONFIG_USB_EHCI
Chunhe Lan57072332013-06-14 16:21:48 +0800265#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
266#define CONFIG_USB_EHCI_FSL
Chunhe Lan57072332013-06-14 16:21:48 +0800267#define CONFIG_DOS_PARTITION
268#endif
269#endif
270
271/*
272 * Miscellaneous configurable options
273 */
274#define CONFIG_SYS_LONGHELP /* undef to save memory */
275#define CONFIG_CMDLINE_EDITING /* Command-line editing */
276#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Chunhe Lan57072332013-06-14 16:21:48 +0800277#if defined(CONFIG_CMD_KGDB)
278#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
279#else
280#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
281#endif
282/* Print Buffer Size */
283#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
284#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
285/* Boot Argument Buffer Size */
286#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Chunhe Lan57072332013-06-14 16:21:48 +0800287
288/*
289 * For booting Linux, the board info and command line data
290 * have to be in the first 64 MB of memory, since this is
291 * the maximum mapped by the Linux kernel during initialization.
292 */
293#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
294#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
295
296/*
297 * Environment Configuration
298 */
299#define CONFIG_BOOTFILE "uImage"
300#define CONFIG_UBOOTPATH (u-boot.bin) /* U-Boot image on TFTP server */
301
302/* default location for tftp and bootm */
303#define CONFIG_LOADADDR 1000000
304
Chunhe Lan57072332013-06-14 16:21:48 +0800305
306#define CONFIG_BAUDRATE 115200
307
308/* Qman/Bman */
309#define CONFIG_SYS_DPAA_QBMAN /* support Q/Bman */
310#define CONFIG_SYS_QMAN_MEM_BASE 0xff000000
311#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
312#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500313#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
314#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
315#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
316#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
317#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
318 CONFIG_SYS_QMAN_CENA_SIZE)
319#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
320#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
Chunhe Lan57072332013-06-14 16:21:48 +0800321#define CONFIG_SYS_BMAN_MEM_BASE 0xff200000
322#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
323#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500324#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
325#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
326#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
327#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
328#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
329 CONFIG_SYS_BMAN_CENA_SIZE)
330#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
331#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
Chunhe Lan57072332013-06-14 16:21:48 +0800332
333/* For FM */
334#define CONFIG_SYS_DPAA_FMAN
335#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
336
337#ifdef CONFIG_SYS_DPAA_FMAN
338#define CONFIG_FMAN_ENET
339#define CONFIG_PHY_ATHEROS
340#endif
341
342/* Default address of microcode for the Linux Fman driver */
343/* QE microcode/firmware address */
344#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800345#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
Chunhe Lan57072332013-06-14 16:21:48 +0800346#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
347#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
348
349#ifdef CONFIG_FMAN_ENET
350#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1
351#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x2
352
353#define CONFIG_SYS_TBIPA_VALUE 8
354#define CONFIG_MII /* MII PHY management */
355#define CONFIG_ETHPRIME "FM1@DTSEC1"
356#endif
357
358#define CONFIG_EXTRA_ENV_SETTINGS \
Chunhe Lan5eabbae2014-10-17 16:24:06 +0800359 "netdev=eth0\0" \
360 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
361 "loadaddr=1000000\0" \
362 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
363 "tftpflash=tftpboot $loadaddr $uboot; " \
364 "protect off $ubootaddr +$filesize; " \
365 "erase $ubootaddr +$filesize; " \
366 "cp.b $loadaddr $ubootaddr $filesize; " \
367 "protect on $ubootaddr +$filesize; " \
368 "cmp.b $loadaddr $ubootaddr $filesize\0" \
369 "consoledev=ttyS0\0" \
370 "ramdiskaddr=2000000\0" \
371 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
Scott Woodb24a4f62016-07-19 17:52:06 -0500372 "fdtaddr=1e00000\0" \
Chunhe Lan5eabbae2014-10-17 16:24:06 +0800373 "fdtfile=p1023rdb.dtb\0" \
374 "othbootargs=ramdisk_size=600000\0" \
375 "bdev=sda1\0" \
Chunhe Lan57072332013-06-14 16:21:48 +0800376 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
377
Chunhe Lan5eabbae2014-10-17 16:24:06 +0800378#define CONFIG_HDBOOT \
379 "setenv bootargs root=/dev/$bdev rw " \
380 "console=$consoledev,$baudrate $othbootargs;" \
381 "tftp $loadaddr $bootfile;" \
382 "tftp $fdtaddr $fdtfile;" \
383 "bootm $loadaddr - $fdtaddr"
384
385#define CONFIG_NFSBOOTCOMMAND \
386 "setenv bootargs root=/dev/nfs rw " \
387 "nfsroot=$serverip:$rootpath " \
388 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
389 "console=$consoledev,$baudrate $othbootargs;" \
390 "tftp $loadaddr $bootfile;" \
391 "tftp $fdtaddr $fdtfile;" \
392 "bootm $loadaddr - $fdtaddr"
393
394#define CONFIG_RAMBOOTCOMMAND \
395 "setenv bootargs root=/dev/ram rw " \
396 "console=$consoledev,$baudrate $othbootargs;" \
397 "tftp $ramdiskaddr $ramdiskfile;" \
398 "tftp $loadaddr $bootfile;" \
399 "tftp $fdtaddr $fdtfile;" \
400 "bootm $loadaddr $ramdiskaddr $fdtaddr"
401
402#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
403
Chunhe Lan57072332013-06-14 16:21:48 +0800404#endif /* __CONFIG_H */