Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 1 | /* |
Kumar Gala | 7c57f3e | 2011-01-11 00:52:35 -0600 | [diff] [blame] | 2 | * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc. |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 3 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 4 | * SPDX-License-Identifier: GPL-2.0+ |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | /* |
| 8 | * mpc8544ds board configuration file |
| 9 | * |
| 10 | */ |
| 11 | #ifndef __CONFIG_H |
| 12 | #define __CONFIG_H |
| 13 | |
| 14 | /* High Level Configuration Options */ |
| 15 | #define CONFIG_BOOKE 1 /* BOOKE */ |
| 16 | #define CONFIG_E500 1 /* BOOKE e500 family */ |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 17 | |
Wolfgang Denk | 2ae1824 | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 18 | #ifndef CONFIG_SYS_TEXT_BASE |
| 19 | #define CONFIG_SYS_TEXT_BASE 0xfff80000 |
| 20 | #endif |
| 21 | |
Ed Swarthout | 837f1ba | 2007-07-27 01:50:51 -0500 | [diff] [blame] | 22 | #define CONFIG_PCI1 1 /* PCI controller 1 */ |
Robert P. J. Day | b38eaec | 2016-05-03 19:52:49 -0400 | [diff] [blame] | 23 | #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ |
| 24 | #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ |
| 25 | #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ |
Ed Swarthout | 837f1ba | 2007-07-27 01:50:51 -0500 | [diff] [blame] | 26 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ |
Gabor Juhos | 842033e | 2013-05-30 07:06:12 +0000 | [diff] [blame] | 27 | #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ |
Kumar Gala | 8ff3de6 | 2007-12-07 12:17:34 -0600 | [diff] [blame] | 28 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ |
Kumar Gala | 0151cba | 2008-10-21 11:33:58 -0500 | [diff] [blame] | 29 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 30 | |
Kumar Gala | 4bcae9c | 2008-01-16 01:16:16 -0600 | [diff] [blame] | 31 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
| 32 | |
Ed Swarthout | 837f1ba | 2007-07-27 01:50:51 -0500 | [diff] [blame] | 33 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 34 | #define CONFIG_ENV_OVERWRITE |
Ed Swarthout | 837f1ba | 2007-07-27 01:50:51 -0500 | [diff] [blame] | 35 | #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 36 | |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 37 | #ifndef __ASSEMBLY__ |
| 38 | extern unsigned long get_board_sys_clk(unsigned long dummy); |
| 39 | #endif |
| 40 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ |
| 41 | |
| 42 | /* |
| 43 | * These can be toggled for performance analysis, otherwise use default. |
| 44 | */ |
Ed Swarthout | 837f1ba | 2007-07-27 01:50:51 -0500 | [diff] [blame] | 45 | #define CONFIG_L2_CACHE /* toggle L2 cache */ |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 46 | #define CONFIG_BTB /* toggle branch predition */ |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 47 | |
| 48 | /* |
| 49 | * Only possible on E500 Version 2 or newer cores. |
| 50 | */ |
| 51 | #define CONFIG_ENABLE_36BIT_PHYS 1 |
| 52 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 53 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ |
| 54 | #define CONFIG_SYS_MEMTEST_END 0x00400000 |
Ed Swarthout | 837f1ba | 2007-07-27 01:50:51 -0500 | [diff] [blame] | 55 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 56 | |
Timur Tabi | e46fedf | 2011-08-04 18:03:41 -0500 | [diff] [blame] | 57 | #define CONFIG_SYS_CCSRBAR 0xe0000000 |
| 58 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 59 | |
Kumar Gala | 1167a2f | 2008-08-26 08:02:30 -0500 | [diff] [blame] | 60 | /* DDR Setup */ |
York Sun | 5614e71 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 61 | #define CONFIG_SYS_FSL_DDR2 |
Kumar Gala | 1167a2f | 2008-08-26 08:02:30 -0500 | [diff] [blame] | 62 | #undef CONFIG_FSL_DDR_INTERACTIVE |
| 63 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ |
| 64 | #define CONFIG_DDR_SPD |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 65 | |
Dave Liu | 9b0ad1b | 2008-10-28 17:53:38 +0800 | [diff] [blame] | 66 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ |
Kumar Gala | 1167a2f | 2008-08-26 08:02:30 -0500 | [diff] [blame] | 67 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
| 68 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 69 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
| 70 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
Kumar Gala | 1167a2f | 2008-08-26 08:02:30 -0500 | [diff] [blame] | 71 | #define CONFIG_VERY_BIG_RAM |
| 72 | |
| 73 | #define CONFIG_NUM_DDR_CONTROLLERS 1 |
| 74 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| 75 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 |
| 76 | |
| 77 | /* I2C addresses of SPD EEPROMs */ |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 78 | #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ |
| 79 | |
Kumar Gala | 1167a2f | 2008-08-26 08:02:30 -0500 | [diff] [blame] | 80 | /* Make sure required options are set */ |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 81 | #ifndef CONFIG_SPD_EEPROM |
| 82 | #error ("CONFIG_SPD_EEPROM is required") |
| 83 | #endif |
| 84 | |
| 85 | #undef CONFIG_CLOCKS_IN_MHZ |
| 86 | |
| 87 | /* |
| 88 | * Memory map |
| 89 | * |
| 90 | * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable |
| 91 | * |
| 92 | * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable |
| 93 | * |
| 94 | * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable |
| 95 | * |
| 96 | * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable |
| 97 | * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable |
| 98 | * |
| 99 | * Localbus cacheable |
| 100 | * |
| 101 | * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable |
| 102 | * 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0 |
| 103 | * |
| 104 | * Localbus non-cacheable |
| 105 | * |
| 106 | * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable |
| 107 | * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable |
| 108 | * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable |
| 109 | * |
| 110 | */ |
| 111 | |
| 112 | /* |
| 113 | * Local Bus Definitions |
| 114 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 115 | #define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* boot TLB */ |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 116 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 117 | #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */ |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 118 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 119 | #define CONFIG_SYS_BR0_PRELIM 0xff801001 |
| 120 | #define CONFIG_SYS_BR1_PRELIM 0xfe801001 |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 121 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 122 | #define CONFIG_SYS_OR0_PRELIM 0xff806e65 |
| 123 | #define CONFIG_SYS_OR1_PRELIM 0xff806e65 |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 124 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 125 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 126 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 127 | #define CONFIG_SYS_FLASH_QUIET_TEST |
| 128 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
| 129 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ |
| 130 | #undef CONFIG_SYS_FLASH_CHECKSUM |
| 131 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
| 132 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
Kumar Gala | 81e56e9 | 2008-06-09 18:55:38 -0500 | [diff] [blame] | 133 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 134 | |
Wolfgang Denk | 14d0a02 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 135 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 136 | |
Jean-Christophe PLAGNIOL-VILLARD | 00b1883 | 2008-08-13 01:40:42 +0200 | [diff] [blame] | 137 | #define CONFIG_FLASH_CFI_DRIVER |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 138 | #define CONFIG_SYS_FLASH_CFI |
| 139 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 140 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 141 | #define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000 |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 142 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 143 | #define CONFIG_SYS_BR2_PRELIM 0xf8201001 /* port size 16bit */ |
| 144 | #define CONFIG_SYS_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/ |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 145 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 146 | #define CONFIG_SYS_BR3_PRELIM 0xf8100801 /* port size 8bit */ |
| 147 | #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 148 | |
Kim Phillips | 7608d75 | 2007-08-21 17:00:17 -0500 | [diff] [blame] | 149 | #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 150 | #define PIXIS_BASE 0xf8100000 /* PIXIS registers */ |
| 151 | #define PIXIS_ID 0x0 /* Board ID at offset 0 */ |
| 152 | #define PIXIS_VER 0x1 /* Board version at offset 1 */ |
| 153 | #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ |
| 154 | #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ |
| 155 | #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch |
| 156 | * register */ |
| 157 | #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ |
| 158 | #define PIXIS_VCTL 0x10 /* VELA Control Register */ |
| 159 | #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ |
| 160 | #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ |
| 161 | #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ |
Kumar Gala | 6bb5b41 | 2009-07-14 22:42:01 -0500 | [diff] [blame] | 162 | #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */ |
| 163 | #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */ |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 164 | #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ |
| 165 | #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ |
| 166 | #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ |
| 167 | #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ |
Andy Fleming | 5a8a163 | 2008-08-31 16:33:30 -0500 | [diff] [blame] | 168 | #define PIXIS_VSPEED2 0x1d /* VELA VSpeed 2 */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 169 | #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ |
Andy Fleming | 5a8a163 | 2008-08-31 16:33:30 -0500 | [diff] [blame] | 170 | #define PIXIS_VSPEED2_TSEC1SER 0x2 |
| 171 | #define PIXIS_VSPEED2_TSEC3SER 0x1 |
| 172 | #define PIXIS_VCFGEN1_TSEC1SER 0x20 |
| 173 | #define PIXIS_VCFGEN1_TSEC3SER 0x40 |
Liu Yu | bff188b | 2008-10-10 11:40:58 +0800 | [diff] [blame] | 174 | #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER) |
| 175 | #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER) |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 176 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 177 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
| 178 | #define CONFIG_SYS_INIT_RAM_ADDR 0xf4010000 /* Initial L1 address */ |
Wolfgang Denk | 553f098 | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 179 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 180 | |
Wolfgang Denk | 25ddd1f | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 181 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 182 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 183 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 184 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
| 185 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 186 | |
| 187 | /* Serial Port - controlled on board with jumper J8 |
| 188 | * open - index 2 |
| 189 | * shorted - index 1 |
| 190 | */ |
| 191 | #define CONFIG_CONS_INDEX 1 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 192 | #define CONFIG_SYS_NS16550_SERIAL |
| 193 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| 194 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 195 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 196 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 197 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
| 198 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 199 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
| 200 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 201 | |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 202 | /* I2C */ |
Heiko Schocher | 00f792e | 2012-10-24 13:48:22 +0200 | [diff] [blame] | 203 | #define CONFIG_SYS_I2C |
| 204 | #define CONFIG_SYS_I2C_FSL |
| 205 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 |
| 206 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
Benjamin Kamath | 7f25fdc | 2016-06-29 16:44:38 -0700 | [diff] [blame] | 207 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 |
Heiko Schocher | 00f792e | 2012-10-24 13:48:22 +0200 | [diff] [blame] | 208 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 209 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 210 | |
| 211 | /* |
| 212 | * General PCI |
| 213 | * Memory space is mapped 1-1, but I/O space must start from 0. |
| 214 | */ |
Kumar Gala | 5af0fdd | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 215 | #define CONFIG_SYS_PCIE_VIRT 0x80000000 /* 1G PCIE TLB */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 216 | #define CONFIG_SYS_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */ |
Kumar Gala | 5af0fdd | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 217 | #define CONFIG_SYS_PCI_VIRT 0xc0000000 /* 512M PCI TLB */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 218 | #define CONFIG_SYS_PCI_PHYS 0xc0000000 /* 512M PCI TLB */ |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 219 | |
Kumar Gala | 5af0fdd | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 220 | #define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000 |
Kumar Gala | 10795f4 | 2008-12-02 16:08:36 -0600 | [diff] [blame] | 221 | #define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000 |
Kumar Gala | 5af0fdd | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 222 | #define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 223 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
Kumar Gala | aca5f01 | 2008-12-02 16:08:40 -0600 | [diff] [blame] | 224 | #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000 |
Kumar Gala | 5f91ef6 | 2008-12-02 16:08:37 -0600 | [diff] [blame] | 225 | #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 226 | #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 |
| 227 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 228 | |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 229 | /* controller 2, Slot 1, tgtid 1, Base address 9000 */ |
Kumar Gala | 64a1686 | 2010-12-17 06:01:24 -0600 | [diff] [blame] | 230 | #define CONFIG_SYS_PCIE2_NAME "Slot 1" |
Kumar Gala | 5af0fdd | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 231 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000 |
Kumar Gala | 10795f4 | 2008-12-02 16:08:36 -0600 | [diff] [blame] | 232 | #define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000 |
Kumar Gala | 5af0fdd | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 233 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 234 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ |
Kumar Gala | aca5f01 | 2008-12-02 16:08:40 -0600 | [diff] [blame] | 235 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000 |
Kumar Gala | 5f91ef6 | 2008-12-02 16:08:37 -0600 | [diff] [blame] | 236 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 237 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000 |
| 238 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 239 | |
| 240 | /* controller 1, Slot 2,tgtid 2, Base address a000 */ |
Kumar Gala | 64a1686 | 2010-12-17 06:01:24 -0600 | [diff] [blame] | 241 | #define CONFIG_SYS_PCIE1_NAME "Slot 2" |
Kumar Gala | 5af0fdd | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 242 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 |
Kumar Gala | 10795f4 | 2008-12-02 16:08:36 -0600 | [diff] [blame] | 243 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 |
Kumar Gala | 5af0fdd | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 244 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 245 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ |
Kumar Gala | aca5f01 | 2008-12-02 16:08:40 -0600 | [diff] [blame] | 246 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000 |
Kumar Gala | 5f91ef6 | 2008-12-02 16:08:37 -0600 | [diff] [blame] | 247 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 248 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000 |
| 249 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 250 | |
| 251 | /* controller 3, direct to uli, tgtid 3, Base address b000 */ |
Kumar Gala | 64a1686 | 2010-12-17 06:01:24 -0600 | [diff] [blame] | 252 | #define CONFIG_SYS_PCIE3_NAME "ULI" |
Kumar Gala | 5af0fdd | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 253 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 |
Kumar Gala | 10795f4 | 2008-12-02 16:08:36 -0600 | [diff] [blame] | 254 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000 |
Kumar Gala | 5af0fdd | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 255 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 256 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */ |
Kumar Gala | aca5f01 | 2008-12-02 16:08:40 -0600 | [diff] [blame] | 257 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000 /* reuse mem LAW */ |
Kumar Gala | 5f91ef6 | 2008-12-02 16:08:37 -0600 | [diff] [blame] | 258 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 259 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */ |
| 260 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */ |
Kumar Gala | 5af0fdd | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 261 | #define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000 |
Kumar Gala | 10795f4 | 2008-12-02 16:08:36 -0600 | [diff] [blame] | 262 | #define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000 |
Kumar Gala | 5af0fdd | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 263 | #define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 264 | #define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000 /* 1M */ |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 265 | |
| 266 | #if defined(CONFIG_PCI) |
| 267 | |
Kumar Gala | 630d9bf | 2008-07-14 14:07:03 -0500 | [diff] [blame] | 268 | /*PCIE video card used*/ |
Kumar Gala | aca5f01 | 2008-12-02 16:08:40 -0600 | [diff] [blame] | 269 | #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT |
Kumar Gala | 630d9bf | 2008-07-14 14:07:03 -0500 | [diff] [blame] | 270 | |
| 271 | /*PCI video card used*/ |
Kumar Gala | aca5f01 | 2008-12-02 16:08:40 -0600 | [diff] [blame] | 272 | /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ |
Kumar Gala | 630d9bf | 2008-07-14 14:07:03 -0500 | [diff] [blame] | 273 | |
| 274 | /* video */ |
Kumar Gala | 630d9bf | 2008-07-14 14:07:03 -0500 | [diff] [blame] | 275 | |
| 276 | #if defined(CONFIG_VIDEO) |
| 277 | #define CONFIG_BIOSEMU |
Kumar Gala | 630d9bf | 2008-07-14 14:07:03 -0500 | [diff] [blame] | 278 | #define CONFIG_ATI_RADEON_FB |
| 279 | #define CONFIG_VIDEO_LOGO |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 280 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET |
Kumar Gala | 630d9bf | 2008-07-14 14:07:03 -0500 | [diff] [blame] | 281 | #endif |
| 282 | |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 283 | #undef CONFIG_EEPRO100 |
| 284 | #undef CONFIG_TULIP |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 285 | |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 286 | #ifndef CONFIG_PCI_PNP |
Kumar Gala | 5f91ef6 | 2008-12-02 16:08:37 -0600 | [diff] [blame] | 287 | #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS |
| 288 | #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 289 | #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ |
| 290 | #endif |
| 291 | |
| 292 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| 293 | #define CONFIG_DOS_PARTITION |
| 294 | #define CONFIG_SCSI_AHCI |
| 295 | |
| 296 | #ifdef CONFIG_SCSI_AHCI |
Rob Herring | 344ca0b | 2013-08-24 10:10:54 -0500 | [diff] [blame] | 297 | #define CONFIG_LIBATA |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 298 | #define CONFIG_SATA_ULI5288 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 299 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 |
| 300 | #define CONFIG_SYS_SCSI_MAX_LUN 1 |
| 301 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) |
| 302 | #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 303 | #endif /* SCSCI */ |
| 304 | |
| 305 | #endif /* CONFIG_PCI */ |
| 306 | |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 307 | #if defined(CONFIG_TSEC_ENET) |
| 308 | |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 309 | #define CONFIG_MII 1 /* MII PHY management */ |
| 310 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ |
Kim Phillips | 255a3577 | 2007-05-16 16:52:19 -0500 | [diff] [blame] | 311 | #define CONFIG_TSEC1 1 |
| 312 | #define CONFIG_TSEC1_NAME "eTSEC1" |
| 313 | #define CONFIG_TSEC3 1 |
| 314 | #define CONFIG_TSEC3_NAME "eTSEC3" |
Ed Swarthout | 837f1ba | 2007-07-27 01:50:51 -0500 | [diff] [blame] | 315 | |
Liu Yu | bff188b | 2008-10-10 11:40:58 +0800 | [diff] [blame] | 316 | #define CONFIG_PIXIS_SGMII_CMD |
Andy Fleming | 652f7c2 | 2008-08-31 16:33:28 -0500 | [diff] [blame] | 317 | #define CONFIG_FSL_SGMII_RISER 1 |
| 318 | #define SGMII_RISER_PHY_OFFSET 0x1c |
| 319 | |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 320 | #define TSEC1_PHY_ADDR 0 |
| 321 | #define TSEC3_PHY_ADDR 1 |
| 322 | |
Andy Fleming | 3a79013 | 2007-08-15 20:03:25 -0500 | [diff] [blame] | 323 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| 324 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| 325 | |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 326 | #define TSEC1_PHYIDX 0 |
| 327 | #define TSEC3_PHYIDX 0 |
| 328 | |
| 329 | #define CONFIG_ETHPRIME "eTSEC1" |
| 330 | |
| 331 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 332 | #endif /* CONFIG_TSEC_ENET */ |
| 333 | |
| 334 | /* |
| 335 | * Environment |
| 336 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 5a1aceb | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 337 | #define CONFIG_ENV_IS_IN_FLASH 1 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 338 | #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 |
Jean-Christophe PLAGNIOL-VILLARD | 0e8d158 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 339 | #define CONFIG_ENV_ADDR 0xfff80000 |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 340 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 341 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x70000) |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 342 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0e8d158 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 343 | #define CONFIG_ENV_SIZE 0x2000 |
| 344 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */ |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 345 | |
| 346 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 347 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 348 | |
Jon Loeliger | 2835e51 | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 349 | /* |
Jon Loeliger | 659e2f6 | 2007-07-10 09:10:49 -0500 | [diff] [blame] | 350 | * BOOTP options |
| 351 | */ |
| 352 | #define CONFIG_BOOTP_BOOTFILESIZE |
| 353 | #define CONFIG_BOOTP_BOOTPATH |
| 354 | #define CONFIG_BOOTP_GATEWAY |
| 355 | #define CONFIG_BOOTP_HOSTNAME |
| 356 | |
Jon Loeliger | 659e2f6 | 2007-07-10 09:10:49 -0500 | [diff] [blame] | 357 | /* |
Jon Loeliger | 2835e51 | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 358 | * Command line configuration. |
| 359 | */ |
Kumar Gala | 1c9aa76 | 2008-09-22 23:40:42 -0500 | [diff] [blame] | 360 | #define CONFIG_CMD_IRQ |
Becky Bruce | 199e262 | 2010-06-17 11:37:25 -0500 | [diff] [blame] | 361 | #define CONFIG_CMD_REGINFO |
Jon Loeliger | 2835e51 | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 362 | |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 363 | #if defined(CONFIG_PCI) |
Jon Loeliger | 2835e51 | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 364 | #define CONFIG_CMD_PCI |
Simon Glass | c649e3c | 2016-05-01 11:36:02 -0600 | [diff] [blame] | 365 | #define CONFIG_SCSI |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 366 | #endif |
Jon Loeliger | 2835e51 | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 367 | |
Hongtao Jia | 86a194b | 2012-12-20 19:39:53 +0000 | [diff] [blame] | 368 | /* |
| 369 | * USB |
| 370 | */ |
| 371 | #define CONFIG_USB_EHCI |
| 372 | |
| 373 | #ifdef CONFIG_USB_EHCI |
Hongtao Jia | 86a194b | 2012-12-20 19:39:53 +0000 | [diff] [blame] | 374 | #define CONFIG_USB_EHCI_PCI |
| 375 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
Hongtao Jia | 86a194b | 2012-12-20 19:39:53 +0000 | [diff] [blame] | 376 | #define CONFIG_PCI_EHCI_DEVICE 0 |
| 377 | #endif |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 378 | |
| 379 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 380 | |
| 381 | /* |
| 382 | * Miscellaneous configurable options |
| 383 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 384 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
Kim Phillips | 5be58f5 | 2010-07-14 19:47:18 -0500 | [diff] [blame] | 385 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
| 386 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 387 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
Jon Loeliger | 2835e51 | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 388 | #if defined(CONFIG_CMD_KGDB) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 389 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 390 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 391 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 392 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 393 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 394 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 395 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 396 | |
| 397 | /* |
| 398 | * For booting Linux, the board info and command line data |
Kumar Gala | a832ac4 | 2011-04-28 10:13:41 -0500 | [diff] [blame] | 399 | * have to be in the first 64 MB of memory, since this is |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 400 | * the maximum mapped by the Linux kernel during initialization. |
| 401 | */ |
Kumar Gala | a832ac4 | 2011-04-28 10:13:41 -0500 | [diff] [blame] | 402 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ |
| 403 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 404 | |
Jon Loeliger | 2835e51 | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 405 | #if defined(CONFIG_CMD_KGDB) |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 406 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 407 | #endif |
| 408 | |
| 409 | /* |
| 410 | * Environment Configuration |
| 411 | */ |
| 412 | |
| 413 | /* The mac addresses for all ethernet interface */ |
| 414 | #if defined(CONFIG_TSEC_ENET) |
Kumar Gala | ea5877e | 2007-08-16 11:01:21 -0500 | [diff] [blame] | 415 | #define CONFIG_HAS_ETH0 |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 416 | #define CONFIG_HAS_ETH1 |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 417 | #endif |
| 418 | |
| 419 | #define CONFIG_IPADDR 192.168.1.251 |
| 420 | |
| 421 | #define CONFIG_HOSTNAME 8544ds_unknown |
Joe Hershberger | 8b3637c | 2011-10-13 13:03:47 +0000 | [diff] [blame] | 422 | #define CONFIG_ROOTPATH "/nfs/mpc85xx" |
Joe Hershberger | b3f44c2 | 2011-10-13 13:03:48 +0000 | [diff] [blame] | 423 | #define CONFIG_BOOTFILE "8544ds/uImage.uboot" |
Ed Swarthout | 837f1ba | 2007-07-27 01:50:51 -0500 | [diff] [blame] | 424 | #define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */ |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 425 | |
Kumar Gala | 50c03c8 | 2007-11-27 22:42:34 -0600 | [diff] [blame] | 426 | #define CONFIG_SERVERIP 192.168.1.1 |
| 427 | #define CONFIG_GATEWAYIP 192.168.1.1 |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 428 | #define CONFIG_NETMASK 255.255.0.0 |
| 429 | |
| 430 | #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ |
| 431 | |
Ed Swarthout | 837f1ba | 2007-07-27 01:50:51 -0500 | [diff] [blame] | 432 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 433 | |
| 434 | #define CONFIG_BAUDRATE 115200 |
| 435 | |
Ed Swarthout | 837f1ba | 2007-07-27 01:50:51 -0500 | [diff] [blame] | 436 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
Marek Vasut | 5368c55 | 2012-09-23 17:41:24 +0200 | [diff] [blame] | 437 | "netdev=eth0\0" \ |
| 438 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
| 439 | "tftpflash=tftpboot $loadaddr $uboot; " \ |
| 440 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ |
| 441 | " +$filesize; " \ |
| 442 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ |
| 443 | " +$filesize; " \ |
| 444 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ |
| 445 | " $filesize; " \ |
| 446 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ |
| 447 | " +$filesize; " \ |
| 448 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ |
| 449 | " $filesize\0" \ |
| 450 | "consoledev=ttyS0\0" \ |
| 451 | "ramdiskaddr=2000000\0" \ |
| 452 | "ramdiskfile=8544ds/ramdisk.uboot\0" \ |
Scott Wood | b24a4f6 | 2016-07-19 17:52:06 -0500 | [diff] [blame] | 453 | "fdtaddr=1e00000\0" \ |
Marek Vasut | 5368c55 | 2012-09-23 17:41:24 +0200 | [diff] [blame] | 454 | "fdtfile=8544ds/mpc8544ds.dtb\0" \ |
| 455 | "bdev=sda3\0" |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 456 | |
| 457 | #define CONFIG_NFSBOOTCOMMAND \ |
| 458 | "setenv bootargs root=/dev/nfs rw " \ |
| 459 | "nfsroot=$serverip:$rootpath " \ |
| 460 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ |
| 461 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 462 | "tftp $loadaddr $bootfile;" \ |
Kumar Gala | 50c03c8 | 2007-11-27 22:42:34 -0600 | [diff] [blame] | 463 | "tftp $fdtaddr $fdtfile;" \ |
| 464 | "bootm $loadaddr - $fdtaddr" |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 465 | |
Ed Swarthout | 837f1ba | 2007-07-27 01:50:51 -0500 | [diff] [blame] | 466 | #define CONFIG_RAMBOOTCOMMAND \ |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 467 | "setenv bootargs root=/dev/ram rw " \ |
| 468 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 469 | "tftp $ramdiskaddr $ramdiskfile;" \ |
| 470 | "tftp $loadaddr $bootfile;" \ |
Kumar Gala | 50c03c8 | 2007-11-27 22:42:34 -0600 | [diff] [blame] | 471 | "tftp $fdtaddr $fdtfile;" \ |
| 472 | "bootm $loadaddr $ramdiskaddr $fdtaddr" |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 473 | |
Ed Swarthout | 837f1ba | 2007-07-27 01:50:51 -0500 | [diff] [blame] | 474 | #define CONFIG_BOOTCOMMAND \ |
| 475 | "setenv bootargs root=/dev/$bdev rw " \ |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 476 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 477 | "tftp $loadaddr $bootfile;" \ |
Kumar Gala | 50c03c8 | 2007-11-27 22:42:34 -0600 | [diff] [blame] | 478 | "tftp $fdtaddr $fdtfile;" \ |
| 479 | "bootm $loadaddr - $fdtaddr" |
Jon Loeliger | 0cde4b0 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 480 | |
| 481 | #endif /* __CONFIG_H */ |