blob: b19ba988dbfb030ceb49a0ec47bad2a93a1f37d4 [file] [log] [blame]
rickb841b6e2017-05-18 14:37:53 +08001/dts-v1/;
2/ {
3 compatible = "nds32 ae3xx";
4 #address-cells = <1>;
5 #size-cells = <1>;
6 interrupt-parent = <&intc>;
7
8 aliases {
9 uart0 = &serial0;
rickbe71a172017-05-23 13:48:27 +080010 ethernet0 = &mac0;
rick7b1a50b2017-08-28 15:13:09 +080011 spi0 = &spi;
rickb841b6e2017-05-18 14:37:53 +080012 } ;
13
14 chosen {
15 /* bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug bootmem_debug memblock=debug loglevel=7"; */
16 bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7";
17 stdout-path = "uart0:38400n8";
18 tick-timer = &timer0;
19 };
20
21 memory@0 {
22 device_type = "memory";
23 reg = <0x00000000 0x40000000>;
24 };
25
rick7b1a50b2017-08-28 15:13:09 +080026 spiclk: virt_100mhz {
27 #clock-cells = <0>;
28 compatible = "fixed-clock";
29 clock-frequency = <100000000>;
30 };
31
rickb841b6e2017-05-18 14:37:53 +080032 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
35 cpu@0 {
36 compatible = "andestech,n13";
37 reg = <0>;
38 /* FIXME: to fill correct frqeuency */
39 clock-frequency = <60000000>;
40 };
41 };
42
43 intc: interrupt-controller {
44 compatible = "andestech,atnointc010";
45 #interrupt-cells = <1>;
46 interrupt-controller;
47 };
48
49 serial0: serial@f0300000 {
50 compatible = "andestech,uart16550", "ns16550a";
51 reg = <0xf0300000 0x1000>;
52 interrupts = <7 4>;
53 clock-frequency = <14745600>;
54 reg-shift = <2>;
55 reg-offset = <32>;
56 no-loopback-test = <1>;
57 };
58
59 timer0: timer@f0400000 {
60 compatible = "andestech,atcpit100";
61 reg = <0xf0400000 0x1000>;
62 interrupts = <2 4>;
63 clock-frequency = <30000000>;
64 };
65
rickbe71a172017-05-23 13:48:27 +080066 mac0: mac@e0100000 {
67 compatible = "andestech,atmac100";
68 reg = <0xe0100000 0x1000>;
69 interrupts = <25 4>;
70 };
71
Rick Chenfebcd972017-06-01 15:09:25 +080072 mmc0: mmc@f0e00000 {
73 compatible = "andestech,atsdc010";
74 max-frequency = <100000000>;
75 fifo-depth = <0x10>;
76 reg = <0xf0e00000 0x1000>;
77 interrupts = <17 4>;
78 };
79
rickb841b6e2017-05-18 14:37:53 +080080 nor@0,0 {
81 compatible = "cfi-flash";
82 reg = <0x88000000 0x1000>;
83 bank-width = <2>;
84 device-width = <1>;
85 };
86
rick7b1a50b2017-08-28 15:13:09 +080087 spi: spi@f0b00000 {
88 compatible = "andestech,atcspi200";
89 reg = <0xf0b00000 0x1000>;
90 #address-cells = <1>;
91 #size-cells = <0>;
92 num-cs = <1>;
93 clocks = <&spiclk>;
94 interrupts = <3 4>;
95 flash@0 {
96 compatible = "spi-flash";
97 spi-max-frequency = <50000000>;
98 reg = <0>;
99 spi-cpol;
100 spi-cpha;
101 };
102 };
rickb841b6e2017-05-18 14:37:53 +0800103};