blob: 438d9025f3fcaeb4daaeaa593ebf9f902b90b2cf [file] [log] [blame]
Jon Loeligerdebb7352006-04-26 17:58:56 -05001/*
Jon Loeligercb5965f2006-05-31 12:44:44 -05002 * Copyright 2006 Freescale Semiconductor
3 * Jeff Brown
Jon Loeligerdebb7352006-04-26 17:58:56 -05004 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
26#include <watchdog.h>
27#include <command.h>
28#include <asm/cache.h>
Becky Brucee34a0e92008-05-08 19:02:51 -050029#include <asm/mmu.h>
Jon Loeligerdebb7352006-04-26 17:58:56 -050030#include <mpc86xx.h>
Andy Fleming75b9d4a2008-08-31 16:33:26 -050031#include <tsec.h>
Becky Bruce4f93f8b2008-01-23 16:31:06 -060032#include <asm/fsl_law.h>
Jon Loeligerdebb7352006-04-26 17:58:56 -050033
Kumar Gala480f6172009-06-18 08:23:01 -050034struct cpu_type cpu_type_list [] = {
35 CPU_TYPE_ENTRY(8610, 8610),
36 CPU_TYPE_ENTRY(8641, 8641),
37 CPU_TYPE_ENTRY(8641D, 8641D),
38};
39
40struct cpu_type *identify_cpu(u32 ver)
41{
42 int i;
43 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
44 if (cpu_type_list[i].soc_ver == ver)
45 return &cpu_type_list[i];
46
47 return NULL;
48}
Jon Loeligerdebb7352006-04-26 17:58:56 -050049
Peter Tyser4ef630d2009-02-05 11:25:25 -060050/*
51 * Default board reset function
52 */
53static void
54__board_reset(void)
55{
56 /* Do nothing */
57}
Peter Tyserf9a109b2009-04-20 11:08:46 -050058void board_reset(void) __attribute__((weak, alias("__board_reset")));
Peter Tyser4ef630d2009-02-05 11:25:25 -060059
60
Jon Loeligerffff3ae2006-08-22 12:06:18 -050061int
62checkcpu(void)
Jon Loeligerdebb7352006-04-26 17:58:56 -050063{
64 sys_info_t sysinfo;
65 uint pvr, svr;
66 uint ver;
67 uint major, minor;
Peter Tysera1c8a712009-02-06 14:30:40 -060068 char buf1[32], buf2[32];
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
Jon Loeliger9553df82007-10-16 15:26:51 -050070 volatile ccsr_gur_t *gur = &immap->im_gur;
Kumar Gala480f6172009-06-18 08:23:01 -050071 struct cpu_type *cpu;
Peter Tysera1c8a712009-02-06 14:30:40 -060072 uint msscr0 = mfspr(MSSCR0);
Jon Loeligerdebb7352006-04-26 17:58:56 -050073
74 svr = get_svr();
Andy Fleming1ced1212008-02-06 01:19:40 -060075 ver = SVR_SOC_VER(svr);
Jon Loeligerdebb7352006-04-26 17:58:56 -050076 major = SVR_MAJ(svr);
77 minor = SVR_MIN(svr);
78
Peter Tysera1c8a712009-02-06 14:30:40 -060079 puts("CPU: ");
80
Kumar Gala480f6172009-06-18 08:23:01 -050081 cpu = identify_cpu(ver);
82 if (cpu) {
83 puts(cpu->name);
84 } else {
Jon Loeligerdebb7352006-04-26 17:58:56 -050085 puts("Unknown");
Jon Loeligerdebb7352006-04-26 17:58:56 -050086 }
Kumar Gala480f6172009-06-18 08:23:01 -050087
Jon Loeligerdebb7352006-04-26 17:58:56 -050088 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
Peter Tysera1c8a712009-02-06 14:30:40 -060089 puts("Core: ");
90
91 pvr = get_pvr();
92 ver = PVR_E600_VER(pvr);
93 major = PVR_E600_MAJ(pvr);
94 minor = PVR_E600_MIN(pvr);
95
96 printf("E600 Core %d", (msscr0 & 0x20) ? 1 : 0 );
97 if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE)
98 puts("\n Core1Translation Enabled");
99 debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr);
100
101 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
Jon Loeligerdebb7352006-04-26 17:58:56 -0500102
103 get_sys_info(&sysinfo);
104
Peter Tysera1c8a712009-02-06 14:30:40 -0600105 puts("Clock Configuration:\n");
106 printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freqProcessor));
107 printf("MPX:%-4s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
108 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
109 strmhz(buf1, sysinfo.freqSystemBus / 2),
110 strmhz(buf2, sysinfo.freqSystemBus));
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500111
Trent Piephoada591d2008-12-03 15:16:37 -0800112 if (sysinfo.freqLocalBus > LCRR_CLKDIV) {
Peter Tysera1c8a712009-02-06 14:30:40 -0600113 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
Jon Loeligerdebb7352006-04-26 17:58:56 -0500114 } else {
Wolfgang Denka9f3acb2009-01-12 14:50:35 +0100115 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
Trent Piephoada591d2008-12-03 15:16:37 -0800116 sysinfo.freqLocalBus);
Jon Loeligerdebb7352006-04-26 17:58:56 -0500117 }
118
Peter Tysera1c8a712009-02-06 14:30:40 -0600119 puts("L1: D-cache 32 KB enabled\n");
120 puts(" I-cache 32 KB enabled\n");
121
122 puts("L2: ");
123 if (get_l2cr() & 0x80000000) {
124#if defined(CONFIG_MPC8610)
125 puts("256");
126#elif defined(CONFIG_MPC8641)
127 puts("512");
128#endif
129 puts(" KB enabled\n");
130 } else {
Jon Loeligercb5965f2006-05-31 12:44:44 -0500131 puts("Disabled\n");
Peter Tysera1c8a712009-02-06 14:30:40 -0600132 }
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500133
134 return 0;
Jon Loeligerdebb7352006-04-26 17:58:56 -0500135}
136
137
Jon Loeligerdebb7352006-04-26 17:58:56 -0500138void
Jon Loeliger126aa702006-05-30 17:47:00 -0500139do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
Jon Loeligerdebb7352006-04-26 17:58:56 -0500140{
Peter Tyser4ef630d2009-02-05 11:25:25 -0600141 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
142 volatile ccsr_gur_t *gur = &immap->im_gur;
Jon Loeligerdebb7352006-04-26 17:58:56 -0500143
Peter Tyser4ef630d2009-02-05 11:25:25 -0600144 /* Attempt board-specific reset */
145 board_reset();
Jon Loeligerdebb7352006-04-26 17:58:56 -0500146
Peter Tyser4ef630d2009-02-05 11:25:25 -0600147 /* Next try asserting HRESET_REQ */
148 out_be32(&gur->rstcr, MPC86xx_RSTCR_HRST_REQ);
Jon Loeligerdebb7352006-04-26 17:58:56 -0500149
Peter Tyser4ef630d2009-02-05 11:25:25 -0600150 while (1)
151 ;
Jon Loeligerdebb7352006-04-26 17:58:56 -0500152}
153
154
Jon Loeligerdebb7352006-04-26 17:58:56 -0500155/*
156 * Get timebase clock frequency
157 */
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500158unsigned long
159get_tbclk(void)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500160{
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500161 sys_info_t sys_info;
Jon Loeligerdebb7352006-04-26 17:58:56 -0500162
163 get_sys_info(&sys_info);
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500164 return (sys_info.freqSystemBus + 3L) / 4L;
Jon Loeligerdebb7352006-04-26 17:58:56 -0500165}
166
Jon Loeligerdebb7352006-04-26 17:58:56 -0500167
168#if defined(CONFIG_WATCHDOG)
169void
170watchdog_reset(void)
171{
Jason Jin3473ab72008-05-13 11:50:36 +0800172#if defined(CONFIG_MPC8610)
173 /*
174 * This actually feed the hard enabled watchdog.
175 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
Jason Jin3473ab72008-05-13 11:50:36 +0800177 volatile ccsr_wdt_t *wdt = &immap->im_wdt;
178 volatile ccsr_gur_t *gur = &immap->im_gur;
179 u32 tmp = gur->pordevsr;
180
181 if (tmp & 0x4000) {
182 wdt->swsrr = 0x556c;
183 wdt->swsrr = 0xaa39;
184 }
185#endif
Jon Loeligerdebb7352006-04-26 17:58:56 -0500186}
187#endif /* CONFIG_WATCHDOG */
188
Jon Loeligerdebb7352006-04-26 17:58:56 -0500189
190#if defined(CONFIG_DDR_ECC)
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500191void
192dma_init(void)
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500193{
Peter Tyser2f21ce42009-05-21 12:10:00 -0500194 volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
Peter Tyserb1f12652009-05-21 12:09:59 -0500195 volatile fsl_dma_t *dma = &dma_base->dma[0];
Jon Loeligerdebb7352006-04-26 17:58:56 -0500196
Peter Tyserb1f12652009-05-21 12:09:59 -0500197 dma->satr = 0x00040000;
198 dma->datr = 0x00040000;
Peter Tyser2f21ce42009-05-21 12:10:00 -0500199 dma->sr = 0xffffffff; /* clear any errors */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500200 asm("sync; isync");
Jon Loeligerdebb7352006-04-26 17:58:56 -0500201}
202
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500203uint
204dma_check(void)
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500205{
Peter Tyser2f21ce42009-05-21 12:10:00 -0500206 volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
Peter Tyserb1f12652009-05-21 12:09:59 -0500207 volatile fsl_dma_t *dma = &dma_base->dma[0];
208 volatile uint status = dma->sr;
Jon Loeligerdebb7352006-04-26 17:58:56 -0500209
210 /* While the channel is busy, spin */
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500211 while ((status & 4) == 4) {
Peter Tyserb1f12652009-05-21 12:09:59 -0500212 status = dma->sr;
Jon Loeligerdebb7352006-04-26 17:58:56 -0500213 }
214
Peter Tyser2f21ce42009-05-21 12:10:00 -0500215 /* clear MR[CS] channel start bit */
216 dma->mr &= 0x00000001;
217 asm("sync;isync");
218
Jon Loeligerdebb7352006-04-26 17:58:56 -0500219 if (status != 0) {
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500220 printf("DMA Error: status = %x\n", status);
Jon Loeligerdebb7352006-04-26 17:58:56 -0500221 }
222 return status;
223}
224
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500225int
226dma_xfer(void *dest, uint count, void *src)
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500227{
Peter Tyser2f21ce42009-05-21 12:10:00 -0500228 volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
Peter Tyserb1f12652009-05-21 12:09:59 -0500229 volatile fsl_dma_t *dma = &dma_base->dma[0];
Jon Loeligerdebb7352006-04-26 17:58:56 -0500230
Peter Tyserb1f12652009-05-21 12:09:59 -0500231 dma->dar = (uint) dest;
232 dma->sar = (uint) src;
233 dma->bcr = count;
234 dma->mr = 0xf000004;
Jon Loeligerdebb7352006-04-26 17:58:56 -0500235 asm("sync;isync");
Peter Tyserb1f12652009-05-21 12:09:59 -0500236 dma->mr = 0xf000005;
Jon Loeligerdebb7352006-04-26 17:58:56 -0500237 asm("sync;isync");
238 return dma_check();
239}
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500240
Jon Loeligerdebb7352006-04-26 17:58:56 -0500241#endif /* CONFIG_DDR_ECC */
242
243
Becky Bruce4f93f8b2008-01-23 16:31:06 -0600244/*
245 * Print out the state of various machine registers.
Becky Brucee34a0e92008-05-08 19:02:51 -0500246 * Currently prints out LAWs, BR0/OR0, and BATs
Becky Bruce4f93f8b2008-01-23 16:31:06 -0600247 */
248void mpc86xx_reginfo(void)
249{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250 immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
Becky Bruce4f93f8b2008-01-23 16:31:06 -0600251 ccsr_lbc_t *lbc = &immap->im_lbc;
252
Becky Brucee34a0e92008-05-08 19:02:51 -0500253 print_bats();
Becky Bruce4f93f8b2008-01-23 16:31:06 -0600254 print_laws();
255
256 printf ("Local Bus Controller Registers\n"
257 "\tBR0\t0x%08X\tOR0\t0x%08X \n", in_be32(&lbc->br0), in_be32(&lbc->or0));
258 printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", in_be32(&lbc->br1), in_be32(&lbc->or1));
259 printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", in_be32(&lbc->br2), in_be32(&lbc->or2));
260 printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", in_be32(&lbc->br3), in_be32(&lbc->or3));
261 printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", in_be32(&lbc->br4), in_be32(&lbc->or4));
262 printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", in_be32(&lbc->br5), in_be32(&lbc->or5));
263 printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", in_be32(&lbc->br6), in_be32(&lbc->or6));
264 printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", in_be32(&lbc->br7), in_be32(&lbc->or7));
Jon Loeligerdebb7352006-04-26 17:58:56 -0500265
266}
Ben Warrendd354792008-06-23 22:57:27 -0700267
Andy Fleming75b9d4a2008-08-31 16:33:26 -0500268/*
269 * Initializes on-chip ethernet controllers.
270 * to override, implement board_eth_init()
Ben Warrendd354792008-06-23 22:57:27 -0700271 */
Ben Warrendd354792008-06-23 22:57:27 -0700272int cpu_eth_init(bd_t *bis)
273{
Andy Fleming75b9d4a2008-08-31 16:33:26 -0500274#if defined(CONFIG_TSEC_ENET)
275 tsec_standard_init(bis);
Ben Warrendd354792008-06-23 22:57:27 -0700276#endif
Andy Fleming75b9d4a2008-08-31 16:33:26 -0500277
Ben Warrendd354792008-06-23 22:57:27 -0700278 return 0;
279}