Shengzhou Liu | c4d0e81 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2013 Freescale Semiconductor, Inc. |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | #ifndef __DDR_H__ |
| 8 | #define __DDR_H__ |
| 9 | struct board_specific_parameters { |
| 10 | u32 n_ranks; |
| 11 | u32 datarate_mhz_high; |
| 12 | u32 rank_gb; |
| 13 | u32 clk_adjust; |
| 14 | u32 wrlvl_start; |
| 15 | u32 wrlvl_ctl_2; |
| 16 | u32 wrlvl_ctl_3; |
Shengzhou Liu | c4d0e81 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 17 | }; |
| 18 | |
| 19 | /* |
| 20 | * These tables contain all valid speeds we want to override with board |
| 21 | * specific parameters. datarate_mhz_high values need to be in ascending order |
| 22 | * for each n_ranks group. |
| 23 | */ |
| 24 | |
| 25 | static const struct board_specific_parameters udimm0[] = { |
| 26 | /* |
| 27 | * memory controller 0 |
Shengzhou Liu | 40483e1 | 2014-05-20 12:08:20 +0800 | [diff] [blame] | 28 | * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | |
| 29 | * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |
Shengzhou Liu | c4d0e81 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 30 | */ |
York Sun | ed9e4e4 | 2014-10-27 11:31:32 -0700 | [diff] [blame] | 31 | {2, 1200, 0, 5, 7, 0x0708090a, 0x0b0c0d09}, |
| 32 | {2, 1400, 0, 5, 7, 0x08090a0c, 0x0d0e0f0a}, |
| 33 | {2, 1700, 0, 5, 8, 0x090a0b0c, 0x0e10110c}, |
| 34 | {2, 1900, 0, 5, 8, 0x090b0c0f, 0x1012130d}, |
| 35 | {2, 2140, 0, 5, 8, 0x090b0c0f, 0x1012130d}, |
Shengzhou Liu | 40483e1 | 2014-05-20 12:08:20 +0800 | [diff] [blame] | 36 | {1, 1200, 0, 5, 7, 0x0808090a, 0x0b0c0c0a}, |
| 37 | {1, 1500, 0, 5, 6, 0x07070809, 0x0a0b0b09}, |
| 38 | {1, 1600, 0, 5, 8, 0x090b0b0d, 0x0d0e0f0b}, |
York Sun | ed9e4e4 | 2014-10-27 11:31:32 -0700 | [diff] [blame] | 39 | {1, 1700, 0, 4, 8, 0x080a0a0c, 0x0c0d0e0a}, |
| 40 | {1, 1900, 0, 5, 8, 0x090a0c0d, 0x0e0f110c}, |
Shengzhou Liu | 40483e1 | 2014-05-20 12:08:20 +0800 | [diff] [blame] | 41 | {1, 2140, 0, 4, 8, 0x090a0b0d, 0x0e0f110b}, |
Shengzhou Liu | c4d0e81 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 42 | {} |
| 43 | }; |
| 44 | |
| 45 | static const struct board_specific_parameters rdimm0[] = { |
| 46 | /* |
| 47 | * memory controller 0 |
Shengzhou Liu | 3fdc827 | 2014-01-13 13:01:06 +0800 | [diff] [blame] | 48 | * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | |
| 49 | * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |
Shengzhou Liu | c4d0e81 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 50 | */ |
Shengzhou Liu | 3fdc827 | 2014-01-13 13:01:06 +0800 | [diff] [blame] | 51 | /* TODO: need tuning these parameters if RDIMM is used */ |
| 52 | {4, 1350, 0, 5, 9, 0x08070605, 0x06070806}, |
| 53 | {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906}, |
| 54 | {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07}, |
| 55 | {2, 1350, 0, 5, 9, 0x08070605, 0x06070806}, |
| 56 | {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06}, |
| 57 | {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07}, |
| 58 | {1, 1350, 0, 5, 9, 0x08070605, 0x06070806}, |
| 59 | {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06}, |
| 60 | {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07}, |
Shengzhou Liu | c4d0e81 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 61 | {} |
| 62 | }; |
| 63 | |
Shengzhou Liu | c4d0e81 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 64 | static const struct board_specific_parameters *udimms[] = { |
| 65 | udimm0, |
| 66 | }; |
| 67 | |
Shengzhou Liu | c4d0e81 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 68 | static const struct board_specific_parameters *rdimms[] = { |
| 69 | rdimm0, |
| 70 | }; |
Shengzhou Liu | c4d0e81 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 71 | #endif |