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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk2262cfe2002-11-18 00:14:45 +00002/*
Graeme Russdbf71152011-04-13 19:43:26 +10003 * (C) Copyright 2008-2011
4 * Graeme Russ, <graeme.russ@gmail.com>
5 *
wdenk2262cfe2002-11-18 00:14:45 +00006 * (C) Copyright 2002
Albert ARIBAUDfa82f872011-08-04 18:45:45 +02007 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
wdenk8bde7f72003-06-27 21:31:46 +00008 *
wdenk2262cfe2002-11-18 00:14:45 +00009 * (C) Copyright 2002
10 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
11 * Marius Groeger <mgroeger@sysgo.de>
12 *
13 * (C) Copyright 2002
14 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
15 * Alex Zuepke <azu@sysgo.de>
16 *
Bin Meng52f952b2014-11-09 22:18:56 +080017 * Part of this file is adapted from coreboot
18 * src/arch/x86/lib/cpu.c
wdenk2262cfe2002-11-18 00:14:45 +000019 */
20
wdenk2262cfe2002-11-18 00:14:45 +000021#include <common.h>
22#include <command.h>
Bin Meng6e6f4ce2015-06-17 11:15:36 +080023#include <dm.h>
Simon Glass200182a2014-10-10 08:21:55 -060024#include <errno.h>
25#include <malloc.h>
Bin Mengd8906c12016-06-08 05:07:38 -070026#include <syscon.h>
Bin Menga0609a82018-07-18 21:42:15 -070027#include <asm/acpi.h>
Bin Mengb7279612017-04-21 07:24:32 -070028#include <asm/acpi_s3.h>
Bin Meng3a34cae2017-04-21 07:24:37 -070029#include <asm/acpi_table.h>
Stefan Reinauer095593c2012-12-02 04:49:50 +000030#include <asm/control_regs.h>
Bin Mengd19c9072016-05-11 07:45:01 -070031#include <asm/coreboot_tables.h>
Simon Glass200182a2014-10-10 08:21:55 -060032#include <asm/cpu.h>
Bin Meng6e6f4ce2015-06-17 11:15:36 +080033#include <asm/lapic.h>
Simon Glasse77b62e2016-03-11 22:07:11 -070034#include <asm/microcode.h>
Bin Meng6e6f4ce2015-06-17 11:15:36 +080035#include <asm/mp.h>
Bin Meng0c2b7ee2016-05-11 07:45:00 -070036#include <asm/mrccache.h>
Bin Meng43dd22f2015-07-06 16:31:30 +080037#include <asm/msr.h>
38#include <asm/mtrr.h>
Simon Glassa49e3c72014-11-12 22:42:26 -070039#include <asm/post.h>
Graeme Russc53fd2b2011-02-12 15:11:30 +110040#include <asm/processor.h>
Graeme Russ0c24c9c2011-02-12 15:11:32 +110041#include <asm/processor-flags.h>
Graeme Russ3f5f18d2008-12-07 10:29:02 +110042#include <asm/interrupt.h>
Bin Meng5e2400e2015-04-24 18:10:04 +080043#include <asm/tables.h>
Gabe Black60a9b6b2011-11-16 23:32:50 +000044#include <linux/compiler.h>
wdenk2262cfe2002-11-18 00:14:45 +000045
Bin Meng52f952b2014-11-09 22:18:56 +080046DECLARE_GLOBAL_DATA_PTR;
47
Bin Meng52f952b2014-11-09 22:18:56 +080048static const char *const x86_vendor_name[] = {
49 [X86_VENDOR_INTEL] = "Intel",
50 [X86_VENDOR_CYRIX] = "Cyrix",
51 [X86_VENDOR_AMD] = "AMD",
52 [X86_VENDOR_UMC] = "UMC",
53 [X86_VENDOR_NEXGEN] = "NexGen",
54 [X86_VENDOR_CENTAUR] = "Centaur",
55 [X86_VENDOR_RISE] = "Rise",
56 [X86_VENDOR_TRANSMETA] = "Transmeta",
57 [X86_VENDOR_NSC] = "NSC",
58 [X86_VENDOR_SIS] = "SiS",
59};
60
Gabe Blackf30fc4d2012-10-20 12:33:10 +000061int __weak x86_cleanup_before_linux(void)
62{
Simon Glass79497032013-04-17 16:13:35 +000063#ifdef CONFIG_BOOTSTAGE_STASH
Simon Glassee2b2432015-03-02 17:04:37 -070064 bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR,
Simon Glass79497032013-04-17 16:13:35 +000065 CONFIG_BOOTSTAGE_STASH_SIZE);
66#endif
67
Gabe Blackf30fc4d2012-10-20 12:33:10 +000068 return 0;
69}
70
Graeme Russd6532442011-12-27 22:46:43 +110071int x86_init_cache(void)
72{
73 enable_caches();
74
wdenk2262cfe2002-11-18 00:14:45 +000075 return 0;
76}
Graeme Russd6532442011-12-27 22:46:43 +110077int init_cache(void) __attribute__((weak, alias("x86_init_cache")));
wdenk2262cfe2002-11-18 00:14:45 +000078
Graeme Russ717979f2011-11-08 02:33:13 +000079void flush_cache(unsigned long dummy1, unsigned long dummy2)
wdenk2262cfe2002-11-18 00:14:45 +000080{
81 asm("wbinvd\n");
wdenk2262cfe2002-11-18 00:14:45 +000082}
Graeme Russ3f5f18d2008-12-07 10:29:02 +110083
Stefan Reinauer095593c2012-12-02 04:49:50 +000084/* Define these functions to allow ehch-hcd to function */
85void flush_dcache_range(unsigned long start, unsigned long stop)
86{
87}
88
89void invalidate_dcache_range(unsigned long start, unsigned long stop)
90{
91}
Simon Glass89371402013-02-28 19:26:11 +000092
93void dcache_enable(void)
94{
95 enable_caches();
96}
97
98void dcache_disable(void)
99{
100 disable_caches();
101}
102
103void icache_enable(void)
104{
105}
106
107void icache_disable(void)
108{
109}
110
111int icache_status(void)
112{
113 return 1;
114}
Simon Glass7bddac92014-10-10 08:21:52 -0600115
Bin Meng52f952b2014-11-09 22:18:56 +0800116const char *cpu_vendor_name(int vendor)
117{
118 const char *name;
119 name = "<invalid cpu vendor>";
Heinrich Schuchardt39670c32017-11-20 19:45:56 +0100120 if (vendor < ARRAY_SIZE(x86_vendor_name) &&
121 x86_vendor_name[vendor])
Bin Meng52f952b2014-11-09 22:18:56 +0800122 name = x86_vendor_name[vendor];
123
124 return name;
125}
126
Simon Glass727c1a92014-11-10 18:00:26 -0700127char *cpu_get_name(char *name)
Bin Meng52f952b2014-11-09 22:18:56 +0800128{
Simon Glass727c1a92014-11-10 18:00:26 -0700129 unsigned int *name_as_ints = (unsigned int *)name;
Bin Meng52f952b2014-11-09 22:18:56 +0800130 struct cpuid_result regs;
Simon Glass727c1a92014-11-10 18:00:26 -0700131 char *ptr;
Bin Meng52f952b2014-11-09 22:18:56 +0800132 int i;
133
Simon Glass727c1a92014-11-10 18:00:26 -0700134 /* This bit adds up to 48 bytes */
Bin Meng52f952b2014-11-09 22:18:56 +0800135 for (i = 0; i < 3; i++) {
136 regs = cpuid(0x80000002 + i);
137 name_as_ints[i * 4 + 0] = regs.eax;
138 name_as_ints[i * 4 + 1] = regs.ebx;
139 name_as_ints[i * 4 + 2] = regs.ecx;
140 name_as_ints[i * 4 + 3] = regs.edx;
141 }
Simon Glass727c1a92014-11-10 18:00:26 -0700142 name[CPU_MAX_NAME_LEN - 1] = '\0';
Bin Meng52f952b2014-11-09 22:18:56 +0800143
144 /* Skip leading spaces. */
Simon Glass727c1a92014-11-10 18:00:26 -0700145 ptr = name;
146 while (*ptr == ' ')
147 ptr++;
Bin Meng52f952b2014-11-09 22:18:56 +0800148
Simon Glass727c1a92014-11-10 18:00:26 -0700149 return ptr;
Bin Meng52f952b2014-11-09 22:18:56 +0800150}
151
Simon Glass727c1a92014-11-10 18:00:26 -0700152int default_print_cpuinfo(void)
Simon Glass92cc94a2014-10-10 08:21:54 -0600153{
Bin Meng52f952b2014-11-09 22:18:56 +0800154 printf("CPU: %s, vendor %s, device %xh\n",
155 cpu_has_64bit() ? "x86_64" : "x86",
156 cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device);
Simon Glass92cc94a2014-10-10 08:21:54 -0600157
Bin Mengb7279612017-04-21 07:24:32 -0700158#ifdef CONFIG_HAVE_ACPI_RESUME
159 debug("ACPI previous sleep state: %s\n",
160 acpi_ss_string(gd->arch.prev_sleep_state));
161#endif
162
Simon Glass92cc94a2014-10-10 08:21:54 -0600163 return 0;
164}
Simon Glass200182a2014-10-10 08:21:55 -0600165
Simon Glassa49e3c72014-11-12 22:42:26 -0700166void show_boot_progress(int val)
167{
Simon Glassa49e3c72014-11-12 22:42:26 -0700168 outb(val, POST_PORT);
169}
Bin Meng5e2400e2015-04-24 18:10:04 +0800170
Bin Meng1ab2c012018-06-17 05:57:53 -0700171#if !defined(CONFIG_SYS_COREBOOT) && !defined(CONFIG_EFI_STUB)
Bin Meng1e2f7b92016-05-11 07:44:56 -0700172/*
173 * Implement a weak default function for boards that optionally
174 * need to clean up the system before jumping to the kernel.
175 */
176__weak void board_final_cleanup(void)
177{
178}
179
Bin Meng5e2400e2015-04-24 18:10:04 +0800180int last_stage_init(void)
181{
Bin Meng474a62b2018-07-18 21:42:16 -0700182 struct acpi_fadt __maybe_unused *fadt;
183
Bin Mengbffd7982017-04-21 07:24:41 -0700184 board_final_cleanup();
185
Bin Meng474a62b2018-07-18 21:42:16 -0700186#ifdef CONFIG_HAVE_ACPI_RESUME
187 fadt = acpi_find_fadt();
Bin Meng3a34cae2017-04-21 07:24:37 -0700188
Bin Meng474a62b2018-07-18 21:42:16 -0700189 if (fadt && gd->arch.prev_sleep_state == ACPI_S3)
Bin Meng0f4e2582017-04-21 07:24:44 -0700190 acpi_resume(fadt);
Bin Meng3a34cae2017-04-21 07:24:37 -0700191#endif
192
Bin Meng5e2400e2015-04-24 18:10:04 +0800193 write_tables();
194
Bin Meng474a62b2018-07-18 21:42:16 -0700195#ifdef CONFIG_GENERATE_ACPI_TABLE
196 fadt = acpi_find_fadt();
197
198 /* Don't touch ACPI hardware on HW reduced platforms */
199 if (fadt && !(fadt->flags & ACPI_FADT_HW_REDUCED_ACPI)) {
200 /*
201 * Other than waiting for OSPM to request us to switch to ACPI
202 * mode, do it by ourselves, since SMI will not be triggered.
203 */
204 enter_acpi_mode(fadt->pm1a_cnt_blk);
205 }
206#endif
207
Bin Meng5e2400e2015-04-24 18:10:04 +0800208 return 0;
209}
210#endif
Simon Glassbcb0c612015-04-29 22:26:01 -0600211
Simon Glassafd5d502016-01-17 16:11:28 -0700212static int x86_init_cpus(void)
Simon Glassbcb0c612015-04-29 22:26:01 -0600213{
Bin Meng6e6f4ce2015-06-17 11:15:36 +0800214#ifdef CONFIG_SMP
215 debug("Init additional CPUs\n");
216 x86_mp_init();
Bin Mengc77b8912015-07-22 01:21:12 -0700217#else
218 struct udevice *dev;
219
220 /*
221 * This causes the cpu-x86 driver to be probed.
222 * We don't check return value here as we want to allow boards
223 * which have not been converted to use cpu uclass driver to boot.
224 */
225 uclass_first_device(UCLASS_CPU, &dev);
Bin Meng6e6f4ce2015-06-17 11:15:36 +0800226#endif
227
Simon Glassbcb0c612015-04-29 22:26:01 -0600228 return 0;
229}
230
231int cpu_init_r(void)
232{
Simon Glassac643e02016-01-17 16:11:30 -0700233 struct udevice *dev;
234 int ret;
235
236 if (!ll_boot_init())
237 return 0;
238
239 ret = x86_init_cpus();
240 if (ret)
241 return ret;
242
243 /*
244 * Set up the northbridge, PCH and LPC if available. Note that these
245 * may have had some limited pre-relocation init if they were probed
246 * before relocation, but this is post relocation.
247 */
248 uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
249 uclass_first_device(UCLASS_PCH, &dev);
250 uclass_first_device(UCLASS_LPC, &dev);
Simon Glasse49ccea2015-08-04 12:34:00 -0600251
Bin Mengd8906c12016-06-08 05:07:38 -0700252 /* Set up pin control if available */
253 ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev);
254 debug("%s, pinctrl=%p, ret=%d\n", __func__, dev, ret);
255
Simon Glasse49ccea2015-08-04 12:34:00 -0600256 return 0;
Simon Glassbcb0c612015-04-29 22:26:01 -0600257}
Bin Meng0c2b7ee2016-05-11 07:45:00 -0700258
259#ifndef CONFIG_EFI_STUB
260int reserve_arch(void)
261{
262#ifdef CONFIG_ENABLE_MRC_CACHE
Bin Mengd19c9072016-05-11 07:45:01 -0700263 mrccache_reserve();
Bin Meng0c2b7ee2016-05-11 07:45:00 -0700264#endif
Bin Mengd19c9072016-05-11 07:45:01 -0700265
266#ifdef CONFIG_SEABIOS
267 high_table_reserve();
268#endif
269
Bin Meng5ae5aa92017-04-21 07:24:47 -0700270#ifdef CONFIG_HAVE_ACPI_RESUME
271 acpi_s3_reserve();
272
273#ifdef CONFIG_HAVE_FSP
Bin Mengba658082017-04-21 07:24:39 -0700274 /*
275 * Save stack address to CMOS so that at next S3 boot,
276 * we can use it as the stack address for fsp_contiue()
277 */
278 fsp_save_s3_stack();
Bin Meng5ae5aa92017-04-21 07:24:47 -0700279#endif /* CONFIG_HAVE_FSP */
280#endif /* CONFIG_HAVE_ACPI_RESUME */
Bin Mengba658082017-04-21 07:24:39 -0700281
Bin Mengd19c9072016-05-11 07:45:01 -0700282 return 0;
Bin Meng0c2b7ee2016-05-11 07:45:00 -0700283}
284#endif