blob: 7d9541bd83a06fd443b20e3516c6c96be1cb079f [file] [log] [blame]
Dirk Eibacha3f9d6c2015-10-28 11:46:32 +01001/*
2 * (C) Copyright 2014
3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
4 *
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12/*
13 * High Level Configuration Options
14 */
15#define CONFIG_E300 1 /* E300 family */
16#define CONFIG_MPC83xx 1 /* MPC83xx family */
17#define CONFIG_MPC830x 1 /* MPC830x family */
18#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
19#define CONFIG_STRIDER 1 /* STRIDER board specific */
20
21#define CONFIG_SYS_TEXT_BASE 0xFE000000
22
23#ifdef CONFIG_STRIDER_CPU
24#define CONFIG_IDENT_STRING " strider cpu 0.01"
25#else
26#define CONFIG_IDENT_STRING " strider con 0.01"
27#endif
28
29#define CONFIG_BOARD_EARLY_INIT_F
30#define CONFIG_BOARD_EARLY_INIT_R
31#define CONFIG_LAST_STAGE_INIT
32
Dirk Eibacha3f9d6c2015-10-28 11:46:32 +010033#define CONFIG_MMC
34#define CONFIG_FSL_ESDHC
35#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
36#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
37
38#define CONFIG_CMD_MMC
39#define CONFIG_GENERIC_MMC
40#define CONFIG_DOS_PARTITION
41#define CONFIG_CMD_EXT2
42
43#define CONFIG_CMD_MEMTEST
44#define CONFIG_SYS_ALT_MEMTEST
45
46#define CONFIG_CMD_FPGAD
47#define CONFIG_CMD_IOLOOP
48
49/*
50 * System Clock Setup
51 */
52#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
53#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
54
55/*
56 * Hardware Reset Configuration Word
57 * if CLKIN is 66.66MHz, then
58 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
59 * We choose the A type silicon as default, so the core is 400Mhz.
60 */
61#define CONFIG_SYS_HRCW_LOW (\
62 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
63 HRCWL_DDR_TO_SCB_CLK_2X1 |\
64 HRCWL_SVCOD_DIV_2 |\
65 HRCWL_CSB_TO_CLKIN_4X1 |\
66 HRCWL_CORE_TO_CSB_3X1)
67/*
68 * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
69 * in 8308's HRCWH according to the manual, but original Freescale's
70 * code has them and I've expirienced some problems using the board
71 * with BDI3000 attached when I've tried to set these bits to zero
72 * (UART doesn't work after the 'reset run' command).
73 */
74#define CONFIG_SYS_HRCW_HIGH (\
75 HRCWH_PCI_HOST |\
76 HRCWH_PCI1_ARBITER_ENABLE |\
77 HRCWH_CORE_ENABLE |\
78 HRCWH_FROM_0XFFF00100 |\
79 HRCWH_BOOTSEQ_DISABLE |\
80 HRCWH_SW_WATCHDOG_DISABLE |\
81 HRCWH_ROM_LOC_LOCAL_16BIT |\
82 HRCWH_RL_EXT_LEGACY |\
83 HRCWH_TSEC1M_IN_MII |\
84 HRCWH_TSEC2M_IN_RGMII |\
85 HRCWH_BIG_ENDIAN)
86
87/*
88 * System IO Config
89 */
90#define CONFIG_SYS_SICRH (\
91 SICRH_ESDHC_A_SD |\
92 SICRH_ESDHC_B_SD |\
93 SICRH_ESDHC_C_SD |\
94 SICRH_GPIO_A_GPIO |\
95 SICRH_GPIO_B_GPIO |\
96 SICRH_IEEE1588_A_GPIO |\
97 SICRH_USB |\
98 SICRH_GTM_GPIO |\
99 SICRH_IEEE1588_B_GPIO |\
100 SICRH_ETSEC2_GPIO |\
101 SICRH_GPIOSEL_1 |\
102 SICRH_TMROBI_V3P3 |\
103 SICRH_TSOBI1_V2P5 |\
104 SICRH_TSOBI2_V2P5) /* 0x0037f103 */
105#define CONFIG_SYS_SICRL (\
106 SICRL_SPI_PF0 |\
107 SICRL_UART_PF0 |\
108 SICRL_IRQ_PF0 |\
109 SICRL_I2C2_PF0 |\
110 SICRL_ETSEC1_TX_CLK) /* 0x00000000 */
111
112/*
113 * IMMR new address
114 */
115#define CONFIG_SYS_IMMR 0xE0000000
116
117/*
118 * SERDES
119 */
120#define CONFIG_FSL_SERDES
121#define CONFIG_FSL_SERDES1 0xe3000
122
123/*
124 * Arbiter Setup
125 */
126#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
127#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
128#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
129
130/*
131 * DDR Setup
132 */
133#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
134#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
135#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
136#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
137#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
138 | DDRCDR_PZ_LOZ \
139 | DDRCDR_NZ_LOZ \
140 | DDRCDR_ODT \
141 | DDRCDR_Q_DRN)
142 /* 0x7b880001 */
143/*
144 * Manually set up DDR parameters
145 * consist of one chip NT5TU64M16HG from NANYA
146 */
147
148#define CONFIG_SYS_DDR_SIZE 128 /* MB */
149
150#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
151#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
152 | CSCONFIG_ODT_RD_NEVER \
153 | CSCONFIG_ODT_WR_ONLY_CURRENT \
154 | CSCONFIG_BANK_BIT_3 \
155 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
156 /* 0x80010102 */
157#define CONFIG_SYS_DDR_TIMING_3 0
158#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
159 | (0 << TIMING_CFG0_WRT_SHIFT) \
160 | (0 << TIMING_CFG0_RRT_SHIFT) \
161 | (0 << TIMING_CFG0_WWT_SHIFT) \
162 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
163 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
164 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
165 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
166 /* 0x00260802 */
167#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
168 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
169 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
170 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
171 | (9 << TIMING_CFG1_REFREC_SHIFT) \
172 | (2 << TIMING_CFG1_WRREC_SHIFT) \
173 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
174 | (2 << TIMING_CFG1_WRTORD_SHIFT))
175 /* 0x26279222 */
176#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
177 | (4 << TIMING_CFG2_CPO_SHIFT) \
178 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
179 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
180 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
181 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
182 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
183 /* 0x021848c5 */
184#define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
185 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
186 /* 0x08240100 */
187#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
188 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
189 | SDRAM_CFG_DBW_16)
190 /* 0x43100000 */
191
192#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
193#define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
194 | (0x0242 << SDRAM_MODE_SD_SHIFT))
195 /* ODT 150ohm CL=4, AL=0 on SDRAM */
196#define CONFIG_SYS_DDR_MODE2 0x00000000
197
198/*
199 * Memory test
200 */
201#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
202#define CONFIG_SYS_MEMTEST_END 0x07f00000
203
204/*
205 * The reserved memory
206 */
207#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
208
209#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
210#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
211
212/*
213 * Initial RAM Base Address Setup
214 */
215#define CONFIG_SYS_INIT_RAM_LOCK 1
216#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
217#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
218#define CONFIG_SYS_GBL_DATA_OFFSET \
219 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
220
221/*
222 * Local Bus Configuration & Clock Setup
223 */
224#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
225#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
226#define CONFIG_SYS_LBC_LBCR 0x00040000
227
228/*
229 * FLASH on the Local Bus
230 */
231#if 1
232#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
233#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
234#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
235#define CONFIG_FLASH_CFI_LEGACY
236#define CONFIG_SYS_FLASH_LEGACY_512Kx16
237#else
238#define CONFIG_SYS_NO_FLASH
239#endif
240
241#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
242#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
243#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
244
245/* Window base at flash base */
246#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
247#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
248
249#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
250 | BR_PS_16 /* 16 bit port */ \
251 | BR_MS_GPCM /* MSEL = GPCM */ \
252 | BR_V) /* valid */
253#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
254 | OR_UPM_XAM \
255 | OR_GPCM_CSNT \
256 | OR_GPCM_ACS_DIV2 \
257 | OR_GPCM_XACS \
258 | OR_GPCM_SCY_15 \
259 | OR_GPCM_TRLX_SET \
260 | OR_GPCM_EHTR_SET)
261
262#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
263#define CONFIG_SYS_MAX_FLASH_SECT 135
264
265#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
266#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
267
268/*
269 * FPGA
270 */
271#define CONFIG_SYS_FPGA0_BASE 0xE0600000
272#define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */
273
274/* Window base at FPGA base */
275#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE
276#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB)
277
278#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \
279 | BR_PS_16 /* 16 bit port */ \
280 | BR_MS_GPCM /* MSEL = GPCM */ \
281 | BR_V) /* valid */
282#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
283 | OR_UPM_XAM \
284 | OR_GPCM_CSNT \
285 | OR_GPCM_ACS_DIV2 \
286 | OR_GPCM_XACS \
287 | OR_GPCM_SCY_15 \
288 | OR_GPCM_TRLX_SET \
289 | OR_GPCM_EHTR_SET)
290
291#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
292#define CONFIG_SYS_FPGA_DONE(k) 0x0010
293
294#define CONFIG_SYS_FPGA_COUNT 1
295
296#define CONFIG_SYS_MCLINK_MAX 3
297
298#define CONFIG_SYS_FPGA_PTR \
299 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
300
301#define CONFIG_SYS_FPGA_NO_RFL_HI
302
303/*
304 * Serial Port
305 */
306#define CONFIG_CONS_INDEX 2
Dirk Eibacha3f9d6c2015-10-28 11:46:32 +0100307#define CONFIG_SYS_NS16550_SERIAL
308#define CONFIG_SYS_NS16550_REG_SIZE 1
309#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
310
311#define CONFIG_SYS_BAUDRATE_TABLE \
312 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
313
314#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
315#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
316
317/* Use the HUSH parser */
318#define CONFIG_SYS_HUSH_PARSER
319
320/* Pass open firmware flat tree */
Dirk Eibacha3f9d6c2015-10-28 11:46:32 +0100321
322/* I2C */
323#define CONFIG_SYS_I2C
324#define CONFIG_SYS_I2C_FSL
325#define CONFIG_SYS_FSL_I2C_SPEED 400000
326#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
327#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
328
329#define CONFIG_PCA953X /* NXP PCA9554 */
Dirk Eibach47098052016-03-16 09:20:12 +0100330#define CONFIG_CMD_PCA953X
331#define CONFIG_CMD_PCA953X_INFO
332#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x24, 16}, {0x25, 16}, {0x26, 16}, \
333 {0x3c, 8}, {0x3d, 8}, {0x3e, 8} }
334
Dirk Eibacha3f9d6c2015-10-28 11:46:32 +0100335#define CONFIG_PCA9698 /* NXP PCA9698 */
336
337#define CONFIG_SYS_I2C_IHS
338#define CONFIG_SYS_I2C_IHS_CH0
339#define CONFIG_SYS_I2C_IHS_SPEED_0 50000
340#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
341#define CONFIG_SYS_I2C_IHS_CH1
342#define CONFIG_SYS_I2C_IHS_SPEED_1 50000
343#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
344#define CONFIG_SYS_I2C_IHS_CH2
345#define CONFIG_SYS_I2C_IHS_SPEED_2 50000
346#define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
347#define CONFIG_SYS_I2C_IHS_CH3
348#define CONFIG_SYS_I2C_IHS_SPEED_3 50000
349#define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
350
351/*
352 * Software (bit-bang) I2C driver configuration
353 */
354#define CONFIG_SYS_I2C_SOFT
355#define CONFIG_SOFT_I2C_READ_REPEATED_START
356#define CONFIG_SYS_I2C_SOFT_SPEED 50000
357#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
358#define I2C_SOFT_DECLARATIONS2
359#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
360#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
361#define I2C_SOFT_DECLARATIONS3
362#define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
363#define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
364#define I2C_SOFT_DECLARATIONS4
365#define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
366#define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
367#ifdef CONFIG_STRIDER_CON
368#define I2C_SOFT_DECLARATIONS5
369#define CONFIG_SYS_I2C_SOFT_SPEED_5 50000
370#define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F
371#define I2C_SOFT_DECLARATIONS6
372#define CONFIG_SYS_I2C_SOFT_SPEED_6 50000
373#define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F
374#define I2C_SOFT_DECLARATIONS7
375#define CONFIG_SYS_I2C_SOFT_SPEED_7 50000
376#define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F
377#define I2C_SOFT_DECLARATIONS8
378#define CONFIG_SYS_I2C_SOFT_SPEED_8 50000
379#define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F
380#endif
381
382#ifdef CONFIG_STRIDER_CON
383#define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8}
384#define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8}
385#define CONFIG_SYS_ADV7611_I2C {5, 6, 7, 8}
386#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
387#define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \
388 {12, 0x4c} }
389#else
390#define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4}
391#define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4}
392#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
393#define CONFIG_STRIDER_FANS { {2, 0x18}, {3, 0x18}, \
394 {4, 0x18} }
395#endif
396
397#ifndef __ASSEMBLY__
398void fpga_gpio_set(unsigned int bus, int pin);
399void fpga_gpio_clear(unsigned int bus, int pin);
400int fpga_gpio_get(unsigned int bus, int pin);
401#endif
402
403#ifdef CONFIG_STRIDER_CON
404#define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0200 : 0x0040)
405#define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020)
406#define I2C_FPGA_IDX ((I2C_ADAP_HWNR > 3) ? \
407 (I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR)
408#else
409#define I2C_SDA_GPIO 0x0040
410#define I2C_SCL_GPIO 0x0020
411#define I2C_FPGA_IDX I2C_ADAP_HWNR
412#endif
413#define I2C_ACTIVE { }
414#define I2C_TRISTATE { }
415#define I2C_READ \
416 (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
417#define I2C_SDA(bit) \
418 do { \
419 if (bit) \
420 fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
421 else \
422 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
423 } while (0)
424#define I2C_SCL(bit) \
425 do { \
426 if (bit) \
427 fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
428 else \
429 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
430 } while (0)
431#define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
432
433/*
434 * Software (bit-bang) MII driver configuration
435 */
436#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
437#define CONFIG_BITBANGMII_MULTI
438
439/*
440 * OSD Setup
441 */
442#define CONFIG_SYS_OSD_SCREENS 1
443#define CONFIG_SYS_DP501_DIFFERENTIAL
444#define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
445
446/*
447 * General PCI
448 * Addresses are mapped 1-1.
449 */
450#define CONFIG_SYS_PCIE1_BASE 0xA0000000
451#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
452#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
453#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
454#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
455#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
456#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
457#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
458#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
459
460/* enable PCIE clock */
461#define CONFIG_SYS_SCCR_PCIEXP1CM 1
462
463#define CONFIG_PCI
464#define CONFIG_PCI_INDIRECT_BRIDGE
465#define CONFIG_PCIE
466
467#define CONFIG_PCI_PNP /* do pci plug-and-play */
468
469#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
470#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
471
472/*
473 * TSEC
474 */
475#define CONFIG_TSEC_ENET /* TSEC ethernet support */
476#define CONFIG_SYS_TSEC1_OFFSET 0x24000
477#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
478
479/*
480 * TSEC ethernet configuration
481 */
482#define CONFIG_MII 1 /* MII PHY management */
483#define CONFIG_TSEC1
484#define CONFIG_TSEC1_NAME "eTSEC0"
485#define TSEC1_PHY_ADDR 1
486#define TSEC1_PHYIDX 0
487#define TSEC1_FLAGS 0
488
489/* Options are: eTSEC[0-1] */
490#define CONFIG_ETHPRIME "eTSEC0"
491
492/*
493 * Environment
494 */
495#if 1
496#define CONFIG_ENV_IS_IN_FLASH 1
497#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
498 CONFIG_SYS_MONITOR_LEN)
499#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
500#define CONFIG_ENV_SIZE 0x2000
501#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
502#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
503#else
504#define CONFIG_ENV_IS_NOWHERE
505#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
506#endif
507
508#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
509#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
510
511/*
512 * Command line configuration.
513 */
514#define CONFIG_CMD_I2C
515#define CONFIG_CMD_MII
516#define CONFIG_CMD_PCI
517#define CONFIG_CMD_PING
518
519#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
520#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
521
522/*
523 * Miscellaneous configurable options
524 */
525#define CONFIG_SYS_LONGHELP /* undef to save memory */
526#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
527#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
528
529#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
530
531#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
532
533#define CONFIG_SYS_CONSOLE_INFO_QUIET
534
535/* Print Buffer Size */
536#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
537#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
538#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
539
540/*
541 * For booting Linux, the board info and command line data
542 * have to be in the first 256 MB of memory, since this is
543 * the maximum mapped by the Linux kernel during initialization.
544 */
545#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
546
547/*
548 * Core HID Setup
549 */
550#define CONFIG_SYS_HID0_INIT 0x000000000
551#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
552 HID0_ENABLE_INSTRUCTION_CACHE | \
553 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
554#define CONFIG_SYS_HID2 HID2_HBE
555
556/*
557 * MMU Setup
558 */
559
560/* DDR: cache cacheable */
561#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
562 BATL_MEMCOHERENCE)
563#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
564 BATU_VS | BATU_VP)
565#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
566#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
567
568/* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */
569#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
570 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
571#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
572 BATU_VP)
573#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
574#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
575
576/* FLASH: icache cacheable, but dcache-inhibit and guarded */
577#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
578 BATL_MEMCOHERENCE)
579#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
580 BATU_VS | BATU_VP)
581#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
582 BATL_CACHEINHIBIT | \
583 BATL_GUARDEDSTORAGE)
584#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
585
586/* Stack in dcache: cacheable, no memory coherence */
587#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
588#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
589 BATU_VS | BATU_VP)
590#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
591#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
592
593/*
594 * Environment Configuration
595 */
596
597#define CONFIG_ENV_OVERWRITE
598
599#if defined(CONFIG_TSEC_ENET)
600#define CONFIG_HAS_ETH0
601#endif
602
603#define CONFIG_BAUDRATE 115200
604
605#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
606
607#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
608
609#define CONFIG_HOSTNAME hrcon
610#define CONFIG_ROOTPATH "/opt/nfsroot"
611#define CONFIG_BOOTFILE "uImage"
612
613#define CONFIG_PREBOOT /* enable preboot variable */
614
615#define CONFIG_EXTRA_ENV_SETTINGS \
616 "netdev=eth0\0" \
617 "consoledev=ttyS1\0" \
618 "u-boot=u-boot.bin\0" \
619 "kernel_addr=1000000\0" \
620 "fdt_addr=C00000\0" \
621 "fdtfile=hrcon.dtb\0" \
622 "load=tftp ${loadaddr} ${u-boot}\0" \
623 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
624 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
625 " +${filesize};cp.b ${fileaddr} " \
626 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
627 "upd=run load update\0" \
628
629#define CONFIG_NFSBOOTCOMMAND \
630 "setenv bootargs root=/dev/nfs rw " \
631 "nfsroot=$serverip:$rootpath " \
632 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
633 "console=$consoledev,$baudrate $othbootargs;" \
634 "tftp ${kernel_addr} $bootfile;" \
635 "tftp ${fdt_addr} $fdtfile;" \
636 "bootm ${kernel_addr} - ${fdt_addr}"
637
638#define CONFIG_MMCBOOTCOMMAND \
639 "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
640 "console=$consoledev,$baudrate $othbootargs;" \
641 "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \
642 "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \
643 "bootm ${kernel_addr} - ${fdt_addr}"
644
645#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
646
647
648#endif /* __CONFIG_H */