| Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Ash Charles | ffe1691 | 2014-05-14 08:34:34 -0700 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2012 |
| 4 | * Gumstix Incorporated, <www.gumstix.com> |
| 5 | * Maintainer: Ash Charles <ash@gumstix.com> |
| Ash Charles | ffe1691 | 2014-05-14 08:34:34 -0700 | [diff] [blame] | 6 | */ |
| 7 | #ifndef _DUOVERO_MUX_DATA_H_ |
| 8 | #define _DUOVERO_MUX_DATA_H_ |
| 9 | |
| 10 | #include <asm/arch/mux_omap4.h> |
| 11 | |
| 12 | const struct pad_conf_entry core_padconf_array_essential[] = { |
| 13 | {SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */ |
| 14 | {SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */ |
| 15 | {SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */ |
| 16 | {SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */ |
| 17 | {SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */ |
| 18 | {SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */ |
| 19 | {I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */ |
| 20 | {I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */ |
| 21 | {I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */ |
| 22 | {I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */ |
| 23 | {I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */ |
| 24 | {I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */ |
| 25 | {I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */ |
| 26 | {I2C4_SDA, (PTU | IEN | M0)}, /* i2c4_sda */ |
| 27 | {UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */ |
| 28 | {UART3_RTS_SD, (M0)}, /* uart3_rts_sd */ |
| 29 | {UART3_RX_IRRX, (PTU | IEN | M0)}, /* uart3_rx */ |
| 30 | {UART3_TX_IRTX, (M0)} /* uart3_tx */ |
| 31 | }; |
| 32 | |
| 33 | const struct pad_conf_entry wkup_padconf_array_essential[] = { |
| 34 | {PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */ |
| 35 | {PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */ |
| 36 | {PAD1_SYS_32K, (IEN | M0)} /* sys_32k */ |
| 37 | }; |
| 38 | |
| 39 | const struct pad_conf_entry core_padconf_array_non_essential[] = { |
| 40 | {GPMC_AD0, (PTU | IEN | M0)}, /* gpmc_ad0 */ |
| 41 | {GPMC_AD1, (PTU | IEN | M0)}, /* gpmc_ad1 */ |
| 42 | {GPMC_AD2, (PTU | IEN | M0)}, /* gpmc_ad2 */ |
| 43 | {GPMC_AD3, (PTU | IEN | M0)}, /* gpmc_ad3 */ |
| 44 | {GPMC_AD4, (PTU | IEN | M0)}, /* gpmc_ad4 */ |
| 45 | {GPMC_AD5, (PTU | IEN | M0)}, /* gpmc_ad5 */ |
| 46 | {GPMC_AD6, (PTU | IEN | M0)}, /* gpmc_ad6 */ |
| 47 | {GPMC_AD7, (PTU | IEN | M0)}, /* gpmc_ad7 */ |
| 48 | {GPMC_AD8, (PTU | IEN | M0)}, /* gpmc_ad8 */ |
| 49 | {GPMC_AD9, (PTU | IEN | M0)}, /* gpmc_ad9 */ |
| 50 | {GPMC_AD10, (PTU | IEN | M0)}, /* gpmc_ad10 */ |
| 51 | {GPMC_AD11, (PTU | IEN | M0)}, /* gpmc_ad11 */ |
| 52 | {GPMC_AD12, (PTU | IEN | M0)}, /* gpmc_ad12 */ |
| 53 | {GPMC_AD13, (PTU | IEN | M0)}, /* gpmc_ad13 */ |
| 54 | {GPMC_AD14, (PTU | IEN | M0)}, /* gpmc_ad14 */ |
| 55 | {GPMC_AD15, (PTU | IEN | M0)}, /* gpmc_ad15 */ |
| 56 | {GPMC_A16, (PTU | IEN | M3)}, /* gpio_40 */ |
| 57 | {GPMC_A17, (PTU | IEN | M3)}, /* gpio_41 - hdmi_ls_oe */ |
| 58 | {GPMC_A18, (PTU | IEN | M3)}, /* gpio_42 */ |
| 59 | {GPMC_A19, (PTU | IEN | M3)}, /* gpio_43 - wifi_en */ |
| 60 | {GPMC_A20, (PTU | IEN | M3)}, /* gpio_44 - eth_irq */ |
| 61 | {GPMC_A21, (PTU | IEN | M3)}, /* gpio_45 - eth_nreset */ |
| 62 | {GPMC_A22, (PTU | IEN | M3)}, /* gpio_46 - eth_pme */ |
| 63 | {GPMC_A23, (PTU | IEN | M3)}, /* gpio_47 */ |
| 64 | {GPMC_A24, (PTU | IEN | M3)}, /* gpio_48 - eth_mdix */ |
| 65 | {GPMC_A25, (PTU | IEN | M3)}, /* gpio_49 - bt_wakeup */ |
| 66 | {GPMC_NCS0, (PTU | M0)}, /* gpmc_ncs0 */ |
| 67 | {GPMC_NCS1, (PTU | M0)}, /* gpmc_ncs1 */ |
| 68 | {GPMC_NCS2, (PTU | M0)}, /* gpmc_ncs2 */ |
| 69 | {GPMC_NCS3, (PTU | IEN | M3)}, /* gpio_53 */ |
| 70 | {C2C_DATA12, (PTU | M0)}, /* gpmc_ncs4 */ |
| 71 | {C2C_DATA13, (PTU | M0)}, /* gpmc_ncs5 - eth_cs */ |
| 72 | {GPMC_NWP, (PTU | IEN | M0)}, /* gpmc_nwp */ |
| 73 | {GPMC_CLK, (PTU | IEN | M0)}, /* gpmc_clk */ |
| 74 | {GPMC_NADV_ALE, (PTU | M0)}, /* gpmc_nadv_ale */ |
| 75 | {GPMC_NBE0_CLE, (PTU | M0)}, /* gpmc_nbe0_cle */ |
| 76 | {GPMC_NBE1, (PTU | M0)}, /* gpmc_nbe1 */ |
| 77 | {GPMC_WAIT0, (PTU | IEN | M0)}, /* gpmc_wait0 */ |
| 78 | {GPMC_WAIT1, (PTU | IEN | M0)}, /* gpio_62 - usbh_nreset */ |
| 79 | {GPMC_NOE, (PTU | M0)}, /* gpmc_noe */ |
| 80 | {GPMC_NWE, (PTU | M0)}, /* gpmc_nwe */ |
| 81 | {HDMI_HPD, (PTD | IEN | M3)}, /* gpio_63 - hdmi_hpd */ |
| 82 | {HDMI_CEC, (PTU | IEN | M0)}, /* hdmi_cec */ |
| 83 | {HDMI_DDC_SCL, (M0)}, /* hdmi_ddc_scl */ |
| 84 | {HDMI_DDC_SDA, (IEN | M0)}, /* hdmi_ddc_sda */ |
| 85 | {CSI21_DX0, (IEN | M0)}, /* csi21_dx0 */ |
| 86 | {CSI21_DY0, (IEN | M0)}, /* csi21_dy0 */ |
| 87 | {CSI21_DX1, (IEN | M0)}, /* csi21_dx1 */ |
| 88 | {CSI21_DY1, (IEN | M0)}, /* csi21_dy1 */ |
| 89 | {CSI21_DX2, (IEN | M0)}, /* csi21_dx2 */ |
| 90 | {CSI21_DY2, (IEN | M0)}, /* csi21_dy2 */ |
| 91 | {CSI21_DX3, (IEN | M0)}, /* csi21_dx3 */ |
| 92 | {CSI21_DY3, (IEN | M0)}, /* csi21_dy3 */ |
| 93 | {CSI21_DX4, (IEN | M0)}, /* csi21_dx4 */ |
| 94 | {CSI21_DY4, (IEN | M0)}, /* csi21_dy4 */ |
| 95 | {CSI22_DX0, (IEN | M0)}, /* csi22_dx0 */ |
| 96 | {CSI22_DY0, (IEN | M0)}, /* csi22_dy0 */ |
| 97 | {CSI22_DX1, (IEN | M0)}, /* csi22_dx1 */ |
| 98 | {CSI22_DY1, (IEN | M0)}, /* csi22_dy1 */ |
| 99 | {USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */ |
| 100 | {USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)}, /* usbb1_ulpiphy_stp */ |
| 101 | {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dir */ |
| 102 | {USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_nxt */ |
| 103 | {USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat0 */ |
| 104 | {USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat1 */ |
| 105 | {USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat2 */ |
| 106 | {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat3 */ |
| 107 | {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */ |
| 108 | {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */ |
| 109 | {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */ |
| 110 | {USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */ |
| 111 | {USBB1_HSIC_DATA, (PTU | IEN | M3)}, /* gpio_96 - usbh_cpen */ |
| 112 | {USBB1_HSIC_STROBE, (PTU | IEN | M3)}, /* gpio_97 - usbh_reset */ |
| 113 | {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */ |
| 114 | {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ |
| 115 | {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ |
| 116 | {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */ |
| 117 | {ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */ |
| 118 | {ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_dl_data */ |
| 119 | {ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_frame */ |
| 120 | {ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_lb_clk */ |
| 121 | {ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_clks */ |
| 122 | {ABE_DMIC_CLK1, (M0)}, /* abe_dmic_clk1 */ |
| 123 | {ABE_DMIC_DIN1, (IEN | M0)}, /* abe_dmic_din1 */ |
| 124 | {ABE_DMIC_DIN2, (IEN | M0)}, /* abe_dmic_din2 */ |
| 125 | {ABE_DMIC_DIN3, (IEN | M0)}, /* abe_dmic_din3 */ |
| 126 | {UART2_CTS, (PTU | IEN | M0)}, /* uart2_cts */ |
| 127 | {UART2_RTS, (M0)}, /* uart2_rts */ |
| 128 | {UART2_RX, (PTU | IEN | M0)}, /* uart2_rx */ |
| 129 | {UART2_TX, (M0)}, /* uart2_tx */ |
| 130 | {HDQ_SIO, (M0)}, /* hdq-sio */ |
| 131 | {MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */ |
| 132 | {MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */ |
| 133 | {MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */ |
| 134 | {MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs0 */ |
| 135 | {MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs1 */ |
| 136 | {SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_clk */ |
| 137 | {SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */ |
| 138 | {SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */ |
| 139 | {SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */ |
| 140 | {SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */ |
| 141 | {SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */ |
| 142 | {MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_clk */ |
| 143 | {MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_simo */ |
| 144 | {MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_somi */ |
| 145 | {MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */ |
| 146 | {UART4_RX, (IEN | PTU | M0)}, /* uart4_rx */ |
| 147 | {UART4_TX, (M0)}, /* uart4_tx */ |
| 148 | {USBB2_ULPITLL_CLK, (PTU | IEN | M3)}, /* gpio_157 - start_adc */ |
| 149 | {USBB2_ULPITLL_STP, (PTU | IEN | M3)}, /* gpio_158 - spi_nirq */ |
| 150 | {USBB2_ULPITLL_DIR, (PTU | IEN | M3)}, /* gpio_159 - bt_nreset */ |
| 151 | {USBB2_ULPITLL_NXT, (PTU | IEN | M3)}, /* gpio_160 - audio_pwron*/ |
| 152 | {USBB2_ULPITLL_DAT0, (PTU | IEN | M3)}, /* gpio_161 - bid_0 */ |
| 153 | {USBB2_ULPITLL_DAT1, (PTU | IEN | M3)}, /* gpio_162 - bid_1 */ |
| 154 | {USBB2_ULPITLL_DAT2, (PTU | IEN | M3)}, /* gpio_163 - bid_2 */ |
| 155 | {USBB2_ULPITLL_DAT3, (PTU | IEN | M3)}, /* gpio_164 - bid_3 */ |
| 156 | {USBB2_ULPITLL_DAT4, (PTU | IEN | M3)}, /* gpio_165 - bid_4 */ |
| 157 | {USBB2_ULPITLL_DAT5, (PTU | IEN | M3)}, /* gpio_166 - ts_irq*/ |
| 158 | {USBB2_ULPITLL_DAT6, (PTU | IEN | M3)}, /* gpio_167 - gps_pps */ |
| 159 | {USBB2_ULPITLL_DAT7, (PTU | IEN | M3)}, /* gpio_168 */ |
| 160 | {USBB2_HSIC_DATA, (PTU | IEN | M3)}, /* gpio_169 */ |
| 161 | {USBB2_HSIC_STROBE, (PTU | IEN | M3)}, /* gpio_170 */ |
| 162 | {UNIPRO_TX1, (PTU | IEN | M3)}, /* gpio_173 */ |
| 163 | {USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */ |
| 164 | {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ |
| 165 | {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ |
| 166 | {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ |
| 167 | {SYS_NIRQ2, (PTU | IEN | M0)}, /* sys_nirq2 */ |
| 168 | {SYS_BOOT0, (M0)}, /* sys_boot0 */ |
| 169 | {SYS_BOOT1, (M0)}, /* sys_boot1 */ |
| 170 | {SYS_BOOT2, (M0)}, /* sys_boot2 */ |
| 171 | {SYS_BOOT3, (M0)}, /* sys_boot3 */ |
| 172 | {SYS_BOOT4, (M0)}, /* sys_boot4 */ |
| 173 | {SYS_BOOT5, (M0)}, /* sys_boot5 */ |
| 174 | {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ |
| 175 | {DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */ |
| 176 | {DPM_EMU16, (PTU | IEN | M3)}, /* gpio_27 */ |
| 177 | {DPM_EMU17, (PTU | IEN | M3)}, /* gpio_28 */ |
| 178 | {DPM_EMU18, (PTU | IEN | M3)}, /* gpio_29 */ |
| 179 | {DPM_EMU19, (PTU | IEN | M3)}, /* gpio_30 */ |
| 180 | }; |
| 181 | |
| 182 | const struct pad_conf_entry wkup_padconf_array_non_essential[] = { |
| 183 | {PAD1_FREF_XTAL_IN, (M0)}, /* fref_xtal_in */ |
| 184 | {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ |
| 185 | {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ |
| 186 | {PAD0_FREF_CLK0_OUT, (M7)}, /* safe mode */ |
| 187 | {PAD1_FREF_CLK3_REQ, M7}, /* safe mode */ |
| 188 | {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ |
| 189 | {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ |
| 190 | {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ |
| 191 | {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ |
| 192 | {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ |
| 193 | {PAD0_SYS_BOOT6, (M0)}, /* sys_boot6 */ |
| 194 | {PAD1_SYS_BOOT7, (M0)}, /* sys_boot7 */ |
| 195 | }; |
| 196 | |
| 197 | |
| 198 | #endif /* _DUOVERO_MUX_DATA_H_ */ |