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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk3d3befa2004-03-14 15:06:13 +00002/*
3 * (C) Copyright 2000
4 * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
5 *
6 * (C) Copyright 2004
7 * ARM Ltd.
8 * Philippe Robin, <philippe.robin@arm.com>
wdenk3d3befa2004-03-14 15:06:13 +00009 */
10
Andreas Engel48d01922008-09-08 14:30:53 +020011/* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */
wdenk3d3befa2004-03-14 15:06:13 +000012
13#include <common.h>
Simon Glass8a9cd5a2014-09-22 17:30:58 -060014#include <dm.h>
Simon Glassaed2fbe2014-09-22 17:30:57 -060015#include <errno.h>
Stuart Wood8b616ed2008-06-02 16:42:19 -040016#include <watchdog.h>
Matt Waddel249d5212010-10-07 15:48:46 -060017#include <asm/io.h>
Marek Vasut39f61472012-09-14 22:38:46 +020018#include <serial.h>
Masahiro Yamada86256b72014-10-24 12:41:19 +090019#include <dm/platform_data/serial_pl01x.h>
Marek Vasut39f61472012-09-14 22:38:46 +020020#include <linux/compiler.h>
Simon Glassaed2fbe2014-09-22 17:30:57 -060021#include "serial_pl01x_internal.h"
Vikas Manocha69751722015-05-06 11:46:29 -070022
23DECLARE_GLOBAL_DATA_PTR;
wdenk3d3befa2004-03-14 15:06:13 +000024
Simon Glass8a9cd5a2014-09-22 17:30:58 -060025#ifndef CONFIG_DM_SERIAL
26
wdenk6705d812004-08-02 23:22:59 +000027static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS;
Simon Glassaed2fbe2014-09-22 17:30:57 -060028static enum pl01x_type pl01x_type __attribute__ ((section(".data")));
29static struct pl01x_regs *base_regs __attribute__ ((section(".data")));
wdenk6705d812004-08-02 23:22:59 +000030#define NUM_PORTS (sizeof(port)/sizeof(port[0]))
wdenk3d3befa2004-03-14 15:06:13 +000031
Simon Glass8a9cd5a2014-09-22 17:30:58 -060032#endif
wdenk3d3befa2004-03-14 15:06:13 +000033
Simon Glassaed2fbe2014-09-22 17:30:57 -060034static int pl01x_putc(struct pl01x_regs *regs, char c)
Rabin Vincent72d5e442010-05-05 09:23:07 +053035{
wdenk42dfe7a2004-03-14 22:25:36 +000036 /* Wait until there is space in the FIFO */
Simon Glassaed2fbe2014-09-22 17:30:57 -060037 if (readl(&regs->fr) & UART_PL01x_FR_TXFF)
38 return -EAGAIN;
wdenk42dfe7a2004-03-14 22:25:36 +000039
40 /* Send the character */
Rabin Vincent72d5e442010-05-05 09:23:07 +053041 writel(c, &regs->dr);
Simon Glassaed2fbe2014-09-22 17:30:57 -060042
43 return 0;
wdenk3d3befa2004-03-14 15:06:13 +000044}
45
Simon Glassaed2fbe2014-09-22 17:30:57 -060046static int pl01x_getc(struct pl01x_regs *regs)
wdenk3d3befa2004-03-14 15:06:13 +000047{
wdenk42dfe7a2004-03-14 22:25:36 +000048 unsigned int data;
wdenk3d3befa2004-03-14 15:06:13 +000049
wdenk42dfe7a2004-03-14 22:25:36 +000050 /* Wait until there is data in the FIFO */
Simon Glassaed2fbe2014-09-22 17:30:57 -060051 if (readl(&regs->fr) & UART_PL01x_FR_RXFE)
52 return -EAGAIN;
wdenk42dfe7a2004-03-14 22:25:36 +000053
Rabin Vincent72d5e442010-05-05 09:23:07 +053054 data = readl(&regs->dr);
wdenk42dfe7a2004-03-14 22:25:36 +000055
56 /* Check for an error flag */
57 if (data & 0xFFFFFF00) {
58 /* Clear the error */
Rabin Vincent72d5e442010-05-05 09:23:07 +053059 writel(0xFFFFFFFF, &regs->ecr);
wdenk42dfe7a2004-03-14 22:25:36 +000060 return -1;
61 }
62
63 return (int) data;
wdenk3d3befa2004-03-14 15:06:13 +000064}
65
Simon Glassaed2fbe2014-09-22 17:30:57 -060066static int pl01x_tstc(struct pl01x_regs *regs)
wdenk3d3befa2004-03-14 15:06:13 +000067{
Stuart Wood8b616ed2008-06-02 16:42:19 -040068 WATCHDOG_RESET();
Rabin Vincent72d5e442010-05-05 09:23:07 +053069 return !(readl(&regs->fr) & UART_PL01x_FR_RXFE);
wdenk3d3befa2004-03-14 15:06:13 +000070}
Marek Vasut39f61472012-09-14 22:38:46 +020071
Simon Glassaed2fbe2014-09-22 17:30:57 -060072static int pl01x_generic_serial_init(struct pl01x_regs *regs,
73 enum pl01x_type type)
74{
Simon Glassaed2fbe2014-09-22 17:30:57 -060075 switch (type) {
76 case TYPE_PL010:
Vikas Manochaf7e517b2014-11-21 10:34:22 -080077 /* disable everything */
78 writel(0, &regs->pl010_cr);
Simon Glassaed2fbe2014-09-22 17:30:57 -060079 break;
Vikas Manochad2ca9fd2014-11-21 10:34:21 -080080 case TYPE_PL011:
Vikas Manochaf7e517b2014-11-21 10:34:22 -080081 /* disable everything */
82 writel(0, &regs->pl011_cr);
Vikas Manochad2ca9fd2014-11-21 10:34:21 -080083 break;
84 default:
85 return -EINVAL;
86 }
87
88 return 0;
89}
90
Linus Walleijd77447f2015-04-21 15:10:06 +020091static int pl011_set_line_control(struct pl01x_regs *regs)
Vikas Manochad2ca9fd2014-11-21 10:34:21 -080092{
93 unsigned int lcr;
94 /*
95 * Internal update of baud rate register require line
96 * control register write
97 */
98 lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
Vikas Manochad2ca9fd2014-11-21 10:34:21 -080099 writel(lcr, &regs->pl011_lcrh);
Simon Glassaed2fbe2014-09-22 17:30:57 -0600100 return 0;
101}
102
103static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
104 int clock, int baudrate)
105{
106 switch (type) {
107 case TYPE_PL010: {
108 unsigned int divisor;
109
Linus Walleijd77447f2015-04-21 15:10:06 +0200110 /* disable everything */
111 writel(0, &regs->pl010_cr);
112
Simon Glassaed2fbe2014-09-22 17:30:57 -0600113 switch (baudrate) {
114 case 9600:
115 divisor = UART_PL010_BAUD_9600;
116 break;
117 case 19200:
Alyssa Rosenzweigb2aa8892017-04-07 09:48:22 -0700118 divisor = UART_PL010_BAUD_19200;
Simon Glassaed2fbe2014-09-22 17:30:57 -0600119 break;
120 case 38400:
121 divisor = UART_PL010_BAUD_38400;
122 break;
123 case 57600:
124 divisor = UART_PL010_BAUD_57600;
125 break;
126 case 115200:
127 divisor = UART_PL010_BAUD_115200;
128 break;
129 default:
130 divisor = UART_PL010_BAUD_38400;
131 }
132
133 writel((divisor & 0xf00) >> 8, &regs->pl010_lcrm);
134 writel(divisor & 0xff, &regs->pl010_lcrl);
135
Linus Walleijd77447f2015-04-21 15:10:06 +0200136 /*
137 * Set line control for the PL010 to be 8 bits, 1 stop bit,
138 * no parity, fifo enabled
139 */
140 writel(UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN,
141 &regs->pl010_lcrh);
Simon Glassaed2fbe2014-09-22 17:30:57 -0600142 /* Finally, enable the UART */
143 writel(UART_PL010_CR_UARTEN, &regs->pl010_cr);
144 break;
145 }
146 case TYPE_PL011: {
147 unsigned int temp;
148 unsigned int divider;
149 unsigned int remainder;
150 unsigned int fraction;
151
152 /*
153 * Set baud rate
154 *
155 * IBRD = UART_CLK / (16 * BAUD_RATE)
156 * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE)))
157 * / (16 * BAUD_RATE))
158 */
159 temp = 16 * baudrate;
160 divider = clock / temp;
161 remainder = clock % temp;
162 temp = (8 * remainder) / baudrate;
163 fraction = (temp >> 1) + (temp & 1);
164
165 writel(divider, &regs->pl011_ibrd);
166 writel(fraction, &regs->pl011_fbrd);
167
Linus Walleijd77447f2015-04-21 15:10:06 +0200168 pl011_set_line_control(regs);
Simon Glassaed2fbe2014-09-22 17:30:57 -0600169 /* Finally, enable the UART */
170 writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE |
171 UART_PL011_CR_RXE | UART_PL011_CR_RTS, &regs->pl011_cr);
172 break;
173 }
174 default:
175 return -EINVAL;
176 }
177
178 return 0;
179}
180
181#ifndef CONFIG_DM_SERIAL
182static void pl01x_serial_init_baud(int baudrate)
183{
184 int clock = 0;
185
186#if defined(CONFIG_PL010_SERIAL)
187 pl01x_type = TYPE_PL010;
188#elif defined(CONFIG_PL011_SERIAL)
189 pl01x_type = TYPE_PL011;
190 clock = CONFIG_PL011_CLOCK;
191#endif
192 base_regs = (struct pl01x_regs *)port[CONFIG_CONS_INDEX];
193
194 pl01x_generic_serial_init(base_regs, pl01x_type);
Vikas Manochaa7deea62014-11-21 10:34:19 -0800195 pl01x_generic_setbrg(base_regs, pl01x_type, clock, baudrate);
Simon Glassaed2fbe2014-09-22 17:30:57 -0600196}
197
198/*
199 * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
200 * Integrator CP has two UARTs, use the first one, at 38400-8-N-1
201 * Versatile PB has four UARTs.
202 */
203int pl01x_serial_init(void)
204{
205 pl01x_serial_init_baud(CONFIG_BAUDRATE);
206
207 return 0;
208}
209
210static void pl01x_serial_putc(const char c)
211{
212 if (c == '\n')
213 while (pl01x_putc(base_regs, '\r') == -EAGAIN);
214
215 while (pl01x_putc(base_regs, c) == -EAGAIN);
216}
217
218static int pl01x_serial_getc(void)
219{
220 while (1) {
221 int ch = pl01x_getc(base_regs);
222
223 if (ch == -EAGAIN) {
224 WATCHDOG_RESET();
225 continue;
226 }
227
228 return ch;
229 }
230}
231
232static int pl01x_serial_tstc(void)
233{
234 return pl01x_tstc(base_regs);
235}
236
237static void pl01x_serial_setbrg(void)
238{
239 /*
240 * Flush FIFO and wait for non-busy before changing baudrate to avoid
241 * crap in console
242 */
243 while (!(readl(&base_regs->fr) & UART_PL01x_FR_TXFE))
244 WATCHDOG_RESET();
245 while (readl(&base_regs->fr) & UART_PL01x_FR_BUSY)
246 WATCHDOG_RESET();
247 pl01x_serial_init_baud(gd->baudrate);
248}
249
Marek Vasut39f61472012-09-14 22:38:46 +0200250static struct serial_device pl01x_serial_drv = {
251 .name = "pl01x_serial",
252 .start = pl01x_serial_init,
253 .stop = NULL,
254 .setbrg = pl01x_serial_setbrg,
255 .putc = pl01x_serial_putc,
Marek Vasutec3fd682012-10-06 14:07:02 +0000256 .puts = default_serial_puts,
Marek Vasut39f61472012-09-14 22:38:46 +0200257 .getc = pl01x_serial_getc,
258 .tstc = pl01x_serial_tstc,
259};
260
261void pl01x_serial_initialize(void)
262{
263 serial_register(&pl01x_serial_drv);
264}
265
266__weak struct serial_device *default_serial_console(void)
267{
268 return &pl01x_serial_drv;
269}
Simon Glassaed2fbe2014-09-22 17:30:57 -0600270
271#endif /* nCONFIG_DM_SERIAL */
Simon Glass8a9cd5a2014-09-22 17:30:58 -0600272
273#ifdef CONFIG_DM_SERIAL
274
Alexander Grafc9bf43d2018-03-07 22:08:25 +0100275int pl01x_serial_setbrg(struct udevice *dev, int baudrate)
Simon Glass8a9cd5a2014-09-22 17:30:58 -0600276{
277 struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
278 struct pl01x_priv *priv = dev_get_priv(dev);
279
Eric Anholtcd0fa5b2016-03-13 18:16:54 -0700280 if (!plat->skip_init) {
281 pl01x_generic_setbrg(priv->regs, priv->type, plat->clock,
282 baudrate);
283 }
Simon Glass8a9cd5a2014-09-22 17:30:58 -0600284
285 return 0;
286}
287
Alexander Graf60019852018-01-25 12:05:55 +0100288int pl01x_serial_probe(struct udevice *dev)
Simon Glass8a9cd5a2014-09-22 17:30:58 -0600289{
290 struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
291 struct pl01x_priv *priv = dev_get_priv(dev);
292
293 priv->regs = (struct pl01x_regs *)plat->base;
294 priv->type = plat->type;
Eric Anholtcd0fa5b2016-03-13 18:16:54 -0700295 if (!plat->skip_init)
296 return pl01x_generic_serial_init(priv->regs, priv->type);
297 else
298 return 0;
Simon Glass8a9cd5a2014-09-22 17:30:58 -0600299}
300
Alexander Grafc9bf43d2018-03-07 22:08:25 +0100301int pl01x_serial_getc(struct udevice *dev)
Simon Glass8a9cd5a2014-09-22 17:30:58 -0600302{
303 struct pl01x_priv *priv = dev_get_priv(dev);
304
305 return pl01x_getc(priv->regs);
306}
307
Alexander Grafc9bf43d2018-03-07 22:08:25 +0100308int pl01x_serial_putc(struct udevice *dev, const char ch)
Simon Glass8a9cd5a2014-09-22 17:30:58 -0600309{
310 struct pl01x_priv *priv = dev_get_priv(dev);
311
312 return pl01x_putc(priv->regs, ch);
313}
314
Alexander Grafc9bf43d2018-03-07 22:08:25 +0100315int pl01x_serial_pending(struct udevice *dev, bool input)
Simon Glass8a9cd5a2014-09-22 17:30:58 -0600316{
317 struct pl01x_priv *priv = dev_get_priv(dev);
318 unsigned int fr = readl(&priv->regs->fr);
319
320 if (input)
321 return pl01x_tstc(priv->regs);
322 else
323 return fr & UART_PL01x_FR_TXFF ? 0 : 1;
324}
325
Alexander Grafc9bf43d2018-03-07 22:08:25 +0100326static const struct dm_serial_ops pl01x_serial_ops = {
Simon Glass8a9cd5a2014-09-22 17:30:58 -0600327 .putc = pl01x_serial_putc,
328 .pending = pl01x_serial_pending,
329 .getc = pl01x_serial_getc,
330 .setbrg = pl01x_serial_setbrg,
331};
332
Masahiro Yamada0f925822015-08-12 07:31:55 +0900333#if CONFIG_IS_ENABLED(OF_CONTROL)
Vikas Manocha69751722015-05-06 11:46:29 -0700334static const struct udevice_id pl01x_serial_id[] ={
335 {.compatible = "arm,pl011", .data = TYPE_PL011},
336 {.compatible = "arm,pl010", .data = TYPE_PL010},
337 {}
338};
339
Alexander Graf60019852018-01-25 12:05:55 +0100340int pl01x_serial_ofdata_to_platdata(struct udevice *dev)
Vikas Manocha69751722015-05-06 11:46:29 -0700341{
342 struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
343 fdt_addr_t addr;
344
Simon Glassa821c4a2017-05-17 17:18:05 -0600345 addr = devfdt_get_addr(dev);
Vikas Manocha69751722015-05-06 11:46:29 -0700346 if (addr == FDT_ADDR_T_NONE)
347 return -EINVAL;
348
349 plat->base = addr;
Alexander Grafb3111632018-01-25 12:05:49 +0100350 plat->clock = dev_read_u32_default(dev, "clock", 1);
Vikas Manocha69751722015-05-06 11:46:29 -0700351 plat->type = dev_get_driver_data(dev);
Alexander Grafb3111632018-01-25 12:05:49 +0100352 plat->skip_init = dev_read_bool(dev, "skip-init");
353
Vikas Manocha69751722015-05-06 11:46:29 -0700354 return 0;
355}
356#endif
357
Simon Glass8a9cd5a2014-09-22 17:30:58 -0600358U_BOOT_DRIVER(serial_pl01x) = {
359 .name = "serial_pl01x",
360 .id = UCLASS_SERIAL,
Vikas Manocha69751722015-05-06 11:46:29 -0700361 .of_match = of_match_ptr(pl01x_serial_id),
362 .ofdata_to_platdata = of_match_ptr(pl01x_serial_ofdata_to_platdata),
363 .platdata_auto_alloc_size = sizeof(struct pl01x_serial_platdata),
Simon Glass8a9cd5a2014-09-22 17:30:58 -0600364 .probe = pl01x_serial_probe,
365 .ops = &pl01x_serial_ops,
Bin Meng46879192018-10-24 06:36:36 -0700366#if !CONFIG_IS_ENABLED(OF_CONTROL)
Simon Glass8a9cd5a2014-09-22 17:30:58 -0600367 .flags = DM_FLAG_PRE_RELOC,
Bin Meng46879192018-10-24 06:36:36 -0700368#endif
Simon Glass59c73d72014-11-24 21:36:35 -0700369 .priv_auto_alloc_size = sizeof(struct pl01x_priv),
Simon Glass8a9cd5a2014-09-22 17:30:58 -0600370};
371
372#endif
Sergey Temerkhanovb81406d2015-10-14 09:54:23 -0700373
374#if defined(CONFIG_DEBUG_UART_PL010) || defined(CONFIG_DEBUG_UART_PL011)
375
376#include <debug_uart.h>
377
378static void _debug_uart_init(void)
379{
380#ifndef CONFIG_DEBUG_UART_SKIP_INIT
381 struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE;
382 enum pl01x_type type = CONFIG_IS_ENABLED(DEBUG_UART_PL011) ?
383 TYPE_PL011 : TYPE_PL010;
384
385 pl01x_generic_serial_init(regs, type);
386 pl01x_generic_setbrg(regs, type,
387 CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
388#endif
389}
390
391static inline void _debug_uart_putc(int ch)
392{
393 struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE;
394
395 pl01x_putc(regs, ch);
396}
397
398DEBUG_UART_FUNCS
399
400#endif