Rafal Jaworowski | 6902df5 | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2005 |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | * |
| 23 | */ |
| 24 | |
| 25 | #include <asm/mmu.h> |
| 26 | #include <common.h> |
Wolfgang Denk | 4681e67 | 2009-05-14 23:18:34 +0200 | [diff] [blame^] | 27 | #include <asm/global_data.h> |
Rafal Jaworowski | 6902df5 | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 28 | #include <pci.h> |
Wolfgang Denk | 4681e67 | 2009-05-14 23:18:34 +0200 | [diff] [blame^] | 29 | #include <asm/mpc8349_pci.h> |
| 30 | #if defined(CONFIG_OF_LIBFDT) |
| 31 | #include <libfdt.h> |
| 32 | #include <fdt_support.h> |
| 33 | #endif |
| 34 | |
| 35 | DECLARE_GLOBAL_DATA_PTR; |
Rafal Jaworowski | 6902df5 | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 36 | |
| 37 | #ifdef CONFIG_PCI |
| 38 | |
| 39 | /* System RAM mapped to PCI space */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 40 | #define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE |
| 41 | #define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE |
Rafal Jaworowski | 6902df5 | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 42 | #define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) |
| 43 | |
| 44 | #ifndef CONFIG_PCI_PNP |
| 45 | static struct pci_config_table pci_tqm834x_config_table[] = { |
| 46 | {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, |
| 47 | PCI_IDSEL_NUMBER, PCI_ANY_ID, |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 48 | pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, |
Rafal Jaworowski | 6902df5 | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 49 | PCI_ENET0_MEMADDR, |
| 50 | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
| 51 | } |
| 52 | }, |
| 53 | {} |
| 54 | }; |
| 55 | #endif |
| 56 | |
| 57 | static struct pci_controller pci1_hose = { |
| 58 | #ifndef CONFIG_PCI_PNP |
| 59 | config_table:pci_tqm834x_config_table, |
| 60 | #endif |
| 61 | }; |
| 62 | |
| 63 | |
| 64 | /************************************************************************** |
| 65 | * pci_init_board() |
| 66 | * |
| 67 | * NOTICE: MPC8349 internally has two PCI controllers (PCI1 and PCI2) but since |
| 68 | * per TQM834x design physical connections to external devices (PCI sockets) |
| 69 | * are routed only to the PCI1 we do not account for the second one - this code |
| 70 | * supports PCI1 module only. Should support for the PCI2 be required in the |
| 71 | * future it needs a separate pci_controller structure (above) and handling - |
| 72 | * please refer to other boards' implementation for dual PCI host controllers, |
| 73 | * for example board/Marvell/db64360/pci.c, pci_init_board() |
| 74 | * |
| 75 | */ |
| 76 | void |
| 77 | pci_init_board(void) |
| 78 | { |
| 79 | volatile immap_t * immr; |
Tanya Jiang | 2fc34ae | 2006-08-03 18:38:13 +0800 | [diff] [blame] | 80 | volatile clk83xx_t * clk; |
| 81 | volatile law83xx_t * pci_law; |
| 82 | volatile pot83xx_t * pci_pot; |
| 83 | volatile pcictrl83xx_t * pci_ctrl; |
| 84 | volatile pciconf83xx_t * pci_conf; |
Rafal Jaworowski | 6902df5 | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 85 | u16 reg16; |
| 86 | u32 reg32; |
| 87 | struct pci_controller * hose; |
| 88 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 89 | immr = (immap_t *)CONFIG_SYS_IMMR; |
Tanya Jiang | 2fc34ae | 2006-08-03 18:38:13 +0800 | [diff] [blame] | 90 | clk = (clk83xx_t *)&immr->clk; |
Rafal Jaworowski | 6902df5 | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 91 | pci_law = immr->sysconf.pcilaw; |
| 92 | pci_pot = immr->ios.pot; |
| 93 | pci_ctrl = immr->pci_ctrl; |
| 94 | pci_conf = immr->pci_conf; |
| 95 | |
| 96 | hose = &pci1_hose; |
Wolfgang Denk | f013dac | 2005-12-04 00:40:34 +0100 | [diff] [blame] | 97 | |
Rafal Jaworowski | 6902df5 | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 98 | /* |
Wolfgang Denk | f013dac | 2005-12-04 00:40:34 +0100 | [diff] [blame] | 99 | * Configure PCI controller and PCI_CLK_OUTPUT |
Rafal Jaworowski | 6902df5 | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 100 | */ |
| 101 | |
| 102 | /* |
| 103 | * WARNING! only PCI_CLK_OUTPUT1 is enabled here as this is the one |
| 104 | * line actually used for clocking all external PCI devices in TQM83xx. |
Wolfgang Denk | f013dac | 2005-12-04 00:40:34 +0100 | [diff] [blame] | 105 | * Enabling other PCI_CLK_OUTPUT lines may lead to board's hang for |
Rafal Jaworowski | 6902df5 | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 106 | * unknown reasons - particularly PCI_CLK_OUTPUT6 and PCI_CLK_OUTPUT7 |
Wolfgang Denk | f013dac | 2005-12-04 00:40:34 +0100 | [diff] [blame] | 107 | * are known to hang the board; this issue is under investigation |
Rafal Jaworowski | 6902df5 | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 108 | * (13 oct 05) |
| 109 | */ |
| 110 | reg32 = OCCR_PCICOE1; |
Wolfgang Denk | f013dac | 2005-12-04 00:40:34 +0100 | [diff] [blame] | 111 | #if 0 |
Rafal Jaworowski | 6902df5 | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 112 | /* enabling all PCI_CLK_OUTPUT lines HANGS the board... */ |
| 113 | reg32 = 0xff000000; |
Wolfgang Denk | f013dac | 2005-12-04 00:40:34 +0100 | [diff] [blame] | 114 | #endif |
Rafal Jaworowski | 6902df5 | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 115 | if (clk->spmr & SPMR_CKID) { |
| 116 | /* PCI Clock is half CONFIG_83XX_CLKIN so need to set up OCCR |
| 117 | * fields accordingly */ |
| 118 | reg32 |= (OCCR_PCI1CR | OCCR_PCI2CR); |
Wolfgang Denk | f013dac | 2005-12-04 00:40:34 +0100 | [diff] [blame] | 119 | |
Rafal Jaworowski | 6902df5 | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 120 | reg32 |= (OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 \ |
| 121 | | OCCR_PCICD3 | OCCR_PCICD4 | OCCR_PCICD5 \ |
| 122 | | OCCR_PCICD6 | OCCR_PCICD7); |
| 123 | } |
| 124 | |
| 125 | clk->occr = reg32; |
| 126 | udelay(2000); |
| 127 | |
| 128 | /* |
| 129 | * Release PCI RST Output signal |
| 130 | */ |
| 131 | pci_ctrl[0].gcr = 0; |
| 132 | udelay(2000); |
| 133 | pci_ctrl[0].gcr = 1; |
| 134 | udelay(2000); |
| 135 | |
| 136 | /* |
| 137 | * Configure PCI Local Access Windows |
| 138 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 139 | pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; |
Rafal Jaworowski | 5a164c8 | 2005-11-17 00:26:18 +0100 | [diff] [blame] | 140 | pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; |
Rafal Jaworowski | 6902df5 | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 141 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 142 | pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; |
Rafal Jaworowski | 5a164c8 | 2005-11-17 00:26:18 +0100 | [diff] [blame] | 143 | pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M; |
Rafal Jaworowski | 6902df5 | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 144 | |
| 145 | /* |
| 146 | * Configure PCI Outbound Translation Windows |
| 147 | */ |
| 148 | |
Wolfgang Denk | f013dac | 2005-12-04 00:40:34 +0100 | [diff] [blame] | 149 | /* PCI1 mem space */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 150 | pci_pot[0].potar = (CONFIG_SYS_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; |
| 151 | pci_pot[0].pobar = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; |
Rafal Jaworowski | 6902df5 | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 152 | pci_pot[0].pocmr = POCMR_EN | (POCMR_CM_512M & POCMR_CM_MASK); |
| 153 | |
| 154 | /* PCI1 IO space */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 155 | pci_pot[1].potar = (CONFIG_SYS_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; |
| 156 | pci_pot[1].pobar = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; |
Rafal Jaworowski | 6902df5 | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 157 | pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK); |
| 158 | |
| 159 | /* |
| 160 | * Configure PCI Inbound Translation Windows |
| 161 | */ |
| 162 | |
Wolfgang Denk | f013dac | 2005-12-04 00:40:34 +0100 | [diff] [blame] | 163 | /* we need RAM mapped to PCI space for the devices to |
| 164 | * access main memory */ |
Rafal Jaworowski | 6902df5 | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 165 | pci_ctrl[0].pitar1 = 0x0; |
| 166 | pci_ctrl[0].pibar1 = 0x0; |
| 167 | pci_ctrl[0].piebar1 = 0x0; |
Rafal Jaworowski | 5a164c8 | 2005-11-17 00:26:18 +0100 | [diff] [blame] | 168 | pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_256M; |
Rafal Jaworowski | 6902df5 | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 169 | |
| 170 | hose->first_busno = 0; |
| 171 | hose->last_busno = 0xff; |
| 172 | |
| 173 | /* PCI memory space */ |
| 174 | pci_set_region(hose->regions + 0, |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 175 | CONFIG_SYS_PCI1_MEM_BASE, |
| 176 | CONFIG_SYS_PCI1_MEM_PHYS, |
| 177 | CONFIG_SYS_PCI1_MEM_SIZE, |
Rafal Jaworowski | 6902df5 | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 178 | PCI_REGION_MEM); |
| 179 | |
| 180 | /* PCI IO space */ |
| 181 | pci_set_region(hose->regions + 1, |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 182 | CONFIG_SYS_PCI1_IO_BASE, |
| 183 | CONFIG_SYS_PCI1_IO_PHYS, |
| 184 | CONFIG_SYS_PCI1_IO_SIZE, |
Rafal Jaworowski | 6902df5 | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 185 | PCI_REGION_IO); |
| 186 | |
| 187 | /* System memory space */ |
| 188 | pci_set_region(hose->regions + 2, |
| 189 | CONFIG_PCI_SYS_MEM_BUS, |
Wolfgang Denk | f013dac | 2005-12-04 00:40:34 +0100 | [diff] [blame] | 190 | CONFIG_PCI_SYS_MEM_PHYS, |
| 191 | CONFIG_PCI_SYS_MEM_SIZE, |
Kumar Gala | ff4e66e | 2009-02-06 09:49:31 -0600 | [diff] [blame] | 192 | PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); |
Wolfgang Denk | f013dac | 2005-12-04 00:40:34 +0100 | [diff] [blame] | 193 | |
Rafal Jaworowski | 6902df5 | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 194 | hose->region_count = 3; |
| 195 | |
| 196 | pci_setup_indirect(hose, |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 197 | (CONFIG_SYS_IMMR+0x8300), |
| 198 | (CONFIG_SYS_IMMR+0x8304)); |
Rafal Jaworowski | 6902df5 | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 199 | |
| 200 | pci_register_hose(hose); |
| 201 | |
| 202 | /* |
| 203 | * Write to Command register |
| 204 | */ |
| 205 | reg16 = 0xff; |
Wolfgang Denk | f013dac | 2005-12-04 00:40:34 +0100 | [diff] [blame] | 206 | pci_hose_read_config_word (hose, PCI_BDF(0,0,0), PCI_COMMAND, |
Rafal Jaworowski | 6902df5 | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 207 | ®16); |
| 208 | reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; |
Wolfgang Denk | f013dac | 2005-12-04 00:40:34 +0100 | [diff] [blame] | 209 | pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_COMMAND, |
Rafal Jaworowski | 6902df5 | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 210 | reg16); |
| 211 | |
| 212 | /* |
| 213 | * Clear non-reserved bits in status register. |
| 214 | */ |
Wolfgang Denk | f013dac | 2005-12-04 00:40:34 +0100 | [diff] [blame] | 215 | pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_STATUS, |
Rafal Jaworowski | 6902df5 | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 216 | 0xffff); |
Wolfgang Denk | f013dac | 2005-12-04 00:40:34 +0100 | [diff] [blame] | 217 | pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_LATENCY_TIMER, |
Rafal Jaworowski | 6902df5 | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 218 | 0x80); |
| 219 | |
| 220 | #ifdef CONFIG_PCI_SCAN_SHOW |
| 221 | printf("PCI: Bus Dev VenId DevId Class Int\n"); |
| 222 | #endif |
| 223 | /* |
| 224 | * Hose scan. |
| 225 | */ |
| 226 | hose->last_busno = pci_hose_scan(hose); |
| 227 | } |
Wolfgang Denk | 4681e67 | 2009-05-14 23:18:34 +0200 | [diff] [blame^] | 228 | |
| 229 | #if defined(CONFIG_OF_LIBFDT) |
| 230 | void ft_pci_setup(void *blob, bd_t *bd) |
| 231 | { |
| 232 | int nodeoffset; |
| 233 | int tmp[2]; |
| 234 | const char *path; |
| 235 | |
| 236 | nodeoffset = fdt_path_offset(blob, "/aliases"); |
| 237 | if (nodeoffset >= 0) { |
| 238 | path = fdt_getprop(blob, nodeoffset, "pci0", NULL); |
| 239 | if (path) { |
| 240 | tmp[0] = cpu_to_be32(pci1_hose.first_busno); |
| 241 | tmp[1] = cpu_to_be32(pci1_hose.last_busno); |
| 242 | do_fixup_by_path(blob, path, "bus-range", |
| 243 | &tmp, sizeof(tmp), 1); |
| 244 | |
| 245 | tmp[0] = cpu_to_be32(gd->pci_clk); |
| 246 | do_fixup_by_path(blob, path, "clock-frequency", |
| 247 | &tmp, sizeof(tmp[0]), 1); |
| 248 | } |
| 249 | #ifdef CONFIG_MPC83XX_PCI2 |
| 250 | path = fdt_getprop(blob, nodeoffset, "pci1", NULL); |
| 251 | if (path) { |
| 252 | tmp[0] = cpu_to_be32(pci2_hose.first_busno); |
| 253 | tmp[1] = cpu_to_be32(pci2_hose.last_busno); |
| 254 | do_fixup_by_path(blob, path, "bus-range", |
| 255 | &tmp, sizeof(tmp), 1); |
| 256 | |
| 257 | tmp[0] = cpu_to_be32(gd->pci_clk); |
| 258 | do_fixup_by_path(blob, path, "clock-frequency", |
| 259 | &tmp, sizeof(tmp[0]), 1); |
| 260 | } |
| 261 | #endif |
| 262 | } |
| 263 | } |
| 264 | #endif /* CONFIG_OF_LIBFDT */ |
Rafal Jaworowski | 6902df5 | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 265 | #endif /* CONFIG_PCI */ |