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wdenkc6097192002-11-03 00:24:07 +00001/*
stroesea20b27a2004-12-16 18:05:42 +00002 * (C) Copyright 2001-2004
wdenkc6097192002-11-03 00:24:07 +00003 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_405GP 1 /* This is a PPC405 CPU */
wdenkc837dcb2004-01-20 23:12:12 +000037#define CONFIG_4xx 1 /* ...member of PPC4xx family */
wdenkc6097192002-11-03 00:24:07 +000038#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
wdenkc837dcb2004-01-20 23:12:12 +000039#define CONFIG_CPCI405_VER2 1 /* ...version 2 */
Matthias Fuchs6f35c532007-06-24 17:41:21 +020040#undef CONFIG_CPCI405_6U /* enable this for 6U boards */
wdenkc6097192002-11-03 00:24:07 +000041
wdenkc837dcb2004-01-20 23:12:12 +000042#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
wdenkc6097192002-11-03 00:24:07 +000043
stroesea20b27a2004-12-16 18:05:42 +000044#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
wdenkc6097192002-11-03 00:24:07 +000045
46#define CONFIG_BAUDRATE 9600
47#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
48
wdenkc6097192002-11-03 00:24:07 +000049#undef CONFIG_BOOTARGS
stroesea20b27a2004-12-16 18:05:42 +000050#undef CONFIG_BOOTCOMMAND
51
52#define CONFIG_PREBOOT /* enable preboot variable */
wdenkc6097192002-11-03 00:24:07 +000053
54#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
55#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
56
57#define CONFIG_MII 1 /* MII PHY management */
wdenkc837dcb2004-01-20 23:12:12 +000058#define CONFIG_PHY_ADDR 0 /* PHY address */
stroesea20b27a2004-12-16 18:05:42 +000059#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
Matthias Fuchs6f35c532007-06-24 17:41:21 +020060#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
61
62#define CONFIG_NET_MULTI 1
63#undef CONFIG_HAS_ETH1
wdenkc6097192002-11-03 00:24:07 +000064
65#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
66
wdenkc837dcb2004-01-20 23:12:12 +000067#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
stroesefe389a82003-08-28 14:17:32 +000068 CONFIG_BOOTP_DNS | \
69 CONFIG_BOOTP_DNS2 | \
70 CONFIG_BOOTP_SEND_HOSTNAME )
stroese9919f132003-05-23 11:38:22 +000071
wdenkc6097192002-11-03 00:24:07 +000072#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
stroese9919f132003-05-23 11:38:22 +000073 CFG_CMD_DHCP | \
wdenkc6097192002-11-03 00:24:07 +000074 CFG_CMD_PCI | \
75 CFG_CMD_IRQ | \
76 CFG_CMD_IDE | \
stroesea20b27a2004-12-16 18:05:42 +000077 CFG_CMD_FAT | \
wdenkc6097192002-11-03 00:24:07 +000078 CFG_CMD_ELF | \
79 CFG_CMD_DATE | \
80 CFG_CMD_JFFS2 | \
81 CFG_CMD_I2C | \
stroesead10dd92003-02-14 11:21:23 +000082 CFG_CMD_MII | \
stroesea0e135b2003-06-24 14:30:28 +000083 CFG_CMD_PING | \
stroesea20b27a2004-12-16 18:05:42 +000084 CFG_CMD_BSP | \
wdenkc837dcb2004-01-20 23:12:12 +000085 CFG_CMD_EEPROM )
wdenkc6097192002-11-03 00:24:07 +000086
stroesea20b27a2004-12-16 18:05:42 +000087#if 0 /* test-only */
88#define CONFIG_NETCONSOLE
89#define CONFIG_NET_MULTI
90
91#ifdef CONFIG_NET_MULTI
92#define CONFIG_PHY1_ADDR 1 /* PHY address: for NetConsole */
93#endif
94#endif
95
wdenkc6097192002-11-03 00:24:07 +000096#define CONFIG_MAC_PARTITION
97#define CONFIG_DOS_PARTITION
98
stroesea20b27a2004-12-16 18:05:42 +000099#define CONFIG_SUPPORT_VFAT
100
101#if 0 /* test-only */
102#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */
103#endif
104
wdenkc6097192002-11-03 00:24:07 +0000105/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
106#include <cmd_confdefs.h>
107
Bartlomiej Siekaaddb2e12006-03-05 18:57:33 +0100108#define CFG_NAND_LEGACY
109
wdenkc837dcb2004-01-20 23:12:12 +0000110#undef CONFIG_WATCHDOG /* watchdog disabled */
wdenkc6097192002-11-03 00:24:07 +0000111
wdenkc837dcb2004-01-20 23:12:12 +0000112#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
wdenkc6097192002-11-03 00:24:07 +0000113
114/*
115 * Miscellaneous configurable options
116 */
117#define CFG_LONGHELP /* undef to save memory */
118#define CFG_PROMPT "=> " /* Monitor Command Prompt */
119
120#undef CFG_HUSH_PARSER /* use "hush" command parser */
121#ifdef CFG_HUSH_PARSER
wdenkc837dcb2004-01-20 23:12:12 +0000122#define CFG_PROMPT_HUSH_PS2 "> "
wdenkc6097192002-11-03 00:24:07 +0000123#endif
124
125#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
wdenkc837dcb2004-01-20 23:12:12 +0000126#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000127#else
wdenkc837dcb2004-01-20 23:12:12 +0000128#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000129#endif
130#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
131#define CFG_MAXARGS 16 /* max number of command args */
132#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
133
wdenkc837dcb2004-01-20 23:12:12 +0000134#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
wdenkc6097192002-11-03 00:24:07 +0000135
wdenkc837dcb2004-01-20 23:12:12 +0000136#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
wdenkc6097192002-11-03 00:24:07 +0000137
stroesea20b27a2004-12-16 18:05:42 +0000138#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
139
wdenkc6097192002-11-03 00:24:07 +0000140#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
141#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
142
wdenkc837dcb2004-01-20 23:12:12 +0000143#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
144#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
145#define CFG_BASE_BAUD 691200
wdenkc6097192002-11-03 00:24:07 +0000146
147/* The following table includes the supported baudrates */
wdenkc837dcb2004-01-20 23:12:12 +0000148#define CFG_BAUDRATE_TABLE \
wdenk8bde7f72003-06-27 21:31:46 +0000149 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
150 57600, 115200, 230400, 460800, 921600 }
wdenkc6097192002-11-03 00:24:07 +0000151
152#define CFG_LOAD_ADDR 0x100000 /* default load address */
153#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
154
wdenkc837dcb2004-01-20 23:12:12 +0000155#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkc6097192002-11-03 00:24:07 +0000156
stroesea20b27a2004-12-16 18:05:42 +0000157#define CONFIG_LOOPW 1 /* enable loopw command */
158
wdenkc6097192002-11-03 00:24:07 +0000159#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
160
wdenkc837dcb2004-01-20 23:12:12 +0000161#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
stroese9e7d5eb2003-04-04 16:48:07 +0000162
wdenkc837dcb2004-01-20 23:12:12 +0000163#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
stroese53cf9432003-06-05 15:39:44 +0000164
wdenkc6097192002-11-03 00:24:07 +0000165/*-----------------------------------------------------------------------
166 * PCI stuff
167 *-----------------------------------------------------------------------
168 */
stroesea20b27a2004-12-16 18:05:42 +0000169#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
170#define PCI_HOST_FORCE 1 /* configure as pci host */
171#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
wdenkc6097192002-11-03 00:24:07 +0000172
stroesea20b27a2004-12-16 18:05:42 +0000173#define CONFIG_PCI /* include pci support */
174#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
175#define CONFIG_PCI_PNP /* do pci plug-and-play */
176 /* resource configuration */
wdenkc6097192002-11-03 00:24:07 +0000177
stroesea20b27a2004-12-16 18:05:42 +0000178#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
wdenkc6097192002-11-03 00:24:07 +0000179
stroesea20b27a2004-12-16 18:05:42 +0000180#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
stroesead10dd92003-02-14 11:21:23 +0000181
stroesea20b27a2004-12-16 18:05:42 +0000182#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
183
184#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
185#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
186#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
187#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
Stefan Roese2076d0a2006-01-18 20:03:15 +0100188#define CFG_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
189#define CFG_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
stroesea20b27a2004-12-16 18:05:42 +0000190#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
191#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
192#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
193#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
wdenkc6097192002-11-03 00:24:07 +0000194
195/*-----------------------------------------------------------------------
196 * IDE/ATA stuff
197 *-----------------------------------------------------------------------
198 */
wdenkc837dcb2004-01-20 23:12:12 +0000199#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
200#undef CONFIG_IDE_LED /* no led for ide supported */
wdenkc6097192002-11-03 00:24:07 +0000201#define CONFIG_IDE_RESET 1 /* reset for ide supported */
202
wdenkc837dcb2004-01-20 23:12:12 +0000203#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
204#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
wdenkc6097192002-11-03 00:24:07 +0000205
wdenkc837dcb2004-01-20 23:12:12 +0000206#define CFG_ATA_BASE_ADDR 0xF0100000
207#define CFG_ATA_IDE0_OFFSET 0x0000
wdenkc6097192002-11-03 00:24:07 +0000208
209#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
wdenkc837dcb2004-01-20 23:12:12 +0000210#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
wdenkc6097192002-11-03 00:24:07 +0000211#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
212
213/*-----------------------------------------------------------------------
214 * Start addresses for the final memory configuration
215 * (Set up by the startup code)
216 * Please note that CFG_SDRAM_BASE _must_ start at 0
217 */
218#define CFG_SDRAM_BASE 0x00000000
219#define CFG_FLASH_BASE 0xFFFC0000
220#define CFG_MONITOR_BASE CFG_FLASH_BASE
221#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
222#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
223
224/*
225 * For booting Linux, the board info and command line data
226 * have to be in the first 8 MB of memory, since this is
227 * the maximum mapped by the Linux kernel during initialization.
228 */
229#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
230/*-----------------------------------------------------------------------
231 * FLASH organization
232 */
233#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
234#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
235
236#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
237#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
238
wdenkc837dcb2004-01-20 23:12:12 +0000239#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
240#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
241#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
wdenkc6097192002-11-03 00:24:07 +0000242/*
243 * The following defines are added for buggy IOP480 byte interface.
244 * All other boards should use the standard values (CPCI405 etc.)
245 */
wdenkc837dcb2004-01-20 23:12:12 +0000246#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
247#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
248#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
wdenkc6097192002-11-03 00:24:07 +0000249
wdenkc837dcb2004-01-20 23:12:12 +0000250#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
wdenkc6097192002-11-03 00:24:07 +0000251
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200252
253/*
254 * JFFS2 partitions
255 */
256
257/* No command line, one static partition, use whole device */
258#undef CONFIG_JFFS2_CMDLINE
259#define CONFIG_JFFS2_DEV "nor0"
260#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
261#define CONFIG_JFFS2_PART_OFFSET 0x00000000
262
263/* mtdparts command line support */
264
265/* Use first bank for JFFS2, second bank contains U-Boot.
266 *
267 * Note: fake mtd_id's used, no linux mtd map file.
268 */
269/*
270#define CONFIG_JFFS2_CMDLINE
271#define MTDIDS_DEFAULT "nor0=cpci4052-0"
272#define MTDPARTS_DEFAULT "mtdparts=cpci4052-0:-(jffs2)"
273*/
wdenkc6097192002-11-03 00:24:07 +0000274
275#if 0 /* Use NVRAM for environment variables */
276/*-----------------------------------------------------------------------
277 * NVRAM organization
278 */
279#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
280#define CFG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
281#define CFG_ENV_ADDR \
282 (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-(CFG_ENV_SIZE+8)) /* Env */
283
284#else /* Use EEPROM for environment variables */
285
wdenkc837dcb2004-01-20 23:12:12 +0000286#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
287#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
288#define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/
wdenk8bde7f72003-06-27 21:31:46 +0000289 /* total size of a CAT24WC16 is 2048 bytes */
wdenkc6097192002-11-03 00:24:07 +0000290#endif
291
292#define CFG_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
293#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */
stroesea20b27a2004-12-16 18:05:42 +0000294#define CFG_VXWORKS_MAC_PTR (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
wdenkc6097192002-11-03 00:24:07 +0000295
296/*-----------------------------------------------------------------------
297 * I2C EEPROM (CAT24WC16) for environment
298 */
299#define CONFIG_HARD_I2C /* I2c with hardware support */
300#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
301#define CFG_I2C_SLAVE 0x7F
302
303#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
wdenkc837dcb2004-01-20 23:12:12 +0000304#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
305/* mask of address bits that overflow into the "EEPROM chip address" */
wdenkc6097192002-11-03 00:24:07 +0000306#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
307#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
308 /* 16 byte page write mode using*/
wdenkc837dcb2004-01-20 23:12:12 +0000309 /* last 4 bits of the address */
wdenkc6097192002-11-03 00:24:07 +0000310#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
311#define CFG_EEPROM_PAGE_WRITE_ENABLE
312
313/*-----------------------------------------------------------------------
314 * Cache Configuration
315 */
Wolfgang Denk0c8721a2005-09-23 11:05:55 +0200316#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
wdenkc837dcb2004-01-20 23:12:12 +0000317 /* have only 8kB, 16kB is save here */
wdenkc6097192002-11-03 00:24:07 +0000318#define CFG_CACHELINE_SIZE 32 /* ... */
319#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
320#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
321#endif
322
323/*
324 * Init Memory Controller:
325 *
326 * BR0/1 and OR0/1 (FLASH)
327 */
328
329#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
330#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
331
332/*-----------------------------------------------------------------------
333 * External Bus Controller (EBC) Setup
334 */
335
wdenkc837dcb2004-01-20 23:12:12 +0000336/* Memory Bank 0 (Flash Bank 0) initialization */
337#define CFG_EBC_PB0AP 0x92015480
338#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
wdenkc6097192002-11-03 00:24:07 +0000339
wdenkc837dcb2004-01-20 23:12:12 +0000340/* Memory Bank 1 (Flash Bank 1) initialization */
341#define CFG_EBC_PB1AP 0x92015480
342#define CFG_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
wdenkc6097192002-11-03 00:24:07 +0000343
wdenkc837dcb2004-01-20 23:12:12 +0000344/* Memory Bank 2 (CAN0, 1) initialization */
345#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
346#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
347#define CFG_LED_ADDR 0xF0000380
wdenkc6097192002-11-03 00:24:07 +0000348
wdenkc837dcb2004-01-20 23:12:12 +0000349/* Memory Bank 3 (CompactFlash IDE) initialization */
350#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
351#define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
wdenkc6097192002-11-03 00:24:07 +0000352
wdenkc837dcb2004-01-20 23:12:12 +0000353/* Memory Bank 4 (NVRAM/RTC) initialization */
354/*#define CFG_EBC_PB4AP 0x01805280 / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1 */
355#define CFG_EBC_PB4AP 0x01805680 /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1 */
356#define CFG_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
wdenkc6097192002-11-03 00:24:07 +0000357
wdenkc837dcb2004-01-20 23:12:12 +0000358/* Memory Bank 5 (optional Quart) initialization */
359#define CFG_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
360#define CFG_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
wdenkc6097192002-11-03 00:24:07 +0000361
wdenkc837dcb2004-01-20 23:12:12 +0000362/* Memory Bank 6 (FPGA internal) initialization */
363#define CFG_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
364#define CFG_EBC_PB6CR 0xF041A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
365#define CFG_FPGA_BASE_ADDR 0xF0400000
wdenkc6097192002-11-03 00:24:07 +0000366
367/*-----------------------------------------------------------------------
368 * FPGA stuff
369 */
370/* FPGA internal regs */
wdenkc837dcb2004-01-20 23:12:12 +0000371#define CFG_FPGA_MODE 0x00
372#define CFG_FPGA_STATUS 0x02
373#define CFG_FPGA_TS 0x04
374#define CFG_FPGA_TS_LOW 0x06
375#define CFG_FPGA_TS_CAP0 0x10
376#define CFG_FPGA_TS_CAP0_LOW 0x12
377#define CFG_FPGA_TS_CAP1 0x14
378#define CFG_FPGA_TS_CAP1_LOW 0x16
379#define CFG_FPGA_TS_CAP2 0x18
380#define CFG_FPGA_TS_CAP2_LOW 0x1a
381#define CFG_FPGA_TS_CAP3 0x1c
382#define CFG_FPGA_TS_CAP3_LOW 0x1e
wdenkc6097192002-11-03 00:24:07 +0000383
384/* FPGA Mode Reg */
wdenkc837dcb2004-01-20 23:12:12 +0000385#define CFG_FPGA_MODE_CF_RESET 0x0001
stroese6f4474e2003-03-20 15:31:19 +0000386#define CFG_FPGA_MODE_DUART_RESET 0x0002
387#define CFG_FPGA_MODE_ENABLE_OUTPUT 0x0004 /* only set on CPCI-405 Ver 3 */
wdenkc6097192002-11-03 00:24:07 +0000388#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
389#define CFG_FPGA_MODE_TS_IRQ_CLEAR 0x1000
wdenkc837dcb2004-01-20 23:12:12 +0000390#define CFG_FPGA_MODE_TS_CLEAR 0x2000
wdenkc6097192002-11-03 00:24:07 +0000391
392/* FPGA Status Reg */
wdenkc837dcb2004-01-20 23:12:12 +0000393#define CFG_FPGA_STATUS_DIP0 0x0001
394#define CFG_FPGA_STATUS_DIP1 0x0002
395#define CFG_FPGA_STATUS_DIP2 0x0004
396#define CFG_FPGA_STATUS_FLASH 0x0008
397#define CFG_FPGA_STATUS_TS_IRQ 0x1000
wdenkc6097192002-11-03 00:24:07 +0000398
wdenkc837dcb2004-01-20 23:12:12 +0000399#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
400#define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for XC2S15 */
wdenkc6097192002-11-03 00:24:07 +0000401
402/* FPGA program pin configuration */
wdenkc837dcb2004-01-20 23:12:12 +0000403#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
404#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
405#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
406#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
407#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
wdenkc6097192002-11-03 00:24:07 +0000408
409/*-----------------------------------------------------------------------
410 * Definitions for initial stack pointer and data area (in data cache)
411 */
wdenkc837dcb2004-01-20 23:12:12 +0000412#define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
wdenkc6097192002-11-03 00:24:07 +0000413
wdenkc837dcb2004-01-20 23:12:12 +0000414#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */
415#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
wdenkc6097192002-11-03 00:24:07 +0000416#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
417#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
wdenkc837dcb2004-01-20 23:12:12 +0000418#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
wdenkc6097192002-11-03 00:24:07 +0000419
420
421/*
422 * Internal Definitions
423 *
424 * Boot Flags
425 */
426#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
427#define BOOTFLAG_WARM 0x02 /* Software reboot */
428
429#endif /* __CONFIG_H */