| Stefano Babic | 79656d2 | 2012-02-22 00:24:40 +0000 | [diff] [blame] | 1 | # |
| 2 | # (C) Copyright 2012 |
| 3 | # Stefano Babic DENX Software Engineering sbabic@denx.de. |
| 4 | # |
| 5 | # See file CREDITS for list of people who contributed to this |
| 6 | # project. |
| 7 | # |
| 8 | # This program is free software; you can redistribute it and/or |
| 9 | # modify it under the terms of the GNU General Public License as |
| 10 | # published by the Free Software Foundation; either version 2 of |
| 11 | # the License or (at your option) any later version. |
| 12 | # |
| 13 | # This program is distributed in the hope that it will be useful, |
| 14 | # but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | # GNU General Public License for more details. |
| 17 | # |
| 18 | # You should have received a copy of the GNU General Public License |
| 19 | # along with this program; if not write to the Free Software |
| 20 | # Foundation Inc. 51 Franklin Street Fifth Floor Boston, |
| 21 | # MA 02110-1301 USA |
| 22 | # |
| 23 | # Refer docs/README.imxmage for more details about how-to configure |
| 24 | # and create imximage boot image |
| 25 | # |
| 26 | # The syntax is taken as close as possible with the kwbimage |
| 27 | |
| 28 | # image version |
| 29 | |
| 30 | IMAGE_VERSION 2 |
| 31 | |
| 32 | # Boot Device : one of |
| 33 | # spi, sd (the board has no nand neither onenand) |
| 34 | |
| 35 | BOOT_FROM nor |
| 36 | |
| 37 | # Device Configuration Data (DCD) |
| 38 | # |
| 39 | # Each entry must have the format: |
| 40 | # Addr-type Address Value |
| 41 | # |
| 42 | # where: |
| 43 | # Addr-type register length (1,2 or 4 bytes) |
| 44 | # Address absolute address of the register |
| 45 | # value value to be stored in the register |
| 46 | |
| 47 | # IOMUX for RAM only |
| 48 | DATA 4 0x53fa8554 0x300020 |
| 49 | DATA 4 0x53fa8560 0x300020 |
| 50 | DATA 4 0x53fa8594 0x300020 |
| 51 | DATA 4 0x53fa8584 0x300020 |
| 52 | DATA 4 0x53fa8558 0x300040 |
| 53 | DATA 4 0x53fa8568 0x300040 |
| 54 | DATA 4 0x53fa8590 0x300040 |
| 55 | DATA 4 0x53fa857c 0x300040 |
| 56 | DATA 4 0x53fa8564 0x300040 |
| 57 | DATA 4 0x53fa8580 0x300040 |
| 58 | DATA 4 0x53fa8570 0x300220 |
| 59 | DATA 4 0x53fa8578 0x300220 |
| 60 | DATA 4 0x53fa872c 0x300000 |
| 61 | DATA 4 0x53fa8728 0x300000 |
| 62 | DATA 4 0x53fa871c 0x300000 |
| 63 | DATA 4 0x53fa8718 0x300000 |
| 64 | DATA 4 0x53fa8574 0x300020 |
| 65 | DATA 4 0x53fa8588 0x300020 |
| 66 | DATA 4 0x53fa855c 0x0 |
| 67 | DATA 4 0x53fa858c 0x0 |
| 68 | DATA 4 0x53fa856c 0x300040 |
| 69 | DATA 4 0x53fa86f0 0x300000 |
| 70 | DATA 4 0x53fa8720 0x300000 |
| 71 | DATA 4 0x53fa86fc 0x0 |
| 72 | DATA 4 0x53fa86f4 0x0 |
| 73 | DATA 4 0x53fa8714 0x0 |
| 74 | DATA 4 0x53fa8724 0x4000000 |
| 75 | # |
| 76 | # DDR RAM |
| 77 | DATA 4 0x63fd9088 0x40404040 |
| 78 | DATA 4 0x63fd9090 0x40404040 |
| 79 | DATA 4 0x63fd907C 0x01420143 |
| 80 | DATA 4 0x63fd9080 0x01450146 |
| 81 | DATA 4 0x63fd9018 0x00111740 |
| 82 | DATA 4 0x63fd9000 0x84190000 |
| 83 | # esdcfgX |
| 84 | DATA 4 0x63fd900C 0x9f5152e3 |
| 85 | DATA 4 0x63fd9010 0xb68e8a63 |
| 86 | DATA 4 0x63fd9014 0x01ff00db |
| 87 | # Read/Write command delay |
| 88 | DATA 4 0x63fd902c 0x000026d2 |
| 89 | # Out of reset delays |
| 90 | DATA 4 0x63fd9030 0x00ff0e21 |
| 91 | # ESDCTL ODT timing control |
| 92 | DATA 4 0x63fd9008 0x12273030 |
| 93 | # ESDCTL power down control |
| 94 | DATA 4 0x63fd9004 0x0002002d |
| 95 | # Set registers in DDR memory chips |
| 96 | DATA 4 0x63fd901c 0x00008032 |
| 97 | DATA 4 0x63fd901c 0x00008033 |
| 98 | DATA 4 0x63fd901c 0x00028031 |
| 99 | DATA 4 0x63fd901c 0x052080b0 |
| 100 | DATA 4 0x63fd901c 0x04008040 |
| 101 | # ESDCTL refresh control |
| 102 | DATA 4 0x63fd9020 0x00005800 |
| 103 | # PHY ZQ HW control |
| 104 | DATA 4 0x63fd9040 0x05380003 |
| 105 | # PHY ODT control |
| 106 | DATA 4 0x63fd9058 0x00022222 |
| 107 | # start DDR3 |
| 108 | DATA 4 0x63fd901c 0x00000000 |