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Srinath915162d2011-04-18 17:40:35 -04001/*
2 * am3517_crane.h - Default configuration for AM3517 CraneBoard.
3 *
4 * Author: Srinath.R <srinath@mistralsolutions.com>
5 *
6 * Based on include/configs/am3517evm.h
7 *
8 * Copyright (C) 2011 Mistral Solutions pvt Ltd
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25#ifndef __CONFIG_H
26#define __CONFIG_H
27
28/*
29 * High Level Configuration Options
30 */
Srinath915162d2011-04-18 17:40:35 -040031#define CONFIG_OMAP 1 /* in a TI OMAP core */
32#define CONFIG_OMAP34XX 1 /* which is a 34XX */
33#define CONFIG_OMAP3_AM3517CRANE 1 /* working with CRANEBOARD */
34
35#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
36
37#include <asm/arch/cpu.h> /* get chip and board defs */
38#include <asm/arch/omap3.h>
39
40/*
41 * Display CPU and Board information
42 */
43#define CONFIG_DISPLAY_CPUINFO 1
44#define CONFIG_DISPLAY_BOARDINFO 1
45
46/* Clock Defines */
47#define V_OSCK 26000000 /* Clock output from T2 */
48#define V_SCLK (V_OSCK >> 1)
49
50#undef CONFIG_USE_IRQ /* no support for IRQs */
51#define CONFIG_MISC_INIT_R
52
53#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
54#define CONFIG_SETUP_MEMORY_TAGS 1
55#define CONFIG_INITRD_TAG 1
56#define CONFIG_REVISION_TAG 1
57
58/*
59 * Size of malloc() pool
60 */
61#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
62#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
63 /* initial data */
64/*
65 * DDR related
66 */
Srinath915162d2011-04-18 17:40:35 -040067#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
68
69/*
70 * Hardware drivers
71 */
72
73/*
74 * NS16550 Configuration
75 */
76#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
77
78#define CONFIG_SYS_NS16550
79#define CONFIG_SYS_NS16550_SERIAL
80#define CONFIG_SYS_NS16550_REG_SIZE (-4)
81#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
82
83/*
84 * select serial console configuration
85 */
86#define CONFIG_CONS_INDEX 3
87#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
88#define CONFIG_SERIAL3 3 /* UART3 on CRANEBOARD */
89
90/* allow to overwrite serial and ethaddr */
91#define CONFIG_ENV_OVERWRITE
92#define CONFIG_BAUDRATE 115200
93#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
94 115200}
Tom Rinia5a88212011-09-03 21:51:50 -040095#define CONFIG_GENERIC_MMC 1
Srinath915162d2011-04-18 17:40:35 -040096#define CONFIG_MMC 1
Tom Rinia5a88212011-09-03 21:51:50 -040097#define CONFIG_OMAP_HSMMC 1
Srinath915162d2011-04-18 17:40:35 -040098#define CONFIG_DOS_PARTITION 1
99
100/*
101 * USB configuration
102 * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
103 * Enable CONFIG_MUSB_UDC for Device functionalities.
104 */
105#define CONFIG_USB_AM35X 1
106#define CONFIG_MUSB_HCD 1
107
108#ifdef CONFIG_USB_AM35X
109
110#ifdef CONFIG_MUSB_HCD
111#define CONFIG_CMD_USB
112
113#define CONFIG_USB_STORAGE
114#define CONGIG_CMD_STORAGE
115#define CONFIG_CMD_FAT
116
117#ifdef CONFIG_USB_KEYBOARD
118#define CONFIG_SYS_USB_EVENT_POLL
119#define CONFIG_PREBOOT "usb start"
120#endif /* CONFIG_USB_KEYBOARD */
121
122#endif /* CONFIG_MUSB_HCD */
123
124#ifdef CONFIG_MUSB_UDC
125/* USB device configuration */
126#define CONFIG_USB_DEVICE 1
127#define CONFIG_USB_TTY 1
128#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
129/* Change these to suit your needs */
130#define CONFIG_USBD_VENDORID 0x0451
131#define CONFIG_USBD_PRODUCTID 0x5678
132#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
133#define CONFIG_USBD_PRODUCT_NAME "AM3517CRANE"
134#endif /* CONFIG_MUSB_UDC */
135
136#endif /* CONFIG_USB_AM35X */
137
138/* commands to include */
139#include <config_cmd_default.h>
140
141#define CONFIG_CMD_EXT2 /* EXT2 Support */
142#define CONFIG_CMD_FAT /* FAT support */
143#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
144
145#define CONFIG_CMD_I2C /* I2C serial bus support */
146#define CONFIG_CMD_MMC /* MMC support */
147#define CONFIG_CMD_NAND /* NAND support */
148#define CONFIG_CMD_DHCP
149#define CONFIG_CMD_PING
150
151#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
152#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
153#undef CONFIG_CMD_IMI /* iminfo */
154#undef CONFIG_CMD_IMLS /* List all found images */
155
156#define CONFIG_SYS_NO_FLASH
157#define CONFIG_HARD_I2C 1
158#define CONFIG_SYS_I2C_SPEED 100000
159#define CONFIG_SYS_I2C_SLAVE 1
160#define CONFIG_SYS_I2C_BUS 0
161#define CONFIG_SYS_I2C_BUS_SELECT 1
162#define CONFIG_DRIVER_OMAP34XX_I2C 1
163
164#undef CONFIG_CMD_NET
165#undef CONFIG_CMD_NFS
166/*
167 * Board NAND Info.
168 */
169#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
170 /* to access nand */
171#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
172 /* to access */
173 /* nand at CS0 */
174
175#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
176 /* NAND devices */
177#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
178
179#define CONFIG_JFFS2_NAND
180/* nand device jffs2 lives on */
181#define CONFIG_JFFS2_DEV "nand0"
182/* start of jffs2 partition */
183#define CONFIG_JFFS2_PART_OFFSET 0x680000
184#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
185
186/* Environment information */
187#define CONFIG_BOOTDELAY 10
188
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000189#define CONFIG_BOOTFILE "uImage"
Srinath915162d2011-04-18 17:40:35 -0400190
191#define CONFIG_EXTRA_ENV_SETTINGS \
192 "loadaddr=0x82000000\0" \
193 "console=ttyS2,115200n8\0" \
Tom Rinia5a88212011-09-03 21:51:50 -0400194 "mmcdev=0\0" \
Srinath915162d2011-04-18 17:40:35 -0400195 "mmcargs=setenv bootargs console=${console} " \
196 "root=/dev/mmcblk0p2 rw " \
197 "rootfstype=ext3 rootwait\0" \
198 "nandargs=setenv bootargs console=${console} " \
199 "root=/dev/mtdblock4 rw " \
200 "rootfstype=jffs2\0" \
Tom Rinia5a88212011-09-03 21:51:50 -0400201 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
Srinath915162d2011-04-18 17:40:35 -0400202 "bootscript=echo Running bootscript from mmc ...; " \
203 "source ${loadaddr}\0" \
Tom Rinia5a88212011-09-03 21:51:50 -0400204 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
Srinath915162d2011-04-18 17:40:35 -0400205 "mmcboot=echo Booting from mmc ...; " \
206 "run mmcargs; " \
207 "bootm ${loadaddr}\0" \
208 "nandboot=echo Booting from nand ...; " \
209 "run nandargs; " \
210 "nand read ${loadaddr} 280000 400000; " \
211 "bootm ${loadaddr}\0" \
212
213#define CONFIG_BOOTCOMMAND \
Tom Rinia5a88212011-09-03 21:51:50 -0400214 "if mmc rescan ${mmcdev}; then " \
Srinath915162d2011-04-18 17:40:35 -0400215 "if run loadbootscript; then " \
216 "run bootscript; " \
217 "else " \
218 "if run loaduimage; then " \
219 "run mmcboot; " \
220 "else run nandboot; " \
221 "fi; " \
222 "fi; " \
223 "else run nandboot; fi"
224
225#define CONFIG_AUTO_COMPLETE 1
226/*
227 * Miscellaneous configurable options
228 */
229#define V_PROMPT "AM3517_CRANE # "
230
231#define CONFIG_SYS_LONGHELP /* undef to save memory */
232#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
233#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
234#define CONFIG_SYS_PROMPT V_PROMPT
235#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
236/* Print Buffer Size */
237#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
238 sizeof(CONFIG_SYS_PROMPT) + 16)
239#define CONFIG_SYS_MAXARGS 32 /* max number of command */
240 /* args */
241/* Boot Argument Buffer Size */
242#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
243/* memtest works on */
244#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
245#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
246 0x01F00000) /* 31MB */
247
248#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
249 /* address */
250
251/*
252 * AM3517 has 12 GP timers, they can be driven by the system clock
253 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
254 * This rate is divided by a local divisor.
255 */
256#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
257#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
258#define CONFIG_SYS_HZ 1000
259
260/*-----------------------------------------------------------------------
261 * Stack sizes
262 *
263 * The stack sizes are set up in start.S using the settings below
264 */
265#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
Srinath915162d2011-04-18 17:40:35 -0400266
267/*-----------------------------------------------------------------------
268 * Physical Memory Map
269 */
270#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
271#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
Srinath915162d2011-04-18 17:40:35 -0400272#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
273
Srinath915162d2011-04-18 17:40:35 -0400274/*-----------------------------------------------------------------------
275 * FLASH and environment organization
276 */
277
278/* **** PISMO SUPPORT *** */
279
280/* Configure the PISMO */
281#define PISMO1_NAND_SIZE GPMC_SIZE_128M
282#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
283
284#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
285 /* on one chip */
286#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
287#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
288
Luca Ceresoli6cbec7b2011-04-20 11:02:05 -0400289#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
Srinath915162d2011-04-18 17:40:35 -0400290
291/* Monitor at start of flash */
292#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
293
294#define CONFIG_NAND_OMAP_GPMC
295#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
296#define CONFIG_ENV_IS_IN_NAND 1
297#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
298
Luca Ceresoli6cbec7b2011-04-20 11:02:05 -0400299#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB sector */
300#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
301#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
Srinath915162d2011-04-18 17:40:35 -0400302
303/*-----------------------------------------------------------------------
304 * CFI FLASH driver setup
305 */
306/* timeout values are in ticks */
307#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
308#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
309
310/* Flash banks JFFS2 should use */
311#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
312 CONFIG_SYS_MAX_NAND_DEVICE)
313#define CONFIG_SYS_JFFS2_MEM_NAND
314/* use flash_info[2] */
315#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
316#define CONFIG_SYS_JFFS2_NUM_BANKS 1
317
Srinath915162d2011-04-18 17:40:35 -0400318#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
319#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
320#define CONFIG_SYS_INIT_RAM_SIZE 0x800
321#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
322 CONFIG_SYS_INIT_RAM_SIZE - \
323 GENERATED_GBL_DATA_SIZE)
Tom Rinid067cc42011-11-18 12:48:11 +0000324
325/* Defines for SPL */
326#define CONFIG_SPL
327#define CONFIG_SPL_NAND_SIMPLE
328#define CONFIG_SPL_TEXT_BASE 0x40200800
329#define CONFIG_SPL_MAX_SIZE (45 * 1024)
330#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
331
332#define CONFIG_SPL_BSS_START_ADDR 0x80000000
333#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
334
335#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
336#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
337#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
338#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
339
340#define CONFIG_SPL_LIBCOMMON_SUPPORT
341#define CONFIG_SPL_LIBDISK_SUPPORT
342#define CONFIG_SPL_I2C_SUPPORT
343#define CONFIG_SPL_LIBGENERIC_SUPPORT
344#define CONFIG_SPL_MMC_SUPPORT
345#define CONFIG_SPL_FAT_SUPPORT
346#define CONFIG_SPL_SERIAL_SUPPORT
347#define CONFIG_SPL_NAND_SUPPORT
348#define CONFIG_SPL_POWER_SUPPORT
349#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
350
351/* NAND boot config */
352#define CONFIG_SYS_NAND_5_ADDR_CYCLE
353#define CONFIG_SYS_NAND_PAGE_COUNT 64
354#define CONFIG_SYS_NAND_PAGE_SIZE 2048
355#define CONFIG_SYS_NAND_OOBSIZE 64
356#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
357#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
358#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
359 10, 11, 12, 13}
360#define CONFIG_SYS_NAND_ECCSIZE 512
361#define CONFIG_SYS_NAND_ECCBYTES 3
Tom Rinid067cc42011-11-18 12:48:11 +0000362#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
363#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
364
365/*
366 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
367 * 64 bytes before this address should be set aside for u-boot.img's
368 * header. That is 0x800FFFC0--0x80100000 should not be used for any
369 * other needs.
370 */
371#define CONFIG_SYS_TEXT_BASE 0x80100000
372#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
373#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
374
Srinath915162d2011-04-18 17:40:35 -0400375#endif /* __CONFIG_H */